An Efficiency Analysis of 27 Level Single-Phase Asymmetric Inverter without Regeneration

For medium voltage applications, multilevel inverters are used. One of its classic topologies is the Cascaded H-Bridge, which requires isolated DC voltages to work. Depending on the DC voltage ratio used in the Cascaded H-bridge can be classified into symmetric and asymmetric. In comparison between symmetric and asymmetric inverters, the latter can generate an AC output voltage with more output voltage levels. DC voltage ratio most documented are binary and trinary. The last can generate an AC voltage of 3n = 27 levels is obtained, using n = 3 inverters in cascade and NLM modulation, which generates a flow power of the load to the inverters (regeneration). This work analyzes the semiconductor losses (switching and conduction) and the THD of the AC output voltage in function of index modulation, considering a non-regenerative modulation technique for a 27-level single-phase asymmetric inverter. To confirm the theoretical analyzes, simulation and experimental results are shown.


Introduction
In applications for medium and high voltage drives, multilevel inverters are used [1,2]. By using low-voltage semiconductor devices, it is possible to generate any AC voltage [3]. The classic topologies within multilevel inverters are NPC [4], Clamped capacitor [5], and cascaded H-bridge (CHB) [6]. These topologies advantages are: (i) low distortion and low dv/dt AC voltage, (ii) low switching frequency, and (iii) low common-mode voltage [7].
Depending on the multilevel inverter's topology, the number of power cells or semiconductors used to achieve the desired number of AC voltage levels can be a problem. An option to solve the problem indicated above is the use of CHB, with different DC voltages, which is called an asymmetric inverter [8]. Depending on the DC voltage ratio, this relationship can be binary [9] or tertiary [10], the latter being the most documented.
Some advantages of asymmetric inverters are: (i) generates an AC output voltage with low THD (<3%), when DC voltage ratio is tertiary, 1:3:9, with a reduced number of power cells and suitable modulation technique [10,11], (ii) minimize the switching frequency of semiconductors devices, and (iii) use effectively use the blocking characteristics of each device used in the power converter [12].
Despite these significant advantages, asymmetric inverters have the following disadvantages: (i) many isolated DC sources are required, this will depend on the number of 3), and others are common of the power cell, as load parameters (ZL, RL, LL, θ) and load current IL.
The second step is mandatory to know the parameters of the semiconductor. In this case, IGBT is used in all power cells because the VDC values are not high (experimental results with low power prototype). These parameters are used to characterize the IGBT turn-on, IGBT turn-off, and diode turn-off.
The third step is to analyze the modulation technique used in the power converter. In particular is interesting to obtain the switching frequency device in function of index modulation. In asymmetric inverters, this parameter depends on the power cell because the firing pattern is not the same between them.
The fourth step is to analyze the modulation technique but considering the load that feeds. Assuming that the asymmetric inverter feeds an AC motor, the simplified steadystate behavior is represented as RL load. Thus, the conduction time inside the semiconductor device depends on the θ of the load. When the voltage and current load has the same sign, IGBT is on, but the voltage and current do not have the same sign; the diode is on.
In the fifth step, the energy dissipated is estimated in the semiconductor devices considering [26], and finally the sixth step, the efficiency is computed.
The summary methodology is depicted in Figure 2.  The manuscript is organized as follows; Section 2 explained the methodology used to computed the efficiency in 27 Levels Single-Phase Asymmetric Inverter without Regeneration, the Section 3 shows the topology used in this study. Section 4 analyzes the switching frequency in the semiconductor devices, which depends on the modulation technique used in each power cell. Then, Section 5 presents the semiconductors losses. These losses are divided into two: (i) switching losses and (ii) conduction losses; both depend on the semiconductors devices parameters, the operating point of each power cell, and the modulation technique. In Section 6, simulated results are displayed for steady-state and disturbances, and in Section 7, experimental results are presented. Finally, in Section 8, the conclusions of the work are explained.

Methodology
To estimate efficiency, based on semiconductors losses, in the 27 Level Single-Phase Asymmetric Inverter without Regeneration, it is necessary to know specific parameters and operating conditions of the power converter.
The first is necessary to know the operating point of the power converter and the topology. In this case, these variables depend on the power cell, V DCi , I DCi , v ai , (with i = 1, 2, 3), and others are common of the power cell, as load parameters (Z L , R L , L L , θ) and load current I L .
The second step is mandatory to know the parameters of the semiconductor. In this case, IGBT is used in all power cells because the V DC values are not high (experimental results with low power prototype). These parameters are used to characterize the IGBT turn-on, IGBT turn-off, and diode turn-off.
The third step is to analyze the modulation technique used in the power converter. In particular is interesting to obtain the switching frequency device in function of index modulation. In asymmetric inverters, this parameter depends on the power cell because the firing pattern is not the same between them.
The fourth step is to analyze the modulation technique but considering the load that feeds. Assuming that the asymmetric inverter feeds an AC motor, the simplified steady-state behavior is represented as RL load. Thus, the conduction time inside the semiconductor device depends on the θ of the load. When the voltage and current load has the same sign, IGBT is on, but the voltage and current do not have the same sign; the diode is on.
In the fifth step, the energy dissipated is estimated in the semiconductor devices considering [26], and finally the sixth step, the efficiency is computed.
The summary methodology is depicted in Figure 2. 3), and others are common of the power cell, as load parameters (ZL, RL, LL, θ) and load current IL. The second step is mandatory to know the parameters of the semiconductor. In this case, IGBT is used in all power cells because the VDC values are not high (experimental results with low power prototype). These parameters are used to characterize the IGBT turn-on, IGBT turn-off, and diode turn-off.
The third step is to analyze the modulation technique used in the power converter. In particular is interesting to obtain the switching frequency device in function of index modulation. In asymmetric inverters, this parameter depends on the power cell because the firing pattern is not the same between them.
The fourth step is to analyze the modulation technique but considering the load that feeds. Assuming that the asymmetric inverter feeds an AC motor, the simplified steadystate behavior is represented as RL load. Thus, the conduction time inside the semiconductor device depends on the θ of the load. When the voltage and current load has the same sign, IGBT is on, but the voltage and current do not have the same sign; the diode is on.
In the fifth step, the energy dissipated is estimated in the semiconductor devices considering [26], and finally the sixth step, the efficiency is computed.
The summary methodology is depicted in Figure 2.    Figure 1a, is shown the topology used for the asymmetric inverter. It is based on CHB, in this case, by 3 H-bridge inverters connected in cascade. Using equal DC voltages, the AC output voltage has seven levels. An alternative is to use different DC voltage ratios to obtain a greater number of voltage levels at the output AC voltage.

Topology
Using a 1: 3: 9 trinary type DC voltage ratio, v a (t) has 27 levels, obtaining a low THD. Commonly for this type of asymmetric inverter, the NLM modulation technique is used, which generates power flow between the power cells, Figure 3a, for specific values of the modulation index, regardless of the type of load it feeds [16][17][18][19]. The use of AFE rectifiers or dissipation resistors is necessary for specific applications, such as AC drives.  Figure 1a, is shown the topology used for the asymmetric inverter. It is based on CHB, in this case, by 3 H-bridge inverters connected in cascade. Using equal DC voltages, the AC output voltage has seven levels. An alternative is to use different DC voltage ratios to obtain a greater number of voltage levels at the output AC voltage.

Topology
Using a 1: 3: 9 trinary type DC voltage ratio, va(t) has 27 levels, obtaining a low THD. Commonly for this type of asymmetric inverter, the NLM modulation technique is used, which generates power flow between the power cells, Figure 3a, for specific values of the modulation index, regardless of the type of load it feeds [16][17][18][19]. The use of AFE rectifiers or dissipation resistors is necessary for specific applications, such as AC drives.  An alternative is the use of an asymmetric inverter with a trinary DC voltage ratio, 1:3:9, where the calculation of the αi is done by minimizing the THD of the AC voltage, Figure 1b, considering as limitation that the voltages of each inverter vai,1, i = 1, 2, 3, are greater than or equal to zero. Avoiding the existence of regeneration [24], Figure 3b, but obtaining an output voltage with low THD (<3.0% for m = 1.0), Figure 1c. This solution eliminates the flow of power between the power cells, simplifying the converter's topology and control.

Switching Losses
The switching process in semiconductor devices is not-ideal Figure 4, as shown in [27].   An alternative is the use of an asymmetric inverter with a trinary DC voltage ratio, 1:3:9, where the calculation of the α i is done by minimizing the THD of the AC voltage, Figure 1b, considering as limitation that the voltages of each inverter v ai,1 , i = 1, 2, 3, are greater than or equal to zero. Avoiding the existence of regeneration [24], Figure 3b, but obtaining an output voltage with low THD (<3.0% for m = 1.0), Figure 1c. This solution eliminates the flow of power between the power cells, simplifying the converter's topology and control.

Switching Losses
The switching process in semiconductor devices is not-ideal Figure 4, as shown in [27].  Figure 1a, is shown the topology used for the asymmetric inverter. It is based on CHB, in this case, by 3 H-bridge inverters connected in cascade. Using equal DC voltages, the AC output voltage has seven levels. An alternative is to use different DC voltage ratios to obtain a greater number of voltage levels at the output AC voltage.

Topology
Using a 1: 3: 9 trinary type DC voltage ratio, va(t) has 27 levels, obtaining a low THD. Commonly for this type of asymmetric inverter, the NLM modulation technique is used, which generates power flow between the power cells, Figure 3a, for specific values of the modulation index, regardless of the type of load it feeds [16][17][18][19]. The use of AFE rectifiers or dissipation resistors is necessary for specific applications, such as AC drives. An alternative is the use of an asymmetric inverter with a trinary DC voltage ratio, 1:3:9, where the calculation of the αi is done by minimizing the THD of the AC voltage, Figure 1b, considering as limitation that the voltages of each inverter vai,1, i = 1, 2, 3, are greater than or equal to zero. Avoiding the existence of regeneration [24], Figure 3b, but obtaining an output voltage with low THD (<3.0% for m = 1.0), Figure 1c. This solution eliminates the flow of power between the power cells, simplifying the converter's topology and control.

Switching Losses
The switching process in semiconductor devices is not-ideal Figure 4, as shown in [27].  In asymmetric inverters, the semiconductor device used in each power cell depends on the value of the DC voltage (blocking voltage) and the switching frequency, according to the switching pattern proposed by the modulation technique. Therefore, each power cell should have a different semiconductor device.
Due to the switches available for experimental results, only IGBTs are considered to analyze switching losses.
The losses in a switching period depend on the following factors: (i) the characteristics of the diode (reverse recovery time and current peak), (ii) characteristics of the IGBT (rise and fall time, tail time and tail current), and (iii) stray inductance. The diodes used in modern IGBTs are fast recovery diodes; thus, the losses due to switching on the diode are less than 1% compared to the losses due to switching off the diode [28]; they are neglected in the analysis. The loss estimation considers the IGBT switching on, the IGBT switching off, and the losses due to the diode switching off, as reviewed in [26].

Conduction Losses
In a semiconductor device, the conduction losses depend on the saturation voltage v sat , and the current flowing through it [29]. A first-order approximation is used to model the saturation voltage, considering threshold voltage V T , and series resistance R T , thus, Then, the average power dissipated in the conduction of the semiconductors at the fundamental frequency is given by, where I AVG corresponds to the average value of the current flowing through the semiconductor, and I RMS is the RMS value of the semiconductor current. Finally, the energy dissipated during a period is, where T COND is the conduction time of the semiconductor. In this work (3) is used to calculate conduction losses.

Switching Frequency
In each power cell of an asymmetric inverter, the output voltage is different, Figure 1b. This is to achieve full AC output voltage, with a high amount of levels and a low THD, Figure 1c. Due to this, the switching frequency of semiconductor devices is different for each power cell.
The switching frequency of a semiconductor device depends on the modulation index of the modulation technique. As the modulation index m decreases, the THD of the AC output voltage increases, Figure 5a. This is due to the disappearance of the firing angles α i ; they tend to a 90 • . Consequently, the inverter's levels of the total output voltage are decreasing.
The main inverter has a semiconductor device switching frequency (f swdev ) of 50 Hz, until m = 0.33; in the remaining two secondary inverters (named in this way for the power supply to the load), their switching frequencies will depend on the pattern of firing of semiconductors and index modulation, Figure 6. For the secondary inverters of 27-level single-phase inverter without regeneration, the second inverter has f swdev = 250 Hz, and for the third inverter, f swdev = 850 Hz, the indicated values are for m = 1.0, where the switching frequency is maximum, and THD is minimum, Figure 5b. The gating pattern for m = 1.0 is shown in Figure 6a. As indicated aforementioned, when m decreases, the switching frequency changes in the semiconductor device, in Figure 6b shown the gating pattern for m = 0.7. Similarly, the gating signal activates the semiconductor device, in this case, IGBT with diode in antiparallel, but the activation of one of these two will depend on the The main inverter has a semiconductor device switching frequency (fswdev) of 50 Hz, until m = 0.33; in the remaining two secondary inverters (named in this way for the power supply to the load), their switching frequencies will depend on the pattern of firing of semiconductors and index modulation, Figure 6. For the secondary inverters of 27-level single-phase inverter without regeneration, the second inverter has fswdev = 250 Hz, and for the third inverter, fswdev = 850 Hz, the indicated values are for m = 1.0, where the switching frequency is maximum, and THD is minimum, Figure 5b. The gating pattern for m = 1.0 is shown in Figure 6a. As indicated aforementioned, when m decreases, the switching frequency changes in the semiconductor device, in Figure 6b shown the gating pattern for m = 0.7. Similarly, the gating signal activates the semiconductor device, in this case, IGBT with diode in antiparallel, but the activation of one of these two will depend on the voltage's polarity the current in the load. If the polarity of the voltage and current load is the same, IGBT is on, otherwise the diode is turned on.
(a) (b)   The main inverter has a semiconductor device switching frequency (fswdev) of 50 Hz, until m = 0.33; in the remaining two secondary inverters (named in this way for the power supply to the load), their switching frequencies will depend on the pattern of firing of semiconductors and index modulation, Figure 6. For the secondary inverters of 27-level single-phase inverter without regeneration, the second inverter has fswdev = 250 Hz, and for the third inverter, fswdev = 850 Hz, the indicated values are for m = 1.0, where the switching frequency is maximum, and THD is minimum, Figure 5b. The gating pattern for m = 1.0 is shown in Figure 6a. As indicated aforementioned, when m decreases, the switching frequency changes in the semiconductor device, in Figure 6b shown the gating pattern for m = 0.7. Similarly, the gating signal activates the semiconductor device, in this case, IGBT with diode in antiparallel, but the activation of one of these two will depend on the voltage's polarity the current in the load. If the polarity of the voltage and current load is the same, IGBT is on, otherwise the diode is turned on.

Steady-State Analysis
The asymmetric inverter of 27-level single-phase inverter without regeneration is analyzed, simulated in PSIM 2020a ® [30]. The simulation's schematic is shown in Figure 7, and the parameters are shown in Table 1, and the values of the α i used are presented in Table 2.

Steady-State Analysis
The asymmetric inverter of 27-level single-phase inverter without regeneration is analyzed, simulated in PSIM 2020a ® [30]. The simulation's schematic is shown in Figure 7, and the parameters are shown in Table 1, and the values of the αi used are presented in Table 2.  In Figure 8a is shown va(t). This voltage has 27 levels, with a THD of 3%. The load current is highly sinusoidal with a THD less than 1.0%. The spectrum harmonic of the load voltage is shown in Figure 8b, where the harmonics' amplitude does not exceed 1.0%. Figure 8c shows the output voltage in each power cells vai(t); these are in phase allowing the harmonics generated by them to cancel each other, not appearing in the load voltage va(t); this condition is imposed by the THD minimization algorithm [24]. The above can be verified by Figure 8b,d.   Figure 8a is shown v a (t). This voltage has 27 levels, with a THD of 3%. The load current is highly sinusoidal with a THD less than 1.0%. The spectrum harmonic of the load voltage is shown in Figure 8b, where the harmonics' amplitude does not exceed 1.0%. Figure 8c shows the output voltage in each power cells v ai (t); these are in phase allowing the harmonics generated by them to cancel each other, not appearing in the load voltage v a (t); this condition is imposed by the THD minimization algorithm [24]. The above can be verified by Figure 8b,d.
To check the modulation technique proposed in [24], it is simulated again for m = 0.7. The output voltage v a (t) is shown, Figure 9a, which has 17 levels, a low harmonic content with a THD of 5.3% Figure 9b, and the load current is sinusoidal with a low THD of 1.3%. The NLM modulation technique presents current circulation between the inverters with lower DC link voltage [16][17][18][19], Figure 3a; this is because the phase between the voltage and the load current are 180 • out of phase, even though the load is purely resistive. In the case To check the modulation technique proposed in [24], it is simulated again for m = 0.7. The output voltage va(t) is shown, Figure 9a, which has 17 levels, a low harmonic content with a THD of 5.3% Figure 9b, and the load current is sinusoidal with a low THD of 1.3%. The NLM modulation technique presents current circulation between the inverters with lower DC link voltage [16][17][18][19], Figure 3a; this is because the phase between the voltage and the load current are 180° out of phase, even though the load is purely resistive. In the case of the analyzed technique [21], the inverter does not present current circulation between the inverters, Figure 9c; this agrees with what is shown in Figure 3b. It can be appreciated, the value of the fundamental is zero for v a2 (n) and v a3 (n) for the value of m = 0.7, Figure 9d; this is imposed by the modulation technique proposed in [24]. With this, it is avoided that the asymmetric inverter's secondary power cells have a power flow between them. Avoiding regeneration.
For the analysis of semiconductor losses, the IRG4BC20UDPBF IGBT switch [31] is considered. IGBTs are subjected to different dc voltages due to the voltage ratio used. This also determines the type of output voltage that they will generate, defining the switching frequency of the IGBTs.
The 27-level single-phase asymmetric inverter without regeneration has an efficiency of 96.22% for m = 1.0 and load power factor 0.8(i), with a THD of v a (t) of 3%, considered the values shown in Tables 1 and 2. The semiconductor losses distribution in Figure 10a is shown for the conditions listed above. It extends the previous analysis for the entire range of the modulation index 0.0 < m < 1.0, but the same load, Figure 10b. It is appreciated that the 27 levels single-phase asymmetric inverter without regeneration for a range 0.8 < m < 1.0, the output voltage has a THD < 5%, with an efficiency close to 96%. It can be appreciated, the value of the fundamental is zero for va2(n) and va3(n) for the value of m = 0.7, Figure 9d; this is imposed by the modulation technique proposed in [24]. With this, it is avoided that the asymmetric inverter's secondary power cells have a power flow between them. Avoiding regeneration.
For the analysis of semiconductor losses, the IRG4BC20UDPBF IGBT switch [31] is considered. IGBTs are subjected to different dc voltages due to the voltage ratio used. This also determines the type of output voltage that they will generate, defining the switching frequency of the IGBTs.
The 27-level single-phase asymmetric inverter without regeneration has an efficiency of 96.22% for m = 1.0 and load power factor 0.8(i), with a THD of va(t) of 3%, considered the values shown in Table 1 and Table 2. The semiconductor losses distribution in Figure  10a is shown for the conditions listed above. It extends the previous analysis for the entire range of the modulation index 0.0 < m < 1.0, but the same load, Figure 10b. It is appreciated that the 27 levels single-phase asymmetric inverter without regeneration for a range 0.8 < m < 1.0, the output voltage has a THD < 5%, with an efficiency close to 96%.

Analysis before Disturbances
In an AC electrical system, voltage variations are allowed within a range of ±10%, where the equipment must be work. In applications such as AC drives, the DC voltage link can have a ripple; this depends on several factors, such as the power converter's topology, the DC capacitor's size, the type of load fed, and the operating point of the power converter [32].

Analysis before Disturbances
In an AC electrical system, voltage variations are allowed within a range of ±10%, where the equipment must be work. In applications such as AC drives, the DC voltage link can have a ripple; this depends on several factors, such as the power converter's topology, the DC capacitor's size, the type of load fed, and the operating point of the power converter [32].
Variations in AC voltage supply affect the DC voltage link in power cells. This dramatically affects the modulation technique analyzed in this work, not allowing the generation of the different output voltage levels, increasing its THD. We focus on analyzing how the DC voltage variation affects the efficiency of the 27 levels single-phase asymmetric inverter without regeneration.
As can be seen in Figure 11a, the DC voltage variation is ±10% [33], for a value of m that varies between 0.0 < m < 1.0. Despite the DC voltage variation in the power cells, the asymmetric inverter's efficiency, for the same value of m, does not change more than 0.5%. This is because this variation mainly affects switching losses, which are not very significant regarding conduction losses for the modulation technique analyzed. Additionally, it should be considered that conduction losses are of greater importance for the modulation technique analyzed in this work, compared to switching losses.

Experimental Results
Finally, to verify what was theoretically exposed, a low-power experimental prototype was implemented. The schematic is very similar, shown in Figure 7. The parameters of the experimental results are shown in Table 3. The DSP TMS320C6713 is used to generate the firing pulses to activate the IRG4BC20UDPBF IGBT switch [31]. Unlike other jobs that use a look-up table. The authors use a polynomial approximation of the seventh degree to obtain the firing angles, which depends on the modulation index and the desired phase angle.  Figure 12 is depicted the experimental results for m = 1.0. The output voltage va(t), has a THD of 3.45%, and the load current ia(t) is almost sinusoidal with a THD < 2%, Figure 12a. The voltage and current load is very similar to that shown in Figure 8a. The harmonic spectrum of va(t) is the depicted in Figure 12b, this has low-frequency harmonics, but amplitude is less than 2%. Compared with Figure 8b, it is slightly different due to the sampling time used, TS = 50 [µS]. With this TS, the amount of points for a period On the other hand, a variation of the load power factor that can supply this 27 levels single-phase asymmetric inverter without regeneration is analyzed for any value of m between 0.0 < m < 1.0, Figure 11b.
The lowest efficiency is when the inverter feeds a pure resistive load, the worst case is an efficiency of 91.81% and improves as the load has more inductive. This behavior is explained below.
Depending on the load power factor, there are instances of time where each power cell's output voltage does not have the same polarity as the load current. This generates that the IGBT does not conduct for these moments, but rather its diode connected in antiparallel. According to the datasheet parameters, it consumes less energy in its conduction state than the IGBT [31].
Additionally, it should be considered that conduction losses are of greater importance for the modulation technique analyzed in this work, compared to switching losses.

Experimental Results
Finally, to verify what was theoretically exposed, a low-power experimental prototype was implemented. The schematic is very similar, shown in Figure 7. The parameters of the experimental results are shown in Table 3. The DSP TMS320C6713 is used to generate the firing pulses to activate the IRG4BC20UDPBF IGBT switch [31]. Unlike other jobs that use a look-up table. The authors use a polynomial approximation of the seventh degree to obtain the firing angles, which depends on the modulation index and the desired phase angle.  Figure 12 is depicted the experimental results for m = 1.0. The output voltage v a (t), has a THD of 3.45%, and the load current i a (t) is almost sinusoidal with a THD < 2%, Figure 12a. The voltage and current load is very similar to that shown in Figure 8a. The harmonic spectrum of v a (t) is the depicted in Figure 12b, this has low-frequency harmonics, but amplitude is less than 2%. Compared with Figure 8b, it is slightly different due to the sampling time used, T S = 50 [µS]. With this T S , the amount of points for a period is 400, with a resolution of 0.9 • , affecting the firing pulses for semiconductor devices. Then, the individual voltages v ai (t) and load current i a (t) are depicted in Figure 12c; these are similar are shown in Figure 8c. As the asymmetric inverter feeds an RL load with a power factor of 0.8 (i), in some instances, the load current and individual voltages have not the same polarity; with this, the antiparallel diode in the IGBT is turned on. Thus, the diode's forward voltage is significant concerning V DC2 and V DC3 , Table 3, generating an offset DC in v a2 (t) and v a3 (t). Finally, Figure 12d shown the harmonic spectrum of the individual voltages v ai (t); these are similar to the ones shown in Figure 8d. The second test is for m = 0.7, where the NLM strategy presents regeneration for 27 levels asymmetric inverter, and the analyzed technique does not. Figure 13a shows the output voltage va(t) and load current ia(t), which is similar to the one shown in Figure 9a, va(t) has 17 levels and low harmonic content with a 6.5% THD. The harmonic spectrum of va(t) in Figure 13b, is similar at shown in Figure 9b. As mentioned above, the difference   The second test is for m = 0.7, where the NLM strategy presents regeneration for 27 levels asymmetric inverter, and the analyzed technique does not. Figure 13a shows the output voltage v a (t) and load current i a (t), which is similar to the one shown in Figure 9a, v a (t) has 17 levels and low harmonic content with a 6.5% THD. The harmonic spectrum of v a (t) in Figure 13b, is similar at shown in Figure 9b. As mentioned above, the difference between the simulated and experimental results is due to the resolution of 0.9 • by point. The individual voltages v ai (t) and load current i a (t) are depicted in Figure 13c; the phase shift present between the voltage and current is due to the load power factor. In this case, the NLM approach presents a circulating current, creating regeneration in the lower DC voltage inverters. Figure 13d shows the experimental spectra of v a1 (n), v a2 (n) and v a3 (n), where the fundamental component of v a2 (n) and v a3 (n) is zero. On the other hand, the diode voltage drop in the IGBT is significant, due to the low DC voltages used in the experimental setup. Generating a slight displacement in v a2 (t) and v a3 (t). Despite the above, the modulation technique avoids power flow between the power cells with lower DC voltage.

Conclusions
An efficiency analysis has been performed to 27-level single-phase asymmetric inverter without regeneration, including THD of the output voltage. The analysis considers THD of the output voltage va(t) and the semiconductors losses as a function of the modulation index, DC voltage variation, and load power factor variation.
The 27 levels single-phase asymmetric inverter without regeneration for m = 1.0 and load power factor 0.8(i), has an efficiency η = 96.22%, with a THD of va(t) 3%. Considering a wider modulation index range, 0.8 < m < 1.0, the efficiency is near (η ≈ 96%) with a THD of va(t) < 5%. Furthermore, the analysis shows that when faced with variations in each power cell's DC voltage, the efficiency does not changes much. The opposite case is with

Conclusions
An efficiency analysis has been performed to 27-level single-phase asymmetric inverter without regeneration, including THD of the output voltage. The analysis considers THD of the output voltage v a (t) and the semiconductors losses as a function of the modulation index, DC voltage variation, and load power factor variation. The 27 levels single-phase asymmetric inverter without regeneration for m = 1.0 and load power factor 0.8(i), has an efficiency η = 96.22%, with a THD of v a (t) 3%. Considering a wider modulation index range, 0.8 < m < 1.0, the efficiency is near (η ≈ 96%) with a THD of v a (t) < 5%. Furthermore, the analysis shows that when faced with variations in each power cell's DC voltage, the efficiency does not changes much. The opposite case is with variations in the load power factor, where the efficiency can vary up to 5%, the worst case being an efficiency of 91.81% for m = 0.01.
With this background, the 27-level single-phase asymmetric inverter, with a modulation technique that prevents the flow of power between its power cells, is a good alternative for low and medium voltage applications, thanks to its high efficiency and output voltage with high quality. Data Availability Statement: Data available on request due to restrictions privacy. The data presented in this study are available on request from the corresponding author.