Attenuation of Zero Sequence Voltage Using a Conventional Three-Wire Dynamic Voltage Restorer

Voltage sags/swells and harmonics are recurring problems in electric energy distribution systems. In order to solve these issues, several dynamic voltage restorer (DVR) topologies, such as the conventional three-wire DVR, have been proposed in the literature. Despite its capability of mitigating voltage disturbances, many researchers have established that conventional three-wire DVR cannot compensate for zero sequence voltage disturbances. In this paper, an in-depth study of the conventional three-phase DVR is presented, which shows that this DVR topology can also be used to attenuate zero sequence voltage components without increasing control complexity. The necessary conditions for this to occur are discussed in details and a brief comparison between the conventional three-wire DVR and other DVR topologies that can compensate for zero sequence voltage disturbances is made. Experimental results are included to validate the theoretical study.


Introduction
Due to the advance of microelectronics, sensitive power electronics devices have been increasingly used in all types of industries. The emergent use of such devices motivated discussions about power quality issues, which resulted in researches on solutions that could mitigate them. In this scenario, the dynamic voltage restorer (DVR) was proposed to compensate for momentary voltage disturbances and has been intensively studied in recent decades [1][2][3][4][5][6].
The DVR is a custom-made series active compensator, which means it works as a dependent voltage source placed in series with the supply grid [4]. Thus, with the proper reference generator, the DVR is capable of generating voltages with the same magnitude, but opposite phase angle, of the grid voltage disturbances (such as harmonic contamination and voltage sags). As exemplified in Figure 1 for a three-phase system, a typical topology of DVR is composed of: an energy storage system or a single DC power source (replaced by a DC bus capacitor in Figure 1); a voltage source inverter (VSI); an output filter; and an injection transformer [7].
Regarding the state of the art, the power converter topologies that are mostly used in three-phase DVRs are [6]: two-level (three-wire) inverters; two-level (four-wire) inverters with split-capacitor; four-leg (four-wire) inverters; and three single-phase H-bridge inverters [8][9][10][11]. These DVR topologies are typically used in low-voltage grid applications due to the simplicity of their modulation methods and due to their lower costs when compared to multilevel solutions. As the grid voltages are raised to medium-voltage level, the two-level topologies mentioned above become disadvantageous due to the voltage and currrent limitations of their semiconductor switches. Alternative options for medium-voltage grid application are [6]: using series-parallel associations of semiconductor switches to increase their maximum blocking voltages and operating currents; or using multilevel inverters [12][13][14]. However, regardless of the DVR topology used, the solutions for medium-voltage can still be classified into three-wire or four-wire.
When focusing on voltage sags/swells that contain zero sequence components, e.g., a single-phase sag [15,16], it is established in the literature that a three-phase three-wire DVR (Figure 1), such as the scheme based in a two-level inverter, which is referred as conventional DVR in this paper, cannot compensate for these disturbances. As consequence, several authors have proposed new DVR topologies to solve this problem, such as the threephase four-wire DVR with split capacitors and the four-leg DVR [6,16], both mentioned in the previous paragraph.
In this scenario, this paper presents an in-depth analysis of the conventional threewire DVR. The contribution is not proposing any new DVR topology, but demonstrating that, differently from the usual assumption, three-phase three-wire DVRs can be used to compensate unbalanced voltage sags/swells (having zero-sequence component). Further, the limitations of this compensation are discussed. This is an important issue, since this topology is the most economical choice and could be applied in many practical situations. Experimental results are included to validate the theoretical study. To the best of the authors' knowledge, the analysis presented here has not been presented in any other publication, being an original contribution of this paper.  Figure 1 shows a conventional three-wire DVR topology with a single DC bus capacitor, where v dvr_a , v dvr_b and v dvr_c are the voltages synthesized by the DVR. The parameters R t , L t and Z m represent the total winding resistance, total leakage inductance and magnetizing impedance of the injection transformers, respectively, all referred to the transformers' secondary side.

Evaluation of the Zero Sequence Component in Three-Phase Circuits with a Conventional DVR
Based on the topology presented in Figure 1, the attenuation of zero sequence voltage is discussed below. Since the switch S x is considered closed for the following analysis, the neutral point of capacitors C f is connected to the neutral point of the transformers. The reader should notice that the switch S x is only being used to show the options of filter connection of the conventional DVR evaluated in this paper.

Evaluation of Zero Sequence Component in the Load Voltages When Using a Conventional DVR
Considering the compensation provided by the DVR shown in Figure 1, the load voltages become where are vectors whose elements are the load, grid and DVR voltage phasors, respectively. However, based on the symmetrical components theory, the zero sequence component of a three-phase signal can be obtained using the following equation: Therefore, the equation that relates the zero sequence load voltage ( V l0 ) with the zero sequence grid voltage ( V g0 ) can be written by Considering that the neutral points of grid and load are connected together, then the currents i la , i lb and i lc may contain homopolar component. If this happens, since the switch S x is considered closed in this analysis, the zero sequence currents that circulate through the primary windings of the injection transformers will also be present in their secondary windings, being part of I dvr_a , I dvr_b and I dvr_c . Thus, In view of the fact that a three-wire inverter is unable to supply zero sequence currents, i.e., I f a + I f b + I f c = 0, the following relation holds when considering a high magnetizing impedance: ( I dvr_a + I dvr_b + I dvr_c ) = ( I ca + I cb + I cc ) = 3n I l0 , (4) in which I l0 is the homopolar component of the load currents and n is the turns ratio of the injection transformers. The voltage phasor at the primary winding of one injection transformer ( V dvr_a , V dvr_b or V dvr_c ) can be obtained, using the transformer's approximate equivalent circuit (indicated in blue in Figure 1), by summing the voltage over the converter filter capacitor C f with the voltage drop in the transformer impedance, but taking the injection transformer turns ratio into account. Thus, Thus, when considering the definition of zero sequence component presented in (2), the following equation is obtained: which can be rewritten as It should be noted that (7) considers injection transformers with same R t and L t . Equation (7) can be substituted into (3) to allow V l0 to be calculated in terms of the load impedance and the DVR's parameters. For example, if the load is balanced, (Z la = Z lb = Z lc = Z l = R l + jωL l ), then I l0 = V l0 /Z l and it becomes possible to rewrite (7) as Since unbalanced three-phase power systems can always be analyzed using symmetrical components [17], the zero sequence grid voltage ( V g0 ) can always be calculated. This means that (8) will be valid no matter the type of sags/swells present in the grid voltages (three-phase, two-phase, single-phase or two-phase-to-ground).
As presented in [16], none of the terms in (8) can be controlled by the converter. This means that a zero sequence disturbance in the grid voltage cannot be compensated by the DVR of Figure 1 and a homopolar voltage component would also appear in the load voltages. This restriction led researchers to seek alternatives that would make it possible to compensate V l0 .
The use of a three-phase four-wire DVR with split capacitors in the DC-bus is a widespread solution to mitigate the zero sequence load voltage. In fact, when modeling the three-phase circuit for this solution ( Figure 2) it is possible to obtain the following equation [16]: Equation (9) shows that the zero sequence load voltage can be eliminated when ωC f V g0 = jn I f 0 . In this case, the necessary zero sequence current i f 0 can be imposed by controlling i f a , i f b and i f c , what makes it possible to mitigate V l0 .
Another well-known solution to this problem is the four-leg DVR topology, which is shown in Figure 3. The fourth leg of this strategy allows the circulation of the homopolar current i 0 , which means that the steady-state mathematical model of the four-leg DVR topology also results in (9). Thus, once again, V l0 can be attenuated through the proper control of i f 0 , by means of imposing the appropriate values of the DVR's currents i f a ,  However, when re-evaluating the conventional three-wire DVR with S x closed ( Figure 1), (8) can be rewritten as

3-phase 4-wire DVR with split capacitors
Thus, if |Z t + Z c | |Z l | then it becomes possible to significantly attenuate V l0 without needing to use any of the solutions described above. If the magnetizing impedance of the injection transformers (Z m ) is included in this analysis, Equation (10) becomes which means that the condition to significantly attenuate V l0 becomes |Z t + Z c //Z m | |Z l |. Equation (11) is valid no matter the type of sags/swells present in the grid voltages (threephase, two-phase, single-phase or two-phase-to-ground), showing the ability of strongly attenuating the zero-sequence load voltage. Besides that, (11) also demonstrates that there is a positive correlation between the zero-sequence grid and load voltages, meaning that the zero-sequence load voltage tends to decrease as the zero-sequence grid voltage decreases.
As a matter of fact, since i f a , i f b and i f c only contain positive and negative sequence currents, the zero sequence equivalent circuit of the electrical diagram in Figure 1 does not include the three-phase inverter and the inductors L f . Then, when evaluating the effect of connecting the common points of the AC capacitors and of the injection transformers, it should be noted that: The zero sequence equivalent circuit of the electrical diagram in Figure 1 will include the capacitor C f . Thus, the zero sequence equivalent impedance becomes the series association of: the load (Z l ); the series impedance of the injection transformers (Z t ); and the RLC parallel impedance formed by Z c //Z m . • The AC filter capacitors and inductors are responsible for filtering out the high frequency harmonic components (switching frequency and its multiples) present in the injected voltages. For the filter design, it must be observed that the capacitance C f , inductance L f , switching frequency of the DVR's inverter and bandwidth of the control system are all correlated [18]. Thus, the AC capacitors must be designed to behave almost like open circuits at fundamental frequency while providing a low-impedance path for switching frequency signals. Consequently, it is expected that |Z t + Z c //Z m | |Z l | holds for a certain range of frequencies, making it possible to attenuate zero sequence voltage disturbances in this range of frequencies.
The zero sequence equivalent circuit of the electrical diagram in Figure 1 won't include the capacitor C f . Therefore, Equation (11) would become: This means that the condition to significantly attenuate V l0 becomes |Z t + Z m | |Z l |, resulting in a larger zero sequence attenuation range than that obtained if S x is closed. • Since the injection transformers generally have high magnetizing impedance, the conventional DVR is capable of attenuating low-frequency zero sequence voltage components whether the switch S x is open or closed. As consequence, depite of the fact that the conventional DVR does not allow the use of single-phase loads, feature that is common to all three-wire DVRs, this solution still can attenuate singlephase sags/swells.

Comparison with Other Usual DVR Topologies
The main advantages of using the conventional DVR over other usual DVR topologies are presented below.

Three-Phase Four-Wire DVR with Split Capacitors
In this topology (Figure 2), the zero sequence current that flows through the mid-point of the DC bus can be controlled. On the other hand, when compared to the conventional DVR, this configuration creates a coupling between the DC and AC sides of the VSI, which causes resonance problems and an additional ripple on the DC bus [16]. This ripple can be attenuated by using larger dc bus capacitors [16]. Besides that, the zero sequence component and the voltage unbalance on the DC bus capacitors must be considered during the control system design.
Therefore, the proper design of the output filter of the conventional DVR avoids the problems described above, making it an attractive solution.

Four-Leg DVR Topology
In this topology (Figure 3), the VSI has a fourth leg that is connected to the common points of the AC capacitors and the injection transformers. By doing so, it enables the circulation of zero sequence current through the DVR while decouples the DC and AC sides of the VSI. However, this new leg demands two additional switches. The zero sequence component and the switching of the forth leg must be considered during the control system design, resulting in additional complexity.
The conventional DVR requires less semiconductor devices and demands less computational effort than the four-leg DVR does. Thus, the conventional DVR still is an attractive solution.

Three-Phase DVR Using Three Single-Phase H-Bridge Inverters
In this topology, an H-bridge is used to generate the DVR voltage over each injection transformer. Therefore, each phase operates independently to compensate for unbalanced voltage disturbances.
An important advantage of the H-bridge based topology over the conventional DVR is that it has higher maximum compensation capability [11]. On the other hand, this strategy requires twice as many semiconductor switches as the conventional DVRs does [11]. Despite the versatility of the H-bridge based topology, its high cost is a major disadvantage, and may even justify not choosing this topology in many situations.

Experimental Results
A prototype containing the three-phase circuit shown in Figure 1 was used to validate the theoretical analysis presented in Section 2. The parameters of the prototype are shown in Table 1. In this table, R f is the inherent resistance of inductors L f . Resistors R c (not included in Figure 1) are used in series with capacitors C f for current limitation purpose. A DC power source was used to supply the DC bus voltage V dc . Regarding the control system, the DVR's controllers and the reference generation were implemented in a dSPACE plataform, model DS1005, featuring a processor running at 1 GHz [19]. The block diagram of the complete control system is shown in Figure 4. This control system was implemented considering: a fast inner current loop, for controlling the VSI output currents; and a slow outer voltage loop, for controlling positive and negative sequence voltages that must be synthesized over C f . Both control loops were implemented in a dq reference frame aligned with the fundamental frequency grid voltage. As shown in Section 2, the conventional DVR could passively attenuate zero sequence voltage components of low-frequency, thus, as shown in Figure 4, no controller was required for compensating these disturbances.
In this scenario, Figure 5a shows the grid, load and DVR voltages in the occurrence of a single-phase sag of 30%. From Figure 5a, it can be seen that the conventional DVR could attenuate single-phase voltages sags, which contained zero sequence components, as stated in the previous section.
As the load became lighter, the condition |Z t + Z c // Z m | |Z l | is compromised. Consequently, it is expected that the conventional DVR will have its ability of attenuating zero sequence voltage component also compromised. In order to confirm this fact, the DVR used for obtaining the results shown in Figure 5a was simulated to attenuate a singlephase sag, but now considering four different loads ( Table 2). The data shown in Table 2 were obtained through simulation results in an attempt to achieve a comparison free of disturbances, such as harmonics, unbalanced grid voltages during pre-fault condition or unbalanced load condition.  Figure 4. Block diagram of the complete control system used to evaluate the ability of the conventional DVR of attenuating zero-sequence voltages.
Results for a load impedance of 10 p.u. As can be seen in Table 2, the reduction in the zero sequence load voltage decreased as the load impedances increased. However, this reduction was still relevant for loads with impedance around 10 p.u. (apparent power around 0.1 p.u.). This happened because the magnetizing impedance and the AC filter capacitors had high impedances at the frequency of the zero sequence components to be compensated. In order to illustrate this aspect through experimental results, Figure 5b-d show the grid, load and DVR voltages in the occurrence of a single-phase sag of 30% for load impedances of 2 p.u., 5 p.u. and 10 p.u., respectively. It should be noted that the waveforms of grid voltages in the laboratory used to obtain experimental results contained some harmonic components. Although these components were less evident in the grid voltage waveforms, they could be easily recognized in the correction voltage (injected by the DVR), due to its lower magnitude.
Since capacitive and inductive impedances depended on the frequency, the conditions |Z t + Z c // Z m | |Z l | (for S x closed) and |Z t + Z m | |Z l | (for S x opened) only held for a certain range of frequencies. In order to evaluate this issue, these conditions were approximated by |Z t + Z c //Z m | > 10 × |Z l | (for S x closed) and |Z t + Z m | > 10 × |Z l | (for S x opened) in the following analysis. Therefore, Figures 6 and 7 show the evaluation of the zero sequence attenuation range for a conventional DVR with the parameters shown in Table 1. As discussed in the Section 2.1, a larger zero sequence attenuation range was obtained if S x was opened.
In order to extend the analysis presented in the previous paragraph, Figures 8 and 9 show the evaluation of the zero sequence attenuation range for a conventional DVR with the parameters shown in Table 1, but now considering RL loads (|Z l | = Z base and PF = 0.8). For this new scenario, S x opened still led to a larger zero sequence attenuation range, as expected. Since the attenuation range of all four scenarios presented in Figures 6-9 covered the fundamental frequency (60 Hz), single-phase sags/swells would be attenuated by using a conventional three-wire DVR for all four scenarios.  Considering no load operation, the conventional DVR lost the ability of attenuating zero sequence voltages. In this scenario, there would be no zero sequence current circulating in the injection transformers, therefore, no zero sequence voltage would be seen over the capacitors C f . This result is in accordance with (11) and (12) for Z l tending to infinite.

Comparative Study between the DVR Topologies Discussed in This Paper
The three DVR topologies that have been discussed in this paper (Figures 1-3) are compared in this subsection. For this purpose, simulation results and technical aspects that differentiate these three topologies are used (Table 3). Table 3. Summary of the comparative study of the DVR topologies discussed in this paper (simulation results).

DVR Topology
Conventional Three-Wire DVR (Figure 1) Three-Phase Four-Wire DVR with Split Capacitors (Figure 2) Four-Leg DVR Topology ( Figure 3) As can be seen in Table 3, the conventional DVR did not require dedicated controller for attenuation of zero sequence voltage, did not couple the DC and AC sides of the DVR's inverter, and demanded fewer power semiconductor devices than the other evaluated DVR topologies. These features highlight the economical advantage of using the conven-tional DVR in applications where it can be used, what emphasizes the importance of this paper's contribution.

Reduction in the zero
However, before choosing the conventional DVR for an application in which the grid voltages may contain zero sequence components, the engineer must evaluate the electrical system in order to determine the DVR's zero sequence attenuation range (as done in Figures 6-9). In fact, depending on the load impedance, the conventional DVR can lead to a reduction in the zero sequence load voltage similar to the four-wire DVR topologies evaluated in this paper (second row of Table 3), which is an advantageous scenario of use of the conventional DVR.

Attenuation of Zero Sequence Voltage for Other Faults Using a Conventional DVR
As stated in Section 2, the conventional DVR can attenuate zero sequence voltages no matter the type of sags/swells present in the grid voltages (three-phase, two-phase, single-phase or two-phase-to-ground). This characteristic was evaluated in simulation for different faults, as indicated in Table 4 and shown in Figure 10.
(f) Two-phase-to-ground short-circuit. As can be seen in Table 4, different faults may lead to different amplitudes of zero sequence grid voltage. However, despite this fact, since all evaluated voltage disturbances were applied to the same electrical circuit, the circuit impedances were the same, which led to: Equation (13) indicates that the conventional DVR reduces the zero sequence load voltage ( V l0 ) by a constant factor, regardless of the amplitude of the zero sequence grid voltage ( V g0 ). This feature can also be seen in the last row of Table 4. Table 4. Summary of the attenuation of zero sequence voltage for different faults being applied to the grid voltages (simulation results).

Conclusions
The great majority power converters used in three-phase DVRs are the three-leg three-wire converter (called conventional topology in this paper), three-leg four-wire split capacitor converter, four-leg converter and three full-bridge single-phase converters. Despite being the simplest and less expensive of them, the conventional topology has been avoided whenever it is necessary to compensate for unbalanced sags/swells, which have zero-sequence component. In this paper, it is shown that, differently from the usual assumption, three-phase DVRs using the conventional topology can be used to compensate unbalanced voltage sags/swells. The theoretical analysis presented shows that the injection transformer zero-sequence current must flow through the parallel association of its magnetizing impedance and of the converter filter capacitor. Once these impedances must be high in the fundamental frequency, it is demonstrated that the zero-sequence load voltage becomes greatly attenuated. It was observed that the ability of the conventional topology to attenuate unbalanced sags/swells is reduced for very low power loads. The mathematical conclusions are validated through experimental and simulation results, considering several types of sags and swells and comparing the response of the conventional and other types of topologies. Further, it is shown how the AC filter capacitors can be tunned so that the parallel resonance between the capacitive reactance and the magnetizing impedance of the injection transformers results in maximum impedance around a frequency of interest, improving the zero sequence attenuation at that frequency.

Data Availability Statement:
No new data were created or analyzed in this study. Data sharing is not applicable to this article.