Variable Speed Drive DC-Bus Voltage Dip Prooﬁng

: This paper proposes a power electronic module that uses a switched capacitor for retaining the integrity of the dc-link voltage of a variable speed drive (VSD) during a 0.2 s short-term power interruption (STPI). Ride-through was achieved through switched capacitor onto the dc bus. However, this technique presents a challenge of the high inrush currents during a ride through compensation. In this work both analytical and experimental investigations were conducted in order to reduce the in-rush currents and its impact on the performance of the VSD during the STPI. Inrush peak currents were reduced by approximately 90%. Experimental results showed torque pulsations of 12.8% and 14.3% at the start and end of dc-link voltage compensation, respectively. A method for sizing the switched capacitor and the inrush limiting resistors is proposed. This methodology is based on the use of readily available nameplate information of the VSD and the electric motor. The proposed module can be retroﬁtted to existing VSDs that are based on v/f control.


Introduction
Electricity supply in developing economies is characterized by low generation and dominated by frequent faults and outages owing to lack of financial resources, old infrastructure and poor maintenance [1][2][3]. Voltage dip sensitive equipment including variable speed drives (VSD) are negatively affected by such frequent faults and outages leading to voltage dip-related trips. This results in disruptions of critical processes, loss of production and revenue [4]. Various transmission grid codes have a common way of defining which grid disturbances have to be tolerated. They also specify frequency of occurrence of these disturbances. VSDs are used to drive critical processes in power generation equipment and they are required to be able to ride-through a 0.2 s short-term power interruption (STPI) [5,6]. Studies carried out by numerous researchers to analyse the behaviour of a VSD during a voltage dip, have identified the dc-link under voltage as the main reason for the VSD tripping during a voltage dip [7][8][9]. There is an abundant number of VSDs on the market of different makes and models which gives rise to differences in susceptibility and response to voltage dips and STPI [9]. Existing VSD topologies can be modified to enhance their ride-through capability. Most modifications to existing topologies would require close collaboration with different manufacturers to access design base technical information. Such arrangements present challenges due to intellectual property which is closely guarded by manufacturers and thus not readily available for access by users of VSDs. Modifications to the drives must then be limited to an electrical connection only between the existing VSDs and ride-through enhancing module. This results in limited options available for enhancing ride-through capability for existing VSDs.
A VSD with a passive front end diode rectifier has limited response possibilities during a voltage disturbance which makes it sensitive to voltage dips [10][11][12]. Reference [13] developed a stacked switched capacitor for energy buffer on the dc bus and developed a switching scheme for the buffer switches. Voltage fault ride through is achieved in [12] through the use of field-oriented control. Various researchers have investigated alternatives of improving the ride-through capability of a VSD to voltage dips [10,11,[14][15][16]. These alternatives can be grouped into those that allow ride-through for a total loss of power under an STPI and those that do not. Invariably, those that can offer ride-through for a STPI incorporate an energy storage device. Several STPI ride-through improvement alternatives incorporating energy storage are available to provide the required additional dc-link power. These include either ordinary or super-capacitors, battery based back-up systems, flywheel based energy storage, motor-generator sets, storage based on super conducting magnetic energy and fuel cells [14,[17][18][19][20].
The simplest alternative for improving STPI ride-through involves increasing the overall dc-link capacitance. Most VSDs are equipped with an electrolytic capacitor on the dc-link. This capacitor is used primarily for filtering the dc-link voltage, providing limited energy storage for a VSD to ride-through minor voltage dips and providing a low impedance path for high frequency inverter currents [19]. Typical capacitance values are between 75-360 µF/kW [15]. Although a larger capacitor is preferred in order to strongly hold the dc link voltage for longer during a STPI, big capacitance tend to cause harmonic pollution onto the supply.
To be able to ride through a STPI, a sufficient energy reserve is required. A variety of energy storage technologies are candidates for providing the required power during a STPI. Battery backup systems, supercapacitors, motor-generator sets, flywheel energy storage systems, superconducting magnetic storage and fuel cells are some examples of these technologies [7]. For low voltage (<1000 V), low power (10 kW) applications, ordinary capacitors, super-capacitors and batteries are suitable candidates [14]. A boost converter maintains the dc-link voltage to a set point during the dip. The boost converter can be connected to the dc-link of a VSD, but more commonly is connected in parallel to the VSD. It uses the remaining voltage during a dip, to supply the dc-link. They do not use an energy storage device. Boost converters can be integrated into new drives between the rectifier and the dc-link capacitors or retrofitted as an add-on module [11,14]. During a voltage dip, the boost converter will sense a drop in the dc-link voltage and begin to regulate the dc-link to a minimum voltage required by the inverter. However, when the supply is completely lost due to a fault, the boost converter loses capability for ride through dip voltage. This paper proposes the use of a switched capacitor onto the VSD dc bus for a 0.2 s STPI ride through capability. Since the additional capacitor is only introduced during a dc bus voltage dip the power quality of the supply is not compromised during the healthy supply of power to the VSD. The power electronic module used to switch the capacitor onto the dc bus is equipped with the necessary inrush current limiting technique. The impact of switching a capacitor onto the dc bus was investigated based on motor performance and the dc bus performance. The work also proposes power electronic module sizing methodology based on the motor and VSD nameplate data.
The paper is organized as follows, Section 2 provides the behavior of the VSD under STPI and Section 3 proposes dc-link voltage dip compensation module. Section 4 is concerned with proposed sizing methodology for voltage dip compensation module, Section 5 with simulation results and analysis, Section 6 with experimental results, Section 7 with the overall analysis of results, and Section 8 with the conclusion.

Variable Speed Drive under Short-Term Power Interruption (STPI)
A voltage dip or STPI on the incoming AC supply of a VSD causes a drop in the dc-link voltage. If supply restoration is delayed, this can lead to a low dc-link voltage protection trip. VSDs are equipped with protection mechanism to guard against low dc-link voltage in order to guarantee good control and avoid damage to equipment. A number of studies have been carried to assess the tolerance of VSDs to voltage dips and STPIs [5,10,21]. Results indicate that most VSDs are most sensitive to three-phase dips and STPIs, less sensitive to two-phase dips and least sensitive to single phase dips. To ride through a STPI will depend on the size of the VSD dc link capacitor. The challenge is that in several industries, VSDs were designed for certain STPI duration. A comparison of VSDs from different manufactures indicates that most VSDs can only survive a STPI of up to 0.05 s. The energy within a VSD-motor-load system during a STPI can be represented by (1), where E L is the total load energy, E C is the energy supplied by the capacitor and E kin is the kinetic energy in the rotating masses. During a STPI, the capacitor and rotating masses provide energy E L to the load, resulting in the reduction of capacitor voltage and motor performance. E L can be expressed as in (2), where T l is the load torque, J l is inertia, C is the dc-link capacitance, V C is capacitor voltage, ω is speed of rotating assembly and t 2 -t 1 is the duration of the STPI. From (2), it can be concluded that the behavior of a VSD during a STPI is influenced by three main parameters: C which determines the electric energy E C stored in the dc-link, J l which determines the kinetic energy E kin stored in the rotating parts and the motor load T l . For the same load torque, a VSD with a large capacitance driving a load with a high inertia has a better chance of riding through a voltage dip as compared to lower capacitance and motor inertia. At the end of the STPI, i.e., when supply is restored, large inrush currents can be experienced due to reduced VSD dc link capacitor voltage. If not controlled, this inrush current can cause nuisance tripping of protective devices, damage VSD components and cause undesirable torque pulsations. The magnitude of inrush current is largely dependent on the capacitor voltage at the end of the STPI. A lower capacitor voltage results in a higher inrush charging current. Low dc-link voltage protection is incorporated to ensure that the capacitor does not discharge excessively which would otherwise lead to high inrush currents. During initial powering, inrush current is limited by use of a pre-charge resistor based circuit [22].

Proposed DC-Link Voltage Dip Compensation
The proposed voltage dip compensating module (module) was developed to ensure a 0.2 s ride-through capability of a 1.5 kW VSD while striving to sustain demanded motor load. This work only focus on V/f controlled VSDs as they are predominantly used in industry. The proposed module was required to be active only during an STPI and when charging in order to minimize harmonic pollution onto the grid associated with an increased capacitance on the dc link. Ride-through requirements are listed in Table 1.  Figure 1 shows the proposed module developed for retaining the dc bus voltage using a switched capacitor C a . C e is the existing VSD dc bus capacitor. The switches T c and T d controlled the charging and discharging of C a , respectively. The diodes (D c and D d ) were installed to prevent IGBT freewheeling diodes from conducting whenever the respective IGBT was switched off and thus allowed the flow of power in one direction in each of the charging and discharging circuits. The resistor R C , that was installed on the charging leg of C a limited inrush current to be within VSD rectifier device ratings during charging of C a . Resistor R d installed on the discharging leg limited the inrush current when module was activated as C a charged C e .
Energies 2021, 14, x FOR PEER REVIEW charging leg of Ca limited inrush current to be within VSD rectifier device rat charging of Ca. Resistor Rd installed on the discharging leg limited the inrush cu module was activated as Ca charged Ce. Charging of Ca was conducted using the rectifier of the VSD through the detection circuit sensed the STPI and controlled the switching of IGBTs, Tc an ensured that the voltage dip compensation module (VDCM) was switched ont when required i.e., during the dip and taken out once the voltage STPI had cle fully charged.

DC-Link during Compensation
Let us assume a low inertia load and a negligible energy contribution fr masses. During the period after the start of the STPI and before Ca is switched link, Ce provides energy required by the load. Thus, when Ca eventually is sw the dc-link, it charges up Ce and provides power to the load during the ST represents the dc-link during compensation. RCa is the capacitor internal resis the IGBTs on state internal resistance, RDd is resistance of the diode during con is the discharge current limiting resistor, RCe is the internal resistance of the VS and Pinv is the VSD inverter input power. Relating capacitance and input pow can be described in (3), Charging of C a was conducted using the rectifier of the VSD through the dc bus. The detection circuit sensed the STPI and controlled the switching of IGBTs, T c and T d which ensured that the voltage dip compensation module (VDCM) was switched onto the dc bus when required i.e., during the dip and taken out once the voltage STPI had cleared and C a fully charged.

DC-Link during Compensation
Let us assume a low inertia load and a negligible energy contribution from rotating masses. During the period after the start of the STPI and before C a is switched onto the dc-link, C e provides energy required by the load. Thus, when C a eventually is switched onto the dc-link, it charges up C e and provides power to the load during the STPI. Figure 2 represents the dc-link during compensation. R Ca is the capacitor internal resistance, R Td is the IGBTs on state internal resistance, R Dd is resistance of the diode during conduction, R d is the discharge current limiting resistor, R Ce is the internal resistance of the VSD capacitor and P inv is the VSD inverter input power. Relating capacitance and input power demand can be described in (3), where V Ca and V Ca_min are the capacitor voltages at start and end of compensation respectively, P is the total power demand and ∆t is STPI duration, V Ca can be represented as in (4) based on Figure 2, where V Rdisch is the voltage drop across IGBT switch, diode D d and resistor R d . Substituting V Ca from (3) into (4) results in (5), Energies 2021, 14, 8257

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represents the dc-link during compensation. RCa is the capacitor internal resista the IGBTs on state internal resistance, RDd is resistance of the diode during cond is the discharge current limiting resistor, RCe is the internal resistance of the VSD and Pinv is the VSD inverter input power. Relating capacitance and input pow can be described in (3),  Inrush current at start of compensation, where V dc is the dc-link voltage at start of compensation.

DC-Link during Charging
The DC-link during charging is shown in Figure 3, Inrush charging current i c at the start of charging can be obtained from (7), where VCa and VCa_min are the capacitor voltages at start and end of compensatio tively, P is the total power demand and Δt is STPI duration, VCa can be represe (4) based on Figure 2, where VRdisch is the voltage drop across IGBT switch, diode Dd and resistor Rd. Su VCa from (3) into (4) results in (5), Inrush current at start of compensation, where Vdc is the dc-link voltage at start of compensation.

DC-Link during Charging
The DC-link during charging is shown in Figure 3, Inrush charging curren start of charging can be obtained from (7), Inrush charging current ic at the start of charging can be obtained from, where VCa_min is the capacitor Ca voltage after compensation.

Sizing Methodology: Voltage Dip Compensating Module
A sizing methodology based on readily available data such as the motor name plate information is developed. Figures 4-6 show the proposed sizing m gies for inrush current limiting resistors Rd, Rc and capacitor Ca. For Figure 4, rithm works backwards from motor size to the dc link of the VSD or inverter. T full load current and the motor power factor can be obtained from the motor na These values will then be used to calculate the input inverter dc current (idc_n). Th Inrush charging current i c at the start of charging can be obtained from, where V Ca_min is the capacitor C a voltage after compensation.

Sizing Methodology: Voltage Dip Compensating Module
A sizing methodology based on readily available data such as the motor and VSD name plate information is developed. Figures 4-6 show the proposed sizing methodologies for inrush current limiting resistors R d , R c and capacitor C a . For Figure 4, this algorithm works backwards from motor size to the dc link of the VSD or inverter. The motor full load current and the motor power factor can be obtained from the motor name plate. These values will then be used to calculate the input inverter dc current (i dc_n ). The inverter Energies 2021, 14, 8257 6 of 19 output transient current or peak current can be obtained from the inverter nameplate. Once this is obtained the inverter peak dc bus current can be calculated (i dc_max ). Then this will allow for the maximum discharge current to be calculated (i d_max ). Since i d_max will be calculated, and given a set voltage where compensation should start (V dc_trig ), diode forward voltage (V f ) and the capacitor voltage (V ca ), it then becomes possible to calculate the total resistance in the capacitor discharge leg. Given the knowledge of the IGBT internal resistance and that of the diode, the current limiting resistor can then be calculated (R d ) including its power rating. Figure 4 shows the analytical progress of obtaining the size of the current limiting resistor when switching the additional capacitor onto the dc bus.
drop calculated is smaller than the set desired voltage drop (Vdc_max) then This will mean that the chosen standard capacitor will satisfy the conditi the dc bus voltage beyond (Vdc_max) during a STPI.
In Figure 6, a charging limiting resistor is calculated. Having obtaine inrush current by calculations. The rectifier maximum output current ca Once the minimum charging resistance is obtained, the inrush charging can be calculated including its power rating. It should be noted that duri scenario, the additional capacitor voltage would be minimal.
Sizing of the additional capacitor Ca and inrush current limiting res was conducted for an induction motor with parameters shown in Append and A2. Using the proposed sizing methodology, the calculated values f obtained were 15.1 mF, 6.91 Ω and 8.15 Ω, respectively.

Simulation Results and Analysis
To validate the operation of the proposed module and assess its impact on VSD and motor behavior, simulation studies were carried out. The simulation model comprised a v/f PWM controlled inverter driving an induction motor rated at 1.5 kW. This study is only concerned with v/f control based VSDs. The VSD simulation parameters are listed in Table A3 in Appendix A.

Simulation Results without DC-Link Voltage Compensation
When a 0.2 s STPI was simulated on the VSD supply, the dc-link voltage started decaying at a constant rate from an initial value of 556 V whereas the dc-link capacitor of the VSD supplied all the power required by the motor as shown in Figure 7. There was a gradual reduction in speed and torque as the dc-link voltage decayed. The dc-link voltage continued to drop until 300 V which is the under-voltage trip setting at which stage the VSD tripped. This is indicated by the flattening of the dc-link voltage curve and a loss in motor torque. There was an increase in the rate of speed reduction as load torque decelerated the motor-drive rotating assembly. After VSD tripped, for a brief period, the motor switched to an induction generator as the load acted as the prime over and stator windings acted as a current source allowing self-excitation of the motor. Once stator current decayed to zero, developed torque decays to zero. After the STPI was cleared over a period of 0.2 s, there is a sudden buildup of inrush current as shown in Figure 7. This results from  Figure 5 shows the additional switched capacitor sizing. Given the motor shaft power, motor efficiency and inverter efficiency from their nameplates the inverter input power can be calculated. The additional capacitor is calculated based on the assumption that full load current would be produced by this capacitor. This is because the additional capacitor will be used to supply the full load during a STPI. Given the known capacitance (from calculations) and the dc bus voltage, the appropriate capacitor can be chosen from the started capacitor units. Once the equivalent series resistor is calculated, the expected voltage drop on the dc bus can be calculated based on the chosen capacitor. If the voltage drop calculated is smaller than the set desired voltage drop (V dc_max ) then the loop ends. This will mean that the chosen standard capacitor will satisfy the conditions to not drop the dc bus voltage beyond (V dc_max ) during a STPI.
In Figure 6, a charging limiting resistor is calculated. Having obtained the VSD input inrush current by calculations. The rectifier maximum output current can be calculated. Once the minimum charging resistance is obtained, the inrush charging limiting resistor can be calculated including its power rating. It should be noted that during the charging scenario, the additional capacitor voltage would be minimal.
Sizing of the additional capacitor C a and inrush current limiting resistors R d and R c was conducted for an induction motor with parameters shown in Appendix A, Tables A1 and A2. Using the proposed sizing methodology, the calculated values for C a , R d and R c obtained were 15.1 mF, 6.91 Ω and 8.15 Ω, respectively.

Simulation Results and Analysis
To validate the operation of the proposed module and assess its impact on VSD and motor behavior, simulation studies were carried out. The simulation model comprised a v/f PWM controlled inverter driving an induction motor rated at 1.5 kW. This study is only concerned with v/f control based VSDs. The VSD simulation parameters are listed in Table A3 in Appendix A.

Simulation Results without DC-Link Voltage Compensation
When a 0.2 s STPI was simulated on the VSD supply, the dc-link voltage started decaying at a constant rate from an initial value of 556 V whereas the dc-link capacitor of the VSD supplied all the power required by the motor as shown in Figure 7. There was a gradual reduction in speed and torque as the dc-link voltage decayed. The dc-link voltage continued to drop until 300 V which is the under-voltage trip setting at which stage the VSD tripped. This is indicated by the flattening of the dc-link voltage curve and a loss in motor torque. There was an increase in the rate of speed reduction as load torque decelerated the motor-drive rotating assembly. After VSD tripped, for a brief period, the motor switched to an induction generator as the load acted as the prime over and stator windings acted as a current source allowing self-excitation of the motor. Once stator current decayed to zero, developed torque decays to zero. After the STPI was cleared over a period of 0.2 s, there is a sudden buildup of inrush current as shown in Figure 7. This results from low resistance of the VSD capacitor which is now experiencing a sudden high voltage after the STPI.         There was a decrease in the dc-link voltage when the supply was lost. At the point where the dc-link voltage dropped below the trigger set point voltage of 512 V, the dc-link voltage compensating device was initiated. The additional capacitor bank was switched onto the dc link and started supplying additional power. This is evidenced by the sudden halt in the "dc-link voltage" rate of decay and an increase in the dc-link voltage from 512 V to 524 V. The halting of the "dc-link voltage" decay was accompanied by a sudden increase of the current from the additional capacitor since the capacitor started to inject power into the dc-link i.e., delivering power to the motor as shown in Figure 8. Table 2 shows the summary of the simulation results. The "dc-link voltage" continued to drop at a lower rate due to the influence of the additional capacitor. The start and end of compensation had a minor impact on the current drawn by the motor. There was, however, a steady increase in current drawn as the voltage decayed due to the need to maintain a constant power. Once supply was restored after 0.2 s and the "dc-link voltage" was retained from a minimum of 467 V to approximately 566 V, the capacitor bank was switched off from the "dc-link".

Simulation Results with DC-Link Voltage Compensation
Torque pulsations were observed when the compensating module was connected and disconnected respectively from the dc-link at STPI clearance. These torque pulsations were as a result of transients in the dc-link voltage at the start and end of compensation.
Once STPI had cleared and the dc-link voltage stabilized, charging of C a from the dclink commenced. Figure 9 shows the simulation results obtained. To avoid continuous and excessive loading of the dc-link due to charging action, pulse charging was adopted. This can be seen from the pulsed charging current trend. This approach resulted in minimum impact on the torque and speed of the motor.

Experimental Set-Up and Results
Two induction machines were used for the experimental setup. One machine acted as a motor and the other as a generator in order to load the induction motor. The motor was driven by two-quadrant industrial VSD. Loading on the induction generator was driven through the 4 quadrant VSD. Figure 10, shows the experimental block diagram. The proposed voltage dip compensating module (VDCM) was interfaced to a two-quadrant VSD connected to a 1.5 kW induction motor. A 2.2 kW induction generator coupled to the induction motor provided the required loading of the induction motor. The SIEMENS S7 Programmable Logic Controller (PLC) was used for the generation of the logic signals used for controlling the power switches. These power switches were responsible for creating a voltage dip on the dc bus and switching the additional capacitor onto the dc bus. Since a PLC was used for the generation of the switching signals, the period of the short-term power interruption could be set to any desired value.
A variac transformer was used for the voltage dip generator on the dc bus of the 2 quadrant VSD. The variac allowed for any dc bus dip voltage needed to be achieved. Figure 11 shows the diagram of the voltage dip generator. When switch S1 is on S2 is open, the variac would be set to a lower supply voltage in order to emulate a fault on the supply and by switching on S2 for a particular period a voltage dip can be created on the dc bus of the VSD. Figure 12 shows the experimental set-up.
The motor speed and torque were measured by a torque transducer mounted between the motor and generator coupling. The torque transducer had a maximum error of 0.25%. The voltage transducers and the current transducers each had a maximum total error of +/−1%. Before the capacitor was put on standby for dc-link compensation, charging was carried out through a separately powered bridge rectifier as shown in Figure 12.

Experimental Test Conditions
The investigation involved assessing the behavior of the VSD without and with dc-link voltage compensation when subjected to a 0.2 s STPI. An industrial VSD was used and the investigation was carried out with the induction motor loaded to rated torque. To avoid damage to the VSD, key protection schemes including low dc-link voltage protection and overcurrent were left enabled. VSD dc-link voltage compensation, slip compensation and torque compensation control schemes were disabled to ensure alignment with the simulation model.

Experimental Set-Up and Results
Two induction machines were used for the experimental setup. One machine acted as a motor and the other as a generator in order to load the induction motor. The motor was driven by two-quadrant industrial VSD. Loading on the induction generator was driven through the 4 quadrant VSD. Figure 10, shows the experimental block diagram. The proposed voltage dip compensating module (VDCM) was interfaced to a two-quadrant VSD connected to a 1.5 kW induction motor. A 2.2 kW induction generator coupled to the induction motor provided the required loading of the induction motor. The SIE-MENS S7 Programmable Logic Controller (PLC) was used for the generation of the logic signals used for controlling the power switches. These power switches were responsible for creating a voltage dip on the dc bus and switching the additional capacitor onto the dc bus. Since a PLC was used for the generation of the switching signals, the period of the short-term power interruption could be set to any desired value. A variac transformer was used for the voltage dip generator on the dc bus of the 2 quadrant VSD. The variac allowed for any dc bus dip voltage needed to be achieved. Figure 11 shows the diagram of the voltage dip generator. When switch S1 is on S2 is open, the variac would be set to a lower supply voltage in order to emulate a fault on the supply and by switching on S2 for a particular period a voltage dip can be created on the dc bus of the VSD. Figure 12 shows the experimental set-up.  was driven by two-quadrant industrial VSD. Loading on the induction generator was driven through the 4 quadrant VSD. Figure 10, shows the experimental block diagram. The proposed voltage dip compensating module (VDCM) was interfaced to a two-quadrant VSD connected to a 1.5 kW induction motor. A 2.2 kW induction generator coupled to the induction motor provided the required loading of the induction motor. The SIE-MENS S7 Programmable Logic Controller (PLC) was used for the generation of the logic signals used for controlling the power switches. These power switches were responsible for creating a voltage dip on the dc bus and switching the additional capacitor onto the dc bus. Since a PLC was used for the generation of the switching signals, the period of the short-term power interruption could be set to any desired value. A variac transformer was used for the voltage dip generator on the dc bus of the 2 quadrant VSD. The variac allowed for any dc bus dip voltage needed to be achieved. Figure 11 shows the diagram of the voltage dip generator. When switch S1 is on S2 is open, the variac would be set to a lower supply voltage in order to emulate a fault on the supply and by switching on S2 for a particular period a voltage dip can be created on the dc bus of the VSD. Figure 12 shows the experimental set-up.  The motor speed and torque were measured by a torque transducer mounted between the motor and generator coupling. The torque transducer had a maximum error of 0.25%. The voltage transducers and the current transducers each had a maximum total error of +/−1%. Before the capacitor was put on standby for dc-link compensation, charging was carried out through a separately powered bridge rectifier as shown in Figure 12.

Experimental Test Conditions
The investigation involved assessing the behavior of the VSD without and with dclink voltage compensation when subjected to a 0.2 s STPI. An industrial VSD was used and the investigation was carried out with the induction motor loaded to rated torque. To avoid damage to the VSD, key protection schemes including low dc-link voltage protec-  Figure 13 shows the results obtained when the two-quadrant VSD is subjected to a 0.2 s STPI. Once supply to the VSD was lost, the dc-link voltage immediately started decaying as the VSD dc-link capacitor supplied all the required motor power. The VSD tripped once the dc-link voltage had dropped to below the low dc-link trip setting of 288 V. This is indicated by the flattening of the dc-link voltage curve. Once supply was restored at the end of the dip, the dc-link voltage rapidly increased to its nominal level with some initial oscillations. The voltage dip clearance was followed by a current spike as the VSD dc-link capacitor started charging up.

Results without "DC-Link Voltage" Compensation
The investigation involved assessing the behavior of the VSD without and with dclink voltage compensation when subjected to a 0.2 s STPI. An industrial VSD was used and the investigation was carried out with the induction motor loaded to rated torque. To avoid damage to the VSD, key protection schemes including low dc-link voltage protection and overcurrent were left enabled. VSD dc-link voltage compensation, slip compensation and torque compensation control schemes were disabled to ensure alignment with the simulation model. Figure 13 shows the results obtained when the two-quadrant VSD is subjected to a 0.2 s STPI. Once supply to the VSD was lost, the dc-link voltage immediately started decaying as the VSD dc-link capacitor supplied all the required motor power. The VSD tripped once the dc-link voltage had dropped to below the low dc-link trip setting of 288 V. This is indicated by the flattening of the dc-link voltage curve. Once supply was restored at the end of the dip, the dc-link voltage rapidly increased to its nominal level with some initial oscillations. The voltage dip clearance was followed by a current spike as the VSD dc-link capacitor started charging up. Figure 13. Experimental results without dc-link voltage compensation. Figure 13. Experimental results without dc-link voltage compensation.

With "DC-Link Voltage" Compensation
The dc bus was operated at 556 V and the compensation capacitor was pre-charged to a voltage of 544 V as shown in Figures 14 and 15, respectively. During a fault the dc bus voltage started to drop. Once the voltage drops below 512 V, the trigger circuit was activated which then effectively switched the additional capacitor bank onto the "dc-link". Slight reductions in shaft speed including insignificant motor torque pulsations during the STPI were observed as shown in Figure 14. Figure 15 shows the instant increase of the discharge current from the additional capacitor drawn into the dc bus.

With "DC-Link Voltage" Compensation
The dc bus was operated at 556 V and the compensation capacitor was pre-charged to a voltage of 544 V as shown in Figures 14 and 15, respectively. During a fault the dc bus voltage started to drop. Once the voltage drops below 512 V, the trigger circuit was activated which then effectively switched the additional capacitor bank onto the "dc-link". Slight reductions in shaft speed including insignificant motor torque pulsations during the STPI were observed as shown in Figure 14. Figure 15 shows the instant increase of the discharge current from the additional capacitor drawn into the dc bus.   Figure 16 shows the results obtained of charging from the dc-link of the VSD. The charging circuit was configured to switch off once the dc-link voltage had dropped below a pre-set value. This was done to ensure that the dc-link was not excessively loaded by charging of the additional capacitor.   Figure 16 shows the results obtained of charging from the dc-link of the VSD. The charging circuit was configured to switch off once the dc-link voltage had dropped below a pre-set value. This was done to ensure that the dc-link was not excessively loaded by charging of the additional capacitor. When charging was initiated, a considerable charging current was drawn, resulting in the dc-link voltage dropping below the charging threshold. This caused the charging IGBT to switch off. In this state, the dc-link voltage recovered resulting in the IGBT switching on. This repeated switching results in a pulsed charging current. Once the additional capacitor voltage had recovered to a value which did not trigger switching off the charging IGBT, continuous charging occurred till the capacitor was fully charged. Table 3 summarizes the variations in the dc-link voltage and capacitor voltage during compensation. The voltage drop across the capacitor is less than that of the dc-link. This is as a result of the voltage drop across the inrush limiting resistor during compensation. Table 4 shows the impact of the compensating module on torque and speed.  When charging was initiated, a considerable charging current was drawn, resulting in the dc-link voltage dropping below the charging threshold. This caused the charging IGBT to switch off. In this state, the dc-link voltage recovered resulting in the IGBT switching on. This repeated switching results in a pulsed charging current. Once the additional capacitor voltage had recovered to a value which did not trigger switching off the charging IGBT, continuous charging occurred till the capacitor was fully charged.  The voltage drop across the capacitor is less than that of the dc-link. This is as a result of the voltage drop across the inrush limiting resistor during compensation. Table 4 shows the impact of the compensating module on torque and speed. A comparison of key parameters from calculation as per proposed sizing methodology, simulation and experimental results are summarised in Tables 5 and 6. There is a strong correlation between calculated values (as per sizing methodology), simulation and experimental results for the proposed voltage dip compensation.  To further test the proposed sizing methodology, a study was undertaken for a 7.5 kW motor. Data used for the 7.5 kW induction motor assessment is listed in Table A4 in Appendix A. The results of key parameters are shown in Tables 7 and 8. Calculated and simulated results for dc-link voltage compensation for a 7.5 kW induction motor during a STPI are very comparable. The proposed sizing methodology can thus be used for different sized motors which are driven from a v/f controlled VSDs.

Conclusions
This paper investigated and developed inrush current mitigation schemes for a proposed dc bus voltage ride through a power electronic module. The paper can be summarized as follows: The proposed method whilst effective in improving ride-through capability of VSD resulted in an unwanted voltage drop and energy losses due to the inrush current limiting resistor, which led to reduced overall module efficiency; • The observed behaviour of the VSD was based on a STPI which presents the worst-case scenario. Improved behaviour is expected for less severe voltage dips; • The voltage compensation module can be added to existing VSDs that are based on V/f control in order to avoid operational breakdowns.

Conflicts of Interest:
The authors declare no conflict of interest.