A CMOS Active Rectifier with Efficiency ‐ Improving and Digitally Adaptive Delay Compensation for Wireless Power Transfer Systems

: A CMOS active rectifier with digitally adaptive delay compensation for power efficiency improvement is presented in this work. The power transistors are turned on and turned off in ad ‐ vance under the control of the regenerated compensation signals, which are generated by the pro ‐ posed compensation control circuit; therefore, the reverse current is eliminated, and the efficiency is increased. Simulation results in a standard 0.18 μ m CMOS process show that the turn ‐ on and turn ‐ off delay of the rectifier is effectively compensated. The power efficiency is up to 90.6% when the proposed rectifier works at the operation frequency of 13.56 MHz.


Introduction
Nowadays, the wireless power transfer (WPT) system is a very popular research topic as there are a lot of WPT application scenarios. Most implanted medical devices need to be charged by the WPT system since it is inconvenient to remove the implanted devices from the human body for recharging or to be charged via transcutaneous interconnects [1]. Power efficiency is the most important consideration in the WPT system, especially for the implanted medical devices, since the potential temperature rising due to low efficiency may cause serious harm for human beings. A typical WPT system includes an inverter in the transmitter, coupling coils, and a rectifier followed by a DC/DC converter in the receiver, as shown in Figure 1 [1]. The system efficiency usually can be represented as follows: where , , , and / are the efficiencies of the inverter, the coupling coil, rectifier, and the dc/dc converter, respectively. Since the improvement of does not result in the decrease in , , and / , the system efficiency can be effectively improved by increasing the efficiency of the rectifier . In this paper, we focus on the efficiency improvement of the rectifier.
The active rectifier shown in Figure 2a was firstly proposed by Lam [2]. The comparator-controlled power NMOS and the cross-coupled PMOS have lower conduction voltages compared with the conventional passive diodes; however, the unavoidable delay of the comparator and buffer will result in that the power NMOS turn-on and turn-off with delays, thus causing reverse current and reducing the rectifier's power efficiency. Several methods have been proposed to compensate for the circuit delays. The unbalanced-biasing method is proposed to eliminate reverse current, thereby improving the power efficiency of the rectifier in [3]; however, it cannot work well when process, temperature, and voltage change. An integrated active rectifier for inductively powered applications is presented in [4]. There is an offset control function to compensate for both turn-on and turnoff delay for the comparators. The efficiency is effectively optimized, but it relies on highspeed comparators. In order to generate the switched-offset currents for the comparators adaptively, the work in [5] introduces two feedback loops into the active rectifier, both onand off-delay are compensated effectively against PVT variations and mismatches, but it is complicated. A time-domain technique that converts the buffer's delay time into a voltage is proposed in [6]. This voltage is able to control on/off time in the comparator for variable input voltage; however, the comparator's delay is not considered in this work. The work in [7] proposes to use adaptively biased fast and slow comparators, which are added to the main comparator to eliminate the on/off delay associated with the comparator and buffer chain. In [8], comparators with the digital-assisted biasing technique are utilized to switch the active diodes off in time, and thus, the reverse current can be eliminated; however, the compensation effect is not accurate enough. In [9], cycle-based timing control (CBTC) is proposed to significantly extend the duration for completely compensating on/off delays of active diodes, but there are two identical circuits to compensate MN1 and MN2, respectively, which increases the circuit complexity. In this paper, we propose to use digital circuits to regenerate the control signals for the power transistors' gate to effectively compensate for the rectifier's turn-on and turnoff delay. The proposed digital delay compensation circuit has low complexity, which is built by a small number of simple logic gates and basic flip-flops. The delay of buffer, comparator, and digital compensation circuit are all well-compensated in this proposed compensation circuit, and thus, the desired control signals for the power transistors' gate are regenerated effectively. In Section 2, the turn-on and turn-off delays of the rectifier are deeply analyzed. Section 3 presents the proposed method and Section 4 introduces the digital compensation circuit implementations. The simulation results and performance evaluation are illustrated in Section 5 and Section 6 concludes this work.

Introduction of Active Rectifier
The widely used full-wave active rectifier for the WPT system is displayed in Figure  2a, which consists of two cross-coupled PMOS and two comparator-controlled NMOS [2]. As for two cross-coupled PMOS MP1 and MP2, their gates are connected to VAC2 and VAC1, respectively, and their drains are connected to VAC1 and VAC2, respectively. However, the comparator and buffer have unavoidable propagation delays. Figure 2b illustrates a typical timing waveform when the active rectifier works. The propagation delay in the active rectifier mainly includes the comparator delay and the buffer delay. The turn-on delay will reduce the maximum transmittable power of the rectifier, and the turn-off delay will cause reverse current, which will greatly reduce the efficiency of the rectifier; therefore, both the turn-on delay and turn-off delay should be compensated for.
Common gate amplifier is widely used as the comparator in the rectifier, which also can be considered as a voltage-controlled current source. The comparator delay is the time that the comparator's output current charges its output capacitor to half of the power supply, as illustrated in Figure 3. Detailed analysis can be found in [10]. The comparator delay can be expressed as follows: where COUT is the load capacitance, T is the period of the AC input voltage, gm is the transconductance, IB is the bias current, α is a scaling factor, M is a factor equal to 0.9, and kn depends on the technology. In addition, | | equals | |. It can be seen from Equation (2) that the comparator delay is usually small since COUT is the input capacitance of the buffer, which is much smaller than the gate capacitance of the NMOS power transistor. Additionally, since the comparator delay is proportional to the fourth root of 1/|VAC|, it is less affected when the comparator's supply voltage VDC changes; therefore, in this work, the comparator delay is considered to be equivalent to a fixed value, and it is directly subtracted during the delay compensation process.
As for the delay of the buffer, its delay can be analyzed by the cascading single-stage inverters. The propagation delay of a single inverter is [11]: where VT is the threshold voltage, CL is the parasitic capacitance of the power transistor, VDD is the supply voltage, W and L are the width and length of NMOS in the inverter, respectively. From Equation (3), it can be known that when the supply voltage changes, the propagation delay of the inverter will change accordingly.
The schematic diagram of the inverter chain is shown in Figure 4. The expression of the minimum delay of the buffer (inverter chain) is [12]: where N is the stage number of the inverter, Cint is the intrinsic output capacitance of each inverter, Cg,i is the gate capacitance of the ith stage inverter, and γ = Cint/Cg,i, which is only related to the process and its value is approximately equal to 1 for most sub-micron process inverters. Assuming that each stage of the inverter has the same size enlargement factor f, the expression of F in Equation (4) is: , In order to drive the power transistors with large gate capacitance well, a large-scale buffer is necessary to reduce the rising and falling delay of the power transistor, which can be known from Equations (4) and (5); however, the delay of the large-scale buffer is not negligible. Additionally, the delay of the buffer will greatly change with the power supply according to Equation (3); therefore, in this design, it is necessary to measure and eliminate the real-time delay of the buffer.
The power efficiency of the proposed rectifier can be denoted as follows: In Equation (6), is the output power which can be expressed as follows: The power loss introduced by the reverse current is denoted as , its calculation equation in a half period can be defined as follows: where , is the conduction resistance of NMOS power transistors and . This power loss is the elimination target in this work which has a great impact on the power conversion efficiency of the rectifier. Figure 5 shows the structure of the active rectifier with the proposed compensation method. This paper proposes a two-step delay compensation method. Firstly, the turn-on and turn-off time of the rectifier, excluding the buffer's delay and the compensation control circuit delay, is measured by the measurement module, then recorded by recording sequences, respectively. Secondly, a fixed value is initialized into recording sequences to eliminate the comparator delay. Both of the delay compensation steps are realized with digital circuits. As shown in Figure 5, the digital circuit is used to generate the compensation signal (VDIGITAL1 or VDIGITAL2). The compensation signal passes through the buffer to turn on or turn off the power transistor MN1 or MN2, respectively. When the circuit environments changes, the rectified voltage VDC also changes; therefore, the delay-compensation control circuit should work continuously. Fortunately, the circuit environment usually changes slowly, so we choose to calibrate it every 1 μs, which is enough. The start signal (VSTART) is used, which is a 1 MHz square wave. At each rising edge of VSTART, the compensation control circuit will be triggered for calibration and perform a new round of compensation. In the following, we introduce the turn-on delay compensation and turn-off delay compensation, respectively, as well as the main implementation circuits.

Turn-On Delay Compensation
As analyzed before, the delay of the buffer and the compensation control circuit is compensated in real-time. Besides that, the comparator delay is compensated by considering it as a constant. Let us consider the turn-on delay first.
When the rising edge of VSTART comes, the recording process of the digital module is triggered. As shown in Figure 6a, t1 is recorded by the recording sequence 1, which is the time from the falling edge of the buffer's output to the rising edge of the comparator's output. This time can be measured and recorded by using digital counters and registers with a 1 GHz reference clock.
According to the value recorded by recording sequence 1, the counting sequence generates the rising and falling edges of the compensation signal. Specifically, when the falling edge of the comparators' output comes, the counting sequence starts counting until time passes by the recording value t1. At this time, the compensation control circuit generates the rising edge of the compensation signal VRISE in the next half period, as shown in Figure 6b. As the rising propagation delay is usually close to the falling propagation of the buffer and compensation control circuit, so the counting starts from the falling edge of the comparator's output is reasonable. In addition, t3 is the comparator's rising delay, t4 is the buffer's rising delay, and t5 is the compensation control circuit's rising delay, as illustrated in Figure 6b.
As analyzed before, t1 is the turn-on time of the rectifier, excluding the buffer's delay t4 and digital module delay t5; however, there is still a comparator's rising delay t3 that is not compensated. As for the comparator's raising delay t3, it is considered as a constant. To realize the compensation of t3, a fixed value is initialized into recording sequence 1 directly in the second delay compensation stage to make MN1 and MN2 turn off in advance; therefore, the rising edge of the compensation signal VRISE is generated when the counting sequence passes through the time that is the recording time t1 minus the fixed comparator compensation time t3. For improving the robustness of the method, an adjustable 3-bit digital code is imported to the chip to make sure that the comparator delay is always well estimated for different process, voltage, and temperature cases.
In this way, the rising edge of the compensation signal VRISE eliminates the turn-on delay of the comparator, buffer, and compensation control circuit. Compared with VCM-PRISE, which is the original comparator output, VRISE is earlier than VCMPRISE with (t3 + t4 + t5) as shown in Figure 6b. After the end of the recording process, the compensation control circuit no longer performs measurement and is only triggered until the next period rising edge of VSTART arrives.

Turn-Off Delay Compensation
The turn-off delay compensation is similar to the turn-on delay compensation. As for the delay of the buffer and compensation control circuit, we propose to measure t2, which is the time from the rising edge of the buffer's output to the falling edge of the comparator's output, and then, t2 is recorded by the recording sequence 2. When the rising edge of the comparators' output comes, the counting sequence starts counting until time passes by the value of the recording value t2 minus the fixed comparator compensation value t6. At this time, the digital module generates the falling edge of the compensation signal VFALL, as shown in Figure 6b. Compared with VCMPFALL, VFALL is earlier than VCMPFALL with (t6 + t7 + t8), in which the comparator's turn-off delay t7 can be compensated with a method similar to that for the comparator's turn-on delay cancelation.

System Operation Process
As a summary of the proposed compensation method, the system process flowchart is illustrated in Figure 7 and is introduced as follows: (1) After starting the system, the rising edge of VSTART is generated, which activates the initialization stage of the system operation process. (2) t1 and t2 are measured and recorded in preparation for the generation of compensation signals. (3) After the falling edge of the comparator's output, the rising edge of the compensation signal is generated when time passes through (t1 − t3). (4) After the rising edge of the comparator's output, the falling edge of the compensation signal is generated when time passes through (t2 − t6). Until now, the compensation signal of only one NMOS has been generated. (5) The delay compensation control circuit continuously performs step (3) and step (4) until a new rising edge of VSTART is generated, and this processing cycle reaches the end. The rising edge of VSTART is generated every 1 μs to recalibrate the compensation control circuit, and it will not stop being generated unless the wireless power transfer system containing the proposed rectifier is turned off or the generation of the calibration signal VSTART is stopped.

Circuit Implementation
In this section, the main implementation circuits are introduced in detail, including the recording sequence circuit, the counting sequence control circuit, and the compensation signals generating circuit.
As mentioned in Section 3, t1 and t2 are necessary to be measured for the next operation step. In the practical circuit, two auxiliary signals VMS1 and VMS2 are generated, as shown in Figure 8a. Taking a part of one period as an example, VMS1 remains high from the falling edge of VGN2 to the rising edge of VCMP1 and VMS2 remains high from the rising edge of VGN2 to the falling edge of VCMP2; therefore, t1 and t2 can be measured by measuring the high voltage duration of VMS1 and VMS2, respectively.
The recording sequence circuit consists of five flip-flops, as illustrated in Figure 8b. Take the recording sequence that records t1 as an example, it can only be activated when VMS1 is high. At the time of the new VSTART's rising edge, the flip-flops are reset for recording the new measurement result.
In order to save the area and the cost of the counting control circuit, the counting task for generating either the rising or falling edge of the compensation signal is performed by one counting control circuit, as shown in Figure 9. This counting control circuit is activated to count at the comparator's rising or falling edge until VCOUNT (1)(2)(3)(4)(5) are equal to VFRECORD (1)(2)(3)(4)(5) or VRRECORD (1)(2)(3)(4)(5), and VFRECORD (1)(2)(3)(4)(5) as well as VRRECORD (1)(2)(3)(4)(5) are the recording data of t1 and t2 in digital form, respectively. At the moment when the data are equal, the rising edge of compensation signal VRISE or the falling edge of compensation signal VFALL is generated by rear circuits and fed back into the counting control circuit, and thus the count is paused. As for the other two signals, VSET and VRESET, of the counting control circuit, they are used to set and reset the counting module's initial value, which is used to eliminate the fixed comparator's delay, respectively.
In the practical circuit, VRBIT (1)(2)(3)(4)(5) is the output of the comparison between VRRECORD(1-5) and VCOUNT (1)(2)(3)(4)(5), when VRRECORD (1)(2)(3)(4)(5) and VCOUNT (1)(2)(3)(4)(5) are equal in every five bits, the five bits of VRBIT are all high, and then VRSIE is generated. As for the process of VFALL's generation, it is similar to the process of VRISE's generation as introduced above.  For simplifying the control circuit, two channels that generate the compensation signals for MN1 and MN2 are combined in one circuit, as illustrated in Figure 10. This circuit is the only one signal path from the output of the comparator (CMP1 or CMP2) to the gate of NMOS; therefore, the NMOS will lose control once VRISE or VFALL is not generated successfully. For solving this potential problem and improving the robustness of the compensation control circuit, the rising edge signal and the falling edge signal of the comparator are also set as input signals of this circuit. When VRISE and VFALL are not generated, VCMPRISE and VCMPFALL replace them to control MN1 and MN2. Since the rising edge and the falling edge of compensation signal are earlier than VCMPRISE and VCMPFALL, the compensation signal VSIGN would not be disturbed by the change of VCMPRISE or VCMPFALL when VRISE and VFALL are generated normally. As introduced in the system operation process, the compensation control circuit is recalibrated every 1 μs, then t1, t2 are remeasured and re-recorded at the initialization stage. At this stage, the comparator's output is required to control MN1 and MN2 directly; therefore, a state-switching circuit is designed, as shown in Figure 11. At the beginning of the initialization stage, VSTART is generated and VCONTROL is selected to be equal to VCMP. At the end of the initialization stage, the recording process is terminated and VMS1 falls to the low level; then, VCONTROL is selected to be equal to VCMP. It should be noted that the state-switching circuit is also responsible for extracting VCONTROL1, VCONTROL2 from VSIGN to drive MN1 and MN2, respectively. Taking the state-switching circuit that controls MN2 as an example: at the time when the falling edge of VCMP1 is generated, VCONTROL2 is selected to be equal to VSIGN, and the generation of the falling edge of VCMP2 means that MN2 has been controlled to be turned on and off in its half period. In the next half period, VSIGN turns to control MN1 and VCONTROL2 is selected to be equal to VCMP2, which remains low in this half period. Finally, VCONTROL1 and VCONTROL2 are processed by the level-shift and auxiliary module to generate the digital signals VDIGITAL1 and VDIGITAL2. After that, the compensated gate drive signals VGN1_COMP and VGN2_COMP are generated after the process of two-stage buffers to drive MN1 and MN2, respectively. This drive control circuit is illustrated in Figure 12a, and the waveforms of the main signals are displayed in Figure 12b. As for the auxiliary module, it is designed to solve the case that the compensation control circuit generates error compensation signals when the proposed rectifier is just started by locking the compensation signals to low.

Simulation Results
The proposed rectifier was implemented and simulated in a standard 0.18 μm CMOS process whose parameters are listed in Table 1. Figure 13 shows the layout and the die photo of the proposed rectifier.  Figure 14 shows the main transient waveforms of the proposed rectifier. It shows that the compensated gate drive signal VGN1_COMP and VGN2_COMP turn off the rectifier earlier, and thus, the reverse current is eliminated. Additionally, it is satisfactory that the rectifier is not turned on too late due to the control of the compensation control circuit, which reduces the loss of the maximum transmittable power.
The power efficiencies of the proposed rectifier under different conditions that input voltage changes from 3 V to 4 V and the load resistance of 100 Ω or 500 Ω are displayed in Figure 15. As for the result, the rectifier's efficiency is always higher than 86% and the highest power efficiency is 90.6% when the input is 4 V, and the load resistance is 500 Ω. We also designed and simulated a rectifier without the proposed compensation method; its power efficiency is also displayed in Figure 15. For the targeted input voltage and output load range, the highest efficiency is 85.5%, which is much lower than that of the proposed rectifier. Compared with the rectifier without the compensation method, the efficiency of the proposed rectifier is increased by up to 7%.
For more details, the power distribution of the proposed active rectifier is shown in Figure 16. It can be seen that the compensation control circuit of the proposed rectifier only consumes little power, and the rectifier can achieve an efficiency as high as 90%.   As shown in Table 2, the performance of the proposed rectifier is concluded and compared with the state-of-the-art designs. The peak efficiency is almost 91% at the load of 500 Ω and the input voltage of 4 V, respectively. In this work, the value of turn-on and turn-off compensation delay are 2 ns and 2.5 ns, respectively. These values are competitive in the works which are published in recent years. For example, in [13], the value of turnon and turn-off compensation delay are 0.75 ~ 1.5 ns and −0.7 ~ 0.5 ns, respectively. In [14] and [15], these values are both about 4 ns and 2 ~ 4 ns, respectively.
As for the complexity, the proposed fully digital delay compensation circuit is built by a small number of simple logic gates and basic flip-flops composed of active devices. In addition, the proposed delay compensation circuit is shared by MN1 and MN2 compensation control method, instead of using two identical circuits to compensate MN1 and MN2, respectively; however, the proposed delay compensation circuits are all mixed-signal circuits in [15,16]. Especially in [16], there are some passive devices that exist in the proposed delay compensation circuit. In [9], two identical circuits are used to compensate MN1 and MN2, respectively, which also increases the circuit complexity.
In order to evaluate the impact of the output load change on power conversion efficiency, a figure of merit (FoM) is introduced and listed in Table 2. It is defined as follows: (9) where and are the power conversion efficiency at the load of 100 Ω and 500 Ω, respectively. A smaller FoM value means that the power conversion efficiency is less affected by the variation of the load, and the proposed rectifier's FoM value is comparable to previous state-of-the-art work.

Conclusions
An efficiency-improving CMOS active rectifier with the digitally on-delay and offdelay compensation control circuit is developed in this paper. The compensation control circuit adaptively regenerates the compensated gate drive signal to control the NMOS to turn on and off in advance by measuring and recording the NMOS's turn-on delay and turn-off delay, and thus, the reverse current is eliminated, and the efficiency of the rectifier is improved. The simulation results show that this work is indeed effective in eliminating the delay of NMOS and is competitive compared with the previous state-of-the-art design.
Author Contributions: The authors contributed to different parts of the paper preparation as follows: Conceptualization, J.M. and X.T.; methodology and software, J.M. and X.T.; validation and analysis, Y.Z.; writing-original draft preparation, Y.Z. and X.T.; writing-review and editing, Y.Z. and X.T.; supervision, X.T. All authors have read and agreed to the published version of the manuscript.
Funding: This work was funded by Shenzhen Basic Research Foundation (No. JCYJ20180508152019687 and WDZC20200819152116001).

Institutional Review Board Statement: Not applicable.
Informed Consent Statement: Not applicable.