Mechanical Switch Based Adaptive Fault Ride-through Strategy for Power Quality Improvement Device

: Cascaded H-bridge power quality improving device (PQID) has garnered extensive at-tention for its ﬂexible electric energy conversion and fast voltage response. However, the failure rate of PQID is relatively high due to the use of large numbers of power electronic devices. This paper proposes a mechanical-switch based adaptive fault ride-through strategy for improving the operational stability and power supply reliability of PQID. According to the features of the topology and working principle of PQID, this paper summarized the types of internal faults and analyzed the characteristics of different types of faults. Based on the shortcomings of existing mechanical switches as a bypass method, corresponding adaptive fault ride-through strategies are proposed for different types of faults, and a comprehensive simulation test has been carried out. The results show that the proposed strategy can adaptively ride through unit faults and effectively improve the output waveform quality during the ride through time.


Introduction
As the proportion of renewable energy in the power system increases, many traditional distribution systems transfer towards cyber-physical multi-microgrids (MMGs) [1]. Line voltage stability is one of the key objectives for distribution systems [2]. The diversification trend of the distribution network load puts forward higher requirements for the reliability of the power supply [3]. From the perspective of the power supply company, prompt online assessment, Two-Stage Active and Reactive Power Coordinated Optimal dispatch can improve the line voltage quality of the power system [4]. From the perspective of load, power electronic device is a more appropriate solution. Especially in medium voltage and large capacity field, power quality improvement devices (PQID) with energy storage have become the high-priority solution in current industry [5]. The cascaded H-bridge (CHB) has the characteristics of modularity and redundancy [6]. It can output a medium-voltage voltage of 10 kV without a step-up transformer, suitable for medium-voltage large-capacity application scenarios.
Multiple H-bridge power units cascade the output of PQID. Due to the use of many power semiconductor devices, the failure rate is relatively high [7]. Due to the modularity of PQID, its main faults all occur inside the H-bridge power unit. According to statistics, the proportion of power semiconductor device failures accounts for 38% of the failure statistics of multilevel converters [8,9]. The faults of the power unit can be divided into two types: short-circuit and open-circuit faults. Short-circuit switch faults are fast-acting and destructive, as it commonly damages the switch [10]. Usually, the Insulated Gate Bipolar Transistor (IGBT) switch module integrates hardware short-circuit protection (1) The proposed strategy uses mechanical switches as reliable bypass devices, which reduces the system cost. (2) The proposed voltage optimization method has the advantages of simplicity and self-adaptation. There is no need to change the control strategy after completing the fault ride-through process. (3) The best fault ride-through method can be selected according to the system operation and fault conditions. The proposed strategy is applicable to all voltage-controlled cascaded H-bridge topologies.
The rest of this paper is structured as follows. The topology of the PQID is described in Section 2. This paper analyzes the different fault characteristics of the H-bridge unit in Section 3. A mechanical-switches based adaptive fault ride-through strategy for multiple faults is presented in Section 4. Simulation results are presented in Section 5 to test the performances of the proposed strategies. The conclusions are drawn in Section 6.  vmi is the output voltage of the power unit. Each unit in PQID has the same topology, and the Direct Current (DC) side of each unit is independent of the others, which makes it easy to achieve voltage balance. The cascaded H-bridge (CHB) can output medium voltage Alternating Current (AC) voltage without a transformer. If the modulation is reasonable, the operation of each power unit is symmetrical. ...

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Bat Mechanical switch  Figure 2 shows the voltage control strategy of PQID. This control strategy is divided into two parts: power control and voltage amplitude control.
(1) Power control is used to maintain the power balance of the system. Pl is the active power of the load, Pg is the active power of the grid side, and Pext is the output active power setting value of CHB (0 during normal operation). The relationship between Pg and phase angle difference of grid and load δ is: where Ug is Root Mean Square (RMS) of grid voltage, Ul is RMS of load voltage, X1 is the impedance between grid and load. Based on the power difference between Pg and Pl, the reference value of δ * can be obtained through PI control. Adjusting the load voltage frequency can realize the tracking of δ to δ * , and achieve the purpose of power control.
(2) The voltage amplitude control is used to maintain the stability of the load voltage Ul. Uldref = 1, Ulqref = 0. ICdref and ICqref are the reference value of the dq axis component of the CHBC output current. UCdref and UCqref are the reference value of the dq axis component of the CHBC output voltage. The CHBC three-phase modulation voltage is obtained through the inverse dq transformation. v mi is the output voltage of the power unit. Each unit in PQID has the same topology, and the Direct Current (DC) side of each unit is independent of the others, which makes it easy to achieve voltage balance. The cascaded H-bridge (CHB) can output medium voltage Alternating Current (AC) voltage without a transformer. If the modulation is reasonable, the operation of each power unit is symmetrical. Figure 2 shows the voltage control strategy of PQID. This control strategy is divided into two parts: power control and voltage amplitude control.  When vg is normal, the power flow is shown in Figure 3a. CHB does not output active power. When vg drops or is interrupted, the power flow is shown in Figure 3b. CHB output active power. The stability of PQID is mainly affected by the power unit. The bypass switch of the power unit is a mechanical switch with a slow closing speed, and its closing time is 100-130 ms. The closing time is too long for the cascaded H-bridge system. Therefore, the sys- (1) Power control is used to maintain the power balance of the system. P l is the active power of the load, P g is the active power of the grid side, and P ext is the output active power setting value of CHB (0 during normal operation). The relationship between P g and phase angle difference of grid and load δ is: where U g is Root Mean Square (RMS) of grid voltage, U l is RMS of load voltage, X 1 is the impedance between grid and load. Based on the power difference between P g and P l , the reference value of δ * can be obtained through PI control. Adjusting the load voltage frequency can realize the tracking of δ to δ * , and achieve the purpose of power control.
(2) The voltage amplitude control is used to maintain the stability of the load voltage U l . U ldref = 1, U lqref = 0. I Cdref and I Cqref are the reference value of the dq axis component of the CHBC output current. U Cdref and U Cqref are the reference value of the dq axis When v g is normal, the power flow is shown in Figure 3a. CHB does not output active power. When v g drops or is interrupted, the power flow is shown in Figure 3b. CHB output active power.  When vg is normal, the power flow is shown in Figure 3a. CHB does not output active power. When vg drops or is interrupted, the power flow is shown in Figure 3b. CHB output active power. The stability of PQID is mainly affected by the power unit. The bypass switch of the power unit is a mechanical switch with a slow closing speed, and its closing time is 100-130 ms. The closing time is too long for the cascaded H-bridge system. Therefore, the system needs fault ride-through and voltage optimization during closing time. Figure 4 is the timeline.

Power Unit Fault Analysis
Since the IGBT module integrates short-circuit protection, this article only discusses open-circuit faults. When the inverter unit is normal, the power unit can complete the fault ride-through process by internal bypass switches. Therefore, this section only analyzes the inverter unit fault. Inverter unit faults can be divided into controllable faults and uncontrollable faults. Figure 5 shows controllable faults, a common feature: a current bypass path shown by the dashed line. This article classifies this type of faults as controllable faults. The stability of PQID is mainly affected by the power unit. The bypass switch of the power unit is a mechanical switch with a slow closing speed, and its closing time is 100-130 ms. The closing time is too long for the cascaded H-bridge system. Therefore, the system needs fault ride-through and voltage optimization during closing time. Figure 4 is the timeline.

Controllable Fault
When vg is normal, the power flow is shown in Figure 3a. CHB does no power. When vg drops or is interrupted, the power flow is shown in Figure put active power. The stability of PQID is mainly affected by the power unit. The bypas power unit is a mechanical switch with a slow closing speed, and its closin 130 ms. The closing time is too long for the cascaded H-bridge system. Ther tem needs fault ride-through and voltage optimization during closing time. timeline.

Power Unit Fault Analysis
Since the IGBT module integrates short-circuit protection, this article open-circuit faults. When the inverter unit is normal, the power unit can fault ride-through process by internal bypass switches. Therefore, this sec lyzes the inverter unit fault. Inverter unit faults can be divided into controlla uncontrollable faults.

Power Unit Fault Analysis
Since the IGBT module integrates short-circuit protection, this article only discusses open-circuit faults. When the inverter unit is normal, the power unit can complete the fault ride-through process by internal bypass switches. Therefore, this section only analyzes the inverter unit fault. Inverter unit faults can be divided into controllable faults and uncontrollable faults.  The output voltage of the power unit during normal operation is:

Controllable Fault
where vCi is the capacitor voltage, S1i, S2i, S3i, S4i is the trigger signal state of switches. Figure 5a shows the open-circuit fault of S1i. io < 0, the current flows through the anti-paral- The output voltage of the power unit during normal operation is: where v Ci is the capacitor voltage, S 1i , S 2i , S 3i , S 4i is the trigger signal state of switches. Figure 5a shows the open-circuit fault of S 1i . i o < 0, the current flows through the antiparallel diode of S 1i . i o > 0, since the open circuit of S 1i blocks the current path, the current will flow through the anti-parallel diode of S 2i instead of the capacitor. The output voltage is: where f 1,i is the fault state of S 1i . When an open circuit fault trigger in S 1i , f 1,i = 1. When S 1i is normal, f 1,i = 0. α is defined as: According to Equation (4), it can be seen that IGBT open-circuit fault will destroy the symmetry of voltage and current. Because of the current bypass path existing, the method proposed in [12] can be used to isolate the faulty unit.

Uncontrollable Fault
When the power unit has multiple open-circuit switches, the current bypass path does not exist. This article classifies such faults as uncontrollable faults. Figure 6 shows the most severe uncontrollable fault, all IGBTs in open-circuit condition. The current flows into the DC capacitor through the diode with the power transmitting in the reverse direction and capacitor charging. According to Equation (4) the unit output voltage of uncontrollable fault is obtained as: where f 2,i is the fault state of S 2i , f 3,i is the fault state of S 3i , f 4,i is the fault state of S 4i .  Power unit normal operation, the rectifier output current is > 0. An uncontrollable fault occurs, il > 0. The power is transferred from the inverter circuit to the capacitor in the reverse direction. Since the rectifier on the other side of the capacitor cannot transfer power in the reverse direction, is = 0. In a cycle, assuming that the average voltage of the capacitor is Uav, the active power consumed by the discharge resistor is U 2 av/R. Since the value of R is immense (typical value is 50-75 kΩ), the short-term power dissipation effect of the discharge resistance R on the power can be ignored. The voltage value ΔUC that rises in a cycle can be calculated.
If C = 2520 µF, Im = 60 A, the rising voltage during a fault cycle is 0.152 kV, and the Power unit normal operation, the rectifier output current i s > 0. An uncontrollable fault occurs, i l > 0. The power is transferred from the inverter circuit to the capacitor in the reverse direction. Since the rectifier on the other side of the capacitor cannot transfer power in the reverse direction, i s = 0. In a cycle, assuming that the average voltage of the capacitor is U av , the active power consumed by the discharge resistor is U 2 av /R. Since the value of R is immense (typical value is 50-75 kΩ), the short-term power dissipation effect of the discharge resistance R on the power can be ignored. The voltage value ∆U C that rises in a cycle can be calculated.
If C = 2520 µF, I m = 60 A, the rising voltage during a fault cycle is 0.152 kV, and the capacitor voltage reaches 0.758 kV in 50 ms after the fault occurs. Figure 7 shows the voltage and current changes in a cycle after the fault. Assuming the initial capacitor voltage U C0 is 0.9 kV. The capacitor voltage has reached 1.658 kV in 50 ms after the fault, which is very likely to exceed the withstand voltage of the IGBT. Therefore, when an uncontrollable fault occurs, bypass or other control strategies must be adopted to protect other normal switches and minimize the impact of the fault on the output voltage and current. reverse direction. Since the rectifier on the other side of the capacitor cannot t power in the reverse direction, is = 0. In a cycle, assuming that the average voltag capacitor is Uav, the active power consumed by the discharge resistor is U 2 av/R. Si value of R is immense (typical value is 50-75 kΩ), the short-term power dissipatio of the discharge resistance R on the power can be ignored. The voltage value Δ rises in a cycle can be calculated.
If C = 2520 µF, Im = 60 A, the rising voltage during a fault cycle is 0.152 kV, capacitor voltage reaches 0.758 kV in 50 ms after the fault occurs. Figure 7 shows t age and current changes in a cycle after the fault. Assuming the initial capacitor UC0 is 0.9 kV. The capacitor voltage has reached 1.658 kV in 50 ms after the fault, w very likely to exceed the withstand voltage of the IGBT. Therefore, when an unco ble fault occurs, bypass or other control strategies must be adopted to protect other switches and minimize the impact of the fault on the output voltage and current.

Fault Ride-through Strategy under Controllable Faults
When a controllable fault occurs, the controllable IGBT in the unit is contin turned on to form a current bypass path, and the unit output voltage decreases to phase shift angle is adjusted to compensate for the output voltage of the bypassed unit. Figure 8 shows the state of the topology with a controllable failure. As sh Figure

Fault Ride-through Strategy under Controllable Faults
When a controllable fault occurs, the controllable IGBT in the unit is continuously turned on to form a current bypass path, and the unit output voltage decreases to 0. The phase shift angle is adjusted to compensate for the output voltage of the bypassed power unit. Figure 8 shows the state of the topology with a controllable failure. As shown in Figure Figure 8c, the mechanical switch of unit i is closed. Unit i enters the maintenance state. The systems of Figure 8b,c are kept running by the normal unit (green shaded). At this time, θ is calculated according to Equation (8). Figure 9 shows the fault ride-through process of controllable faults.

Fault Ride-through Strategy under Uncontrollable Faults
Due to the unavailable IGBT under the uncontrollable fault, it is necessary to use an external switch for fault ride-through. At present, some permanent magnet mechanisms can be closed within 3 ms, which are widely used in direct current transmission. The thyristor can be closed at the microsecond level. Generally, two thyristors are used in reverse parallel connection as a bypass device, but the power loss and requirements for the trigger power is relatively high. The above bypass scheme is high-cost when applied to CHBC with many units. In this section, an adaptive fault ride-through strategy based on mechanical switches under uncontrollable faults is proposed.
The output voltage of the power unit in Figure 6 is:

Fault Ride-through Strategy under Uncontrollable Faults
Due to the unavailable IGBT under the uncontrollable fault, it is necessary t external switch for fault ride-through. At present, some permanent magnet mec can be closed within 3 ms, which are widely used in direct current transmission. ristor can be closed at the microsecond level. Generally, two thyristors are used in parallel connection as a bypass device, but the power loss and requirements for th power is relatively high. The above bypass scheme is high-cost when applied t with many units. In this section, an adaptive fault ride-through strategy based on ical switches under uncontrollable faults is proposed.
The output voltage of the power unit in Figure 6 is:

Fault Ride-through Strategy under Uncontrollable Faults
Due to the unavailable IGBT under the uncontrollable fault, it is necessary to use an external switch for fault ride-through. At present, some permanent magnet mechanisms can be closed within 3 ms, which are widely used in direct current transmission. The thyristor can be closed at the microsecond level. Generally, two thyristors are used in reverse parallel connection as a bypass device, but the power loss and requirements for the trigger power is relatively high. The above bypass scheme is high-cost when applied to CHBC with many units. In this section, an adaptive fault ride-through strategy based on mechanical switches under uncontrollable faults is proposed.
The output voltage of the power unit in Figure 6 is: v i-fault is unrelated with S mi , which is mainly related to the current state. Figure 10 shows the state of the topology with a controllable failure. As shown in Figure 10a, the most serious uncontrollable fault occurs in unit i: all IGBTs blocked. The equivalent circuit of the system is shown in Figure 10b. Unit i is already in an uncontrollable state.
vi-fault is unrelated with Smi, which is mainly related to the current state. Figure 10 shows the state of the topology with a controllable failure. As shown in Figure 10a, the most serious uncontrollable fault occurs in unit i: all IGBTs blocked. The equivalent circuit of the system is shown in Figure 10b. Unit i is already in an uncontrollable state. The closing time tc of a mechanical contactor is generally 100-130 ms. After the contactor closing, vi-fault = 0, adjust the θ according to Equation (8). To allow PQID to pass the closing delay of tc, the control strategy needs to be adjusted to optimize the output voltage within tc.
Assuming that an uncontrollable fault occurs in unit x of phase A, the output voltage vA of phase A can be calculated.
There are two ways to optimize vA: intra-phase optimization and inter-phase optimization.

Intra-Phase Optimization
According to Equation (10)   The closing time t c of a mechanical contactor is generally 100-130 ms. After the contactor closing, v i-fault = 0, adjust the θ according to Equation (8). To allow PQID to pass the closing delay of t c , the control strategy needs to be adjusted to optimize the output voltage within t c .
Assuming that an uncontrollable fault occurs in unit x of phase A, the output voltage v A of phase A can be calculated.
There are two ways to optimize v A : intra-phase optimization and inter-phase optimization.

Intra-Phase Optimization
According to Equation (10), calculate the output voltage of the power unit v i-fault under an uncontrollable fault. The normal power units in phase are used to compensate v i-fault . Figure 11 shows the topology state of the intra-phase optimization. As shown in Figure 11a    A phase after the fault occurs, which is modulated by all normal units, and U i-fault is the output voltage of the faulted unit. This method evenly distributes the task of compensating the voltage of the faulty unit to all normal power units in the phase, which is suitable for working conditions with low modulation.  Figure 12 is the vector diagram of phase voltage optimization; U'A is the voltage of A phase before the fault occurs, which is modulated by all power units. UA is the voltage o A phase after the fault occurs, which is modulated by all normal units, and Ui-fault is th output voltage of the faulted unit. This method evenly distributes the task of compensa ing the voltage of the faulty unit to all normal power units in the phase, which is suitabl for working conditions with low modulation.

Inter-Phase Optimization
Unlike the intra-phase optimization, the inter-phase optimization does not optimiz the phase voltage but directly optimizes the line voltage. Figure 13 shows the topolog state of intra-phase optimization. The sum of the normal units' output voltages of phas A is vpA. The output voltages of phase B and phase C are increased by vi-fault than norma It can be seen from the figure that the line voltage can remain normal.

Inter-Phase Optimization
Unlike the intra-phase optimization, the inter-phase optimization does not optimize the phase voltage but directly optimizes the line voltage. Figure 13 shows the topology state of intra-phase optimization. The sum of the normal units' output voltages of phase A is v pA . The output voltages of phase B and phase C are increased by v i-fault than normal. It can be seen from the figure that the line voltage can remain normal.       Figure 14 shows the topology state after the mechanical switch closed, vi system can keep the line voltage stable without adjusting the control strategy.     Comparing Figures 12 and 15, it can be seen that the inter-phase optimization is equivalent to the neutral point shifted by vi-fault. The fault ride-through process under uncontrollable faults is shown in Figure 16. Comparing Figures 12 and 15, it can be seen that the inter-phase optimization is equivalent to the neutral point shifted by v i-fault . The fault ride-through process under uncontrollable faults is shown in Figure 16. Comparing Figures 12 and 15, it can be seen that the inter-phase optimizati equivalent to the neutral point shifted by vi-fault. The fault ride-through process unde controllable faults is shown in Figure 16.

Simulation and Verification
In this section, a PQID model is built in PSCAD/EMTDC (Manitoba Hydro Int tional Ltd., Manitoba, Canada) to verify the proposed fault ride-through strategy. Ta shows the simulation parameters.

Simulation and Verification
In this section, a PQID model is built in PSCAD/EMTDC (Manitoba Hydro International Ltd., Manitoba, Canada) to verify the proposed fault ride-through strategy. Table 1 shows the simulation parameters.

Controllable Fault Simulation
The simulation conditions are set as follows. Figure 17 is the timeline of controllable fault simulation. The fault occurs in 150 ms. The fault detection time is 3 ms, and the mechanical switch closing time is 130 ms.

Controllable Fault Simulation
The simulation conditions are set as follows. Figure 17  In medium voltage distribution networks, line voltage is usually used age quality. Figure 18 shows the output line voltage without fault ride-thro Figure 19 shows the output line voltage with fault ride-through strategy. the voltage waveform in Figure 19 is significantly better than that in Figur ride-through strategy proposed in this paper can significantly improve the v degradation caused by controllable faults.  In medium voltage distribution networks, line voltage is usually used to assess voltage quality. Figure 18 shows the output line voltage without fault ride-through strategy. Figure 19 shows the output line voltage with fault ride-through strategy. The quality of the voltage waveform in Figure 19 is significantly better than that in Figure 18. The fault ride-through strategy proposed in this paper can significantly improve the voltage quality degradation caused by controllable faults.
The simulation conditions are set as follows. Figure 17 is the timeline of contr fault simulation. The fault occurs in 150 ms. The fault detection time is 3 ms, and t chanical switch closing time is 130 ms. In medium voltage distribution networks, line voltage is usually used to asse age quality. Figure 18 shows the output line voltage without fault ride-through st Figure 19 shows the output line voltage with fault ride-through strategy. The qu the voltage waveform in Figure 19 is significantly better than that in Figure 18. Th ride-through strategy proposed in this paper can significantly improve the voltage degradation caused by controllable faults.  In medium voltage distribution networks, line voltage is usually used to asse age quality. Figure 18 shows the output line voltage without fault ride-through st Figure 19 shows the output line voltage with fault ride-through strategy. The qu the voltage waveform in Figure 19 is significantly better than that in Figure 18. Th ride-through strategy proposed in this paper can significantly improve the voltage degradation caused by controllable faults.   Figure 20 shows the H-bridge module topology of the simulation model. The H-bridge output port is connected in parallel with a lightning arrester and a mechanical switch. The mechanical switch performs as a reliable bypass. Lightning arresters are used to absorb excess energy. Figure 21 is the timeline of uncontrollable fault simulation. The fault occurs in 150 ms. The fault detection time is 3 ms, and the mechanical switch closing time is 130 ms. Figure 20 shows the H-bridge module topology of the simulation model. The H bridge output port is connected in parallel with a lightning arrester and a mechanica switch. The mechanical switch performs as a reliable bypass. Lightning arresters are used to absorb excess energy. Figure 21 is the timeline of uncontrollable fault simulation. Th fault occurs in 150 ms. The fault detection time is 3 ms, and the mechanical switch closing time is 130 ms.  Figure 22 shows the output line voltage without fault ride-through strategy. It can b seen that the line voltage quality has dropped seriously. Figure 23 is the port current o the power unit. The lightning arrester breaks down before 180 ms to absorb the exces power of the power unit. The arrester actively breaks down to prevent overcurrent. Th mechanical switch is closed at 280 ms, and the arrester current is 0.   Figure 22 shows the output line voltage without fault ride-through stra seen that the line voltage quality has dropped seriously. Figure 23 is the p the power unit. The lightning arrester breaks down before 180 ms to abs power of the power unit. The arrester actively breaks down to prevent ov mechanical switch is closed at 280 ms, and the arrester current is 0.   Figure 22 shows the output line voltage without fault ride-through strategy. It can be seen that the line voltage quality has dropped seriously. Figure 23 is the port current of the power unit. The lightning arrester breaks down before 180 ms to absorb the excess power of the power unit. The arrester actively breaks down to prevent overcurrent. The mechanical switch is closed at 280 ms, and the arrester current is 0.

vi
fault occurs in 150 ms. The fault detection time is 3 ms, and the mechanical switch time is 130 ms.  Figure 22 shows the output line voltage without fault ride-through strategy. It seen that the line voltage quality has dropped seriously. Figure 23 is the port cur the power unit. The lightning arrester breaks down before 180 ms to absorb the power of the power unit. The arrester actively breaks down to prevent overcurre mechanical switch is closed at 280 ms, and the arrester current is 0.  Figure 24 is the output line voltage with intra-phase optimization. The quality of the voltage waveform in Figure 24 is significantly better than that in Figure 22. Figure 25 is the phase voltage. As the figure shows, intra-phase optimization achieves voltage balance by compensating the phase voltage. Figure 23. Current of power unit port. Figure 24 is the output line voltage with intra-phase optimization. The quality voltage waveform in Figure 24 is significantly better than that in Figure 22. Figu the phase voltage. As the figure shows, intra-phase optimization achieves voltage b by compensating the phase voltage.

Voltage Stability Analysis
This section mainly analyzes the stability of the line voltage vAB, which is ch ized by amplitude and harmonics. Figures 28 and 29 are the voltage amplitude. V amplitude voltage with the fault ride-through strategy is closer to 10 kV than that w fault ride-through strategy. As shown Figures 28 and 29, The voltage amplitude sented by the solid line is close to 8 kV, which is already lower than the national sta The fault ride-through strategy proposed in this paper can effectively maintain voltage amplitude during the fault.

Voltage Stability Analysis
This section mainly analyzes the stability of the line voltage v AB , which is characterized by amplitude and harmonics. Figures 28 and 29 are the voltage amplitude. Voltage amplitude voltage with the fault ride-through strategy is closer to 10 kV than that without fault ride-through strategy. As shown Figures 28 and 29, The voltage amplitude represented by the solid line is close to 8 kV, which is already lower than the national standard. The fault ride-through strategy proposed in this paper can effectively maintain the line voltage amplitude during the fault.

Voltage Stability Analysis
This section mainly analyzes the stability of the line voltage vAB, which is cha ized by amplitude and harmonics. Figures 28 and 29 are the voltage amplitude. V amplitude voltage with the fault ride-through strategy is closer to 10 kV than that w fault ride-through strategy. As shown Figures 28 and 29, The voltage amplitude sented by the solid line is close to 8 kV, which is already lower than the national sta The fault ride-through strategy proposed in this paper can effectively maintain t voltage amplitude during the fault. Figures 30 and 31 are total harmonic distortion (THD). Due to the existence fault detection delay, the THD with the fault ride-through strategy will rise brie the rise will not exceed 4%. However, THD without a fault ride-through strategy w tinue to rise sharply. As shown in Figure 31, the THD represented by the solid l exceeded the national standard. The fault ride-through strategy proposed in this can effectively prevent line voltage distortion. Figures 30 and 31 are total harmonic distortion (THD). Due to the existence of the fault detection delay, the THD with the fault ride-through strategy will rise briefly, but the rise will not exceed 4%. However, THD without a fault ride-through strategy will continue to rise sharply. As shown in Figure 31  Figures 30 and 31 are total harmonic distortion (THD). Due to the existence fault detection delay, the THD with the fault ride-through strategy will rise brie the rise will not exceed 4%. However, THD without a fault ride-through strategy w tinue to rise sharply. As shown in Figure 31, the THD represented by the solid l exceeded the national standard. The fault ride-through strategy proposed in this can effectively prevent line voltage distortion.

Reliability Analysis of Fault Ride-Through Strategy
The safety of components in the power unit during a fault is also the focus o tion. Figure 32 shows the vC of controllable failure. Figure 33 shows the vC of unco ble failure. VCES is the saturation voltage of the IGBT. When the voltage across the I higher than VCES, IGBT may break down. The DC voltage of the power unit with fau through will not continue to rise. It can be seen from the figure that the fault ride-th strategy can prevent IGBT overvoltage. Figures 30 and 31 are total harmonic distortion (THD). Due to the existence fault detection delay, the THD with the fault ride-through strategy will rise brie the rise will not exceed 4%. However, THD without a fault ride-through strategy w tinue to rise sharply. As shown in Figure 31, the THD represented by the solid l exceeded the national standard. The fault ride-through strategy proposed in thi can effectively prevent line voltage distortion.

Reliability Analysis of Fault Ride-Through Strategy
The safety of components in the power unit during a fault is also the focus o tion. Figure 32 shows the vC of controllable failure. Figure 33 shows the vC of unco ble failure. VCES is the saturation voltage of the IGBT. When the voltage across the higher than VCES, IGBT may break down. The DC voltage of the power unit with fau through will not continue to rise. It can be seen from the figure that the fault ride-t strategy can prevent IGBT overvoltage.

Reliability Analysis of Fault Ride-through Strategy
The safety of components in the power unit during a fault is also the focus of attention. Figure 32 shows the v C of controllable failure. Figure 33 shows the v C of uncontrollable failure. V CES is the saturation voltage of the IGBT. When the voltage across the IGBT is higher than V CES , IGBT may break down. The DC voltage of the power unit with fault ridethrough will not continue to rise. It can be seen from the figure that the fault ride-through strategy can prevent IGBT overvoltage.

Power Transmission Analysis
This section mainly focuses on the active and reactive power generated by t and CHB, the active and reactive power absorbed by the load. The efficiency of the is mainly evaluated by active power transmission. Figure 34 shows the power tr sion of the system under controllable fault. Figures 35 and 36 are the power trans of the system under uncontrollable faults. The power of the grid and the load are re stable. It can be seen that the fault ride-through strategy proposed in this paper h effect on the power transmission of the device.

Power Transmission Analysis
This section mainly focuses on the active and reactive power generated by the grid and CHB, the active and reactive power absorbed by the load. The efficiency of the device is mainly evaluated by active power transmission. Figure 34 shows the power transmission of the system under controllable fault. Figures 35 and 36 are the power transmission of the system under uncontrollable faults. The power of the grid and the load are relatively stable. It can be seen that the fault ride-through strategy proposed in this paper has little effect on the power transmission of the device.

Power Transmission Analysis
This section mainly focuses on the active and reactive power generated b and CHB, the active and reactive power absorbed by the load. The efficiency of is mainly evaluated by active power transmission. Figure 34 shows the power sion of the system under controllable fault. Figures 35 and 36 are the power tra of the system under uncontrollable faults. The power of the grid and the load are stable. It can be seen that the fault ride-through strategy proposed in this pape effect on the power transmission of the device.

Conclusions
This paper studies the fault ride-through strategy for the H-bridge power u of PQID and proposes a mechanical-switches based adaptive fault ride-throug The conclusions are as follows: (1) Conventional mechanical switches cannot effectively bypass the failed p Its slow closing speed will cause the output voltage quality to drop and t nents to be damaged. (2) When a controllable fault occurs in the power unit, the internal switch by ride-through strategy is adopted. An intra-phase optimization or an inter timization fault ride-through strategy is adopted when an uncontrollable f in the power unit.

Conclusions
This paper studies the fault ride-through strategy for the H-bridge power unit failure of PQID and proposes a mechanical-switches based adaptive fault ride-through strategy. The conclusions are as follows: (1) Conventional mechanical switches cannot effectively bypass the failed power unit. Its slow closing speed will cause the output voltage quality to drop and the components to be damaged. (2) When a controllable fault occurs in the power unit, the internal switch bypass fault ride-through strategy is adopted. An intra-phase optimization or an inter-phase optimization fault ride-through strategy is adopted when an uncontrollable fault occurs in the power unit.