Finite Control Set—Model Predictive Control with Non-Spread Spectrum and Reduced Switching Frequency Applied to Multi-Cell Rectiﬁers

: Multi-cell converters are widely used in medium-voltage AC drives. This equipment is based on power cells that operate with low-voltage-rating semiconductors and require an input multipulse transformer. This transformer cancels the low-frequency current harmonics generated by the three-phase diode-based rectiﬁer. Unfortunately, this transformer is bulky, heavy, expensive, and does not extend the existing power cell (three-phase rectiﬁer—Direct Current (DC) voltage-link— single-phase inverter) to the transformer. In this study, a harmonic cancelation method based on ﬁnite control set-model predictive control (FCS–MPC), extending the power cell’s modularity to the input transformer. On the other hand, it considers treating the two disadvantages of the FCS–MPC: High switching frequency and spread spectrum. The details were developed in theory and practice to obtain satisfactory experimental results.


Introduction
Multicell converters are widely used in medium-voltage applications, such as AC drives, active filters, electric vehicles, and PV farms [1]. This type of converter generates high voltage in the inverter stage through the series connection of power cells that use low-voltage semiconductors. Another characteristic of this type of converter is the use of an input multipulse transformer [2], which allows the harmonic cancelation of low-frequency current harmonics generated by the three-phase diode rectifier, obtaining an input current with low THD and a near unitary displacement factor.
In general, this type of converter has the following characteristics: (i) Low harmonic distortion in the AC output voltage, (ii) low switching frequency, and (iii) low common voltage. Thus, these converters can be classified into the following topologies: Neutral Point Clamped (NPC) [3], Cascaded H-Bridge (CHB) [4], and capacitor clamped [5].
This work is focused on a multicell converter based on CHB, which is widely used in the industry, where the power cells are fed by an input multipulse transformer. [6]. Each cell comprises a three-phase diode-based rectifier, a DC link based on a capacitor, and a single-phase voltage source inverter (VSI). For this power cell, using an input transformer is essential because it allows the generation of isolated DC sources.
The three-phase diode rectifier's cancellation of the input current harmonics in multicell converters uses an input multipulse transformer [6][7][8]. Although from the point of view of energy efficiency, for non-linear load power applications, the transformer must not operate at its nominal power [9], the preceding is due to a possible bad design, where it was not considered the current flowing through the transformer has harmonic content. This has a strong economic impact, especially in the industry [10], where a correct transformer design based on the load it will supply (K-Factor) can have a return rate of 25%. Another improvement in multicell converters is the use of modular transformers that improve both the harmonic cancellation of the input currents and a 15% increase in power density [11].
Modifications have been made in the topology shown [4]. It consists of changes in the multipulse transformer input with a phase shift in the secondary, for a transformer with identical secondaries and AFE rectifiers allowing bidirectional management of the flow of power [12]. Another modification presented in [13] unbalances the input voltages, and the load does not affect the input and output currents of the converter, obtaining satisfactory results. The third modification to this topology is seen in [14], where it is proposed to cancel the low-frequency harmonics by generating a switching pattern and transformer phase shift, achieving an input current with 23rd and 25th harmonics. Finally, a modification made in the rectifier stage is the use of AFE rectifiers; the novelty is using a PIR controller to manipulate the input currents of these rectifiers [15]; despite this, the multipulse transformer is still needed. From the point of view of high-power rectifiers [16], a multicell rectifier with low switching frequency is presented, which seeks to be friendly to the electrical network. For this, an optimal modulation is shown, which is compared to SHE. The result of this technique is slightly better than SHE, but both have the disadvantage of using tables to obtain the shooting angles.
Model predictive control (MPC) is a widely used control strategy in power converters [17,18]. A significant feature of MPC is the possibility of including nonlinearities and restrictions on the operation of the converter in a simple manner, in addition to the natural use of the discrete nature of power converters, and achieving a rapid response to changes in references [19].
This work evaluated the control scheme proposed in [20] based on FCS-MPC [21]. In this scheme, the use of a simple design input transformer (wye-wye) is proposed, where the input current control scheme minimizes the harmonics in each power cell. Thus, it is possible to replace the multipulse input transformer, as shown in Figure 1a. In addition, this control scheme achieves a low THD in the input current and unitary displacement factor. In addition, this control strategy covers two problems that affect the FCS-MPC: Spread spectrum and high switching frequency.
An input current reference is used in each AFE rectifier to the first drawback, which allows concentrating the harmonic spectrum around the harmonics, 6·n c ± 1, where n c is the number of cells. The second drawback is solved with a functional cost function FCS-MPC, which reduces the number of commutations in the semiconductor, achieving minimum losses due to switching. Finally, the above is demonstrated using the simulation and experimental results. Figure 1a shows the topology used, which is based on three power cells, n c = 3; (however, the analysis can be extended to arbitrary n c ), where each power cell is composed of an input transformer (wye-wye) and a voltage source AFE rectifier, where the load is resistive for simplicity. In each AFE rectifier, the input current reference abc si i has 18 pulses, which is similar to the input current in an 18-pulse diode-based rectifier. Therefore, the dominant harmonics were chosen as the 17th and 19th harmonics, 6·nc ± 1. The reasons for this are explained later in this section.

Topology and Harmonic Cancellation
On the other hand, these harmonics (17th and 19th) are unwanted in the input current of the multicell AFE rectifier abc g i ; therefore, the input fundamental current reference in each AFE rectifier abc si i has a phase shift angle α, as shown in Figure 1b. This angle is computed offline to obtain the minimum THD in the total input current of the multicell AFE rectifier abc g i . Therefore, such harmonics present in the input of the current power cells do not appear in the current multicell AFE rectifier abc p i .
To minimize the THD of the input current multicell AFE rectifier, the fundamental components of the input currents in each power cell [20] are shown in Figure 1b, where the phase shift angle α is responsible for minimizing the harmonics 17th and 19th in this case. Despite this, the magnitude 1 a p i is slightly different 2 a p i ; however 3 a p i , the AFE rectifiers work with equal active power. This imbalance in the magnitude of the input current in each AFE rectifier is negligible, as discussed later.
To compute the phase shift angle α, a mathematical characterization is necessary for the transformer's secondary currents; thus, references of the input current waveforms of the AFE rectifiers will be obtained [15]. The characterization is performed only for phase a; however, it is valid for phases b and c.
Thus, the overall input current in phase a a g i , is given by, The current a  In each AFE rectifier, the input current reference i abc si has 18 pulses, which is similar to the input current in an 18-pulse diode-based rectifier. Therefore, the dominant harmonics were chosen as the 17th and 19th harmonics, 6·n c ± 1. The reasons for this are explained later in this section.
On the other hand, these harmonics (17th and 19th) are unwanted in the input current of the multicell AFE rectifier i abc g ; therefore, the input fundamental current reference in each AFE rectifier i abc si has a phase shift angle α, as shown in Figure 1b. This angle is computed offline to obtain the minimum THD in the total input current of the multicell AFE rectifier i abc g . Therefore, such harmonics present in the input of the current power cells do not appear in the current multicell AFE rectifier i abc p . To minimize the THD of the input current multicell AFE rectifier, the fundamental components of the input currents in each power cell [20] are shown in Figure 1b, where the phase shift angle α is responsible for minimizing the harmonics 17th and 19th in this case. Despite this, the magnitude i a p1 is slightly different i a p2 ; however i a p3 , the AFE rectifiers work with equal active power. This imbalance in the magnitude of the input current in each AFE rectifier is negligible, as discussed later.
To compute the phase shift angle α, a mathematical characterization is necessary for the transformer's secondary currents; thus, references of the input current waveforms of the AFE rectifiers will be obtained [15]. The characterization is performed only for phase a; however, it is valid for phases b and c.
Thus, the overall input current in phase a i a g , is given by, . (1) The current i a g defined in (1) has a unitary displacement factor desired for the input voltage v a g .
Using (1) and (2), the THD function to minimize the input current multicell AFE rectifier for phase a is given by Thus, using (3), minimizing the THD of the input current multicell AFE rectifier is possible. This minimizes the 17th and 19th harmonics by obtaining an optimum value of α.
The constraint for α is given by, The THD minimization fmincon command was used (Matlab ® ), which minimizes no linear expressions considering the constraints. The minimization result was α = 6.671 • , which provided a 0.561% THD in the input current multicell AFE rectifier i a g . The waveforms shown in Figure 2 were generated from THD minimization and mathematical characterization. The waveforms shown in Figure 2a-c are used as input current references in the input current loop that will be managed by FCS-MPC. The amplitude of these waveforms depends on the output of the V DC PI controller in each power cell.
The input current references contain the 17th and 19th harmonics, as shown in Figure 2a-c, in which: (i) the harmonic content in the input current in each AFE rectifier is fixed, improving a drawback that has the FCS-MPC spread spectrum, obtaining a fixed spectrum; (ii) the equipment is modular and allows the generation of input current i abc g with low THD (0.561%), from currents i abc pi of inferior quality; (iii) there is an extension of the conventional power cell of the multicell converter to the input transformer, because harmonic minimization is performed through the control scheme; and (iv) the proposed input transformer (wye-wye with K-Factor = 3.00) has a simpler design than multipulse transformers (K-Factor = 9.00) [22]. Figure 2d shows that i a g it does not contain the 17th and 19th harmonics (actual amplitudes lower than 1%), because α is computed to minimize the harmonics present in the input current of the AFE rectifiers i a si . Figure 1b shows an apparent power imbalance in each AFE rectifier, and owing to the use of the phase shift angle α, the current i a p1 differs between i a p2 and i a p3 , but the value of α = 6.671 • is near zero; therefore, the apparent power imbalance can be neglected.
where abc si v is, Then, using (6) in (5) it follows that, .

AFE Rectifier Model
In each power cell, input current control is performed through FCS-MPC [21]. This type of control requires knowledge of the system model, which is necessary to obtain.
The system model is shown in Figure 3. As shown in Figure 3a, the power cell uses a wye-wye transformer, so it is preferable to obtain the input current model for each AFE rectifier, referred to as the primary winding of the input transformer. Moreover, the magnetic branch is neglected in the model.
Thus, applying the KVL in Figure 3b, it is obtained that, where v abc si is, Then, using (6) in (5) it follows that,  The input current model in each AFE rectifier, referred to as the primary winding of the transformer, is shown in (7). This model is valid for balanced AC voltage sources.
The result in (7) is valid for continuous time, and it is necessary to discretize it for use in the FCS-MPC, where a forward Euler approximation is used. The above is valid because of the low sampling time (50 [µs]), which is given by where Ts is the sampling time. Thus, employing (7) and (8) is obtained by referring to the primary winding of the discrete model of the input current AFE rectifier, Equation (9) shows that it is possible to predict the future behavior of the input current of each power cell through the semiconductor's previous state, system inputs, and state variables.

Control Scheme
The master-slave loop conforms to the control scheme. The master loop (outer) controls the VDC and the slave loop (inner) controls the input current of each power cell.

DC Voltage Link
A PI controller is used to manage the DC link voltage control in each power cell, as shown in Figure 4. By employing the transfer function defined in (10), it is possible to relate the input current and the DC link voltage in each power cell. Thus,  The input current model in each AFE rectifier, referred to as the primary winding of the transformer, is shown in (7). This model is valid for balanced AC voltage sources.
The result in (7) is valid for continuous time, and it is necessary to discretize it for use in the FCS-MPC, where a forward Euler approximation is used. The above is valid because of the low sampling time (50 [µs]), which is given by where T s is the sampling time. Thus, employing (7) and (8) is obtained by referring to the primary winding of the discrete model of the input current AFE rectifier, Equation (9) shows that it is possible to predict the future behavior of the input current of each power cell through the semiconductor's previous state, system inputs, and state variables.

Control Scheme
The master-slave loop conforms to the control scheme. The master loop (outer) controls the V DC and the slave loop (inner) controls the input current of each power cell.

DC Voltage Link
A PI controller is used to manage the DC link voltage control in each power cell, as shown in Figure 4. By employing the transfer function defined in (10), it is possible to relate the input current and the DC link voltage in each power cell. Thus, The PI controller output provides the reference amplitude value I(k) for the input current for the AFE rectifier because the current waveform is preset, as shown in Figure 2a-c. In addition, it contains the phase shift angle α, previously computed by THD minimization (3).

Input Current with a Reduced Switching Frequency
Once the current reference is generated, it is compared with the estimated value of the FCS-MPC.
The control scheme in Figure 4 considers delay compensation for calculation. For this reason, (9) can be rewritten for instant k + 2 (11).
Some approximations are performed in (11), and these are: v abc g (k + 1) ≈ v abc g (k) and V DCi (k + 1) ≈ V DC (k). This is possible because of the low sampling time used compared to the dynamics of these variables.
Using (11) and FCS-MPC, it is possible to test all the valid states of the AFE rectifier (Table 1) by choosing the state that minimizes the cost function defined below: (12)    The cost function defined in (12) corresponds to the control of the input current in each AFE rectifier.
The high switching frequency is another disadvantage of the FCS-MPC; consequently, the switching losses are high. To overcome this disadvantage, a cost function is added to penalize the state change in semiconductors [23]. Assuming the switch states in each AFE rectifier (Table 1), it is possible to determine the number of switches that switch to perform the transition from one state to another within the eight possible states of switching of each AFE rectifier, as shown in Table 2. Then, the cost function that considers the penalization of the state changes is, C sw depends on the state changes shown in Table 2, and k sw is a weighting factor associated with switching each AFE rectifier.
Finally, the overall cost function to control the input current in each power cell is: + k sw C sw s abc (k), s abc (k + 1) .

Semiconductors Losses
Semiconductor losses are associated with the switching and conduction processes, which depend on the semiconductor used. An analysis of the above processes is detailed below.

Switching Losses
Considering the non-ideal nature of the commutation process, the switching losses were analyzed [24], as shown in Figure 5.
IGBT switches are used in an AFE rectifier, and the losses in one switching period depend on the following factors: (i) Diode characteristics (reverse recovery time and current peak), (ii) IGBT characteristics (rise and fall time, tail time, and tail current), and (iii) stray inductance [25]. Fast recovery diodes are used in modern IGBTs; thus, the diode turn-on losses are less than 1% compared to the diode turn-off losses [26]; therefore, they are neglected in this analysis. Then, the estimated losses consider the IGBT turn-on shown in Figure 5a, IGBT turn-off in Figure 5b, and diode turn-off in Figure 5c, as in [22].

Conduction Losses
The conduction losses are dependent on the saturation voltage sat v and instantaneous current ( ) i t passing through [27]. The device saturation voltage can be modeled using a first-order linear approximation comprising a threshold voltage VT and a series resistance RT.
Thus, the average power dissipated due to conduction losses at the fundamental frequency is given by: IAVG is the average current flowing through the semiconductor, and IRMS is the RMS current flowing through the semiconductor. Finally, the dissipated energy during a period is: where TCOND is the semiconductor conduction time, and (17) is used to calculate the conduction losses.

Experimental Results
To verify the theoretical results, a low-power experimental prototype was built, as shown in Figure 6, which is based on the circuit shown in Figure 1a. The control scheme described in Figure 4 was tested in transient and steady-state conditions using the parameters shown in Table 3.

Conduction Losses
The conduction losses are dependent on the saturation voltage v sat and instantaneous current i(t) passing through [27]. The device saturation voltage can be modeled using a firstorder linear approximation comprising a threshold voltage V T and a series resistance Thus, the average power dissipated due to conduction losses at the fundamental frequency is given by: I AVG is the average current flowing through the semiconductor, and I RMS is the RMS current flowing through the semiconductor. Finally, the dissipated energy during a period is: where T COND is the semiconductor conduction time, and (17) is used to calculate the conduction losses.

Experimental Results
To verify the theoretical results, a low-power experimental prototype was built, as shown in Figure 6, which is based on the circuit shown in Figure 1a. The control scheme described in Figure 4 was tested in transient and steady-state conditions using the parameters shown in Table 3. This prototype was tested under two conditions for the input current loop in each power cell. The first condition is for ksw = 0.00 (FCS-MPC without a reduced switching frequency), and the second is for y ksw = 0.12; both values are used in (14) to evaluate the switching losses. The semiconductor used in the experimental setup was an IGBT Figure 6. Experimental setup. This prototype was tested under two conditions for the input current loop in each power cell. The first condition is for k sw = 0.00 (FCS-MPC without a reduced switching frequency), and the second is for y k sw = 0.12; both values are used in (14) to evaluate the switching losses. The semiconductor used in the experimental setup was an IGBT IRG4BC20UDPBF.
For this analysis, the current and voltage at the semiconductor were the same. In Figure 7a, the case for k sw = 0.00, where the loss distribution is almost symmetric between conduction and switching, achieves an efficiency of 91.00% with f sw = 6 kHz (average value). Then, in Figure 7b, for k sw = 0.12, the efficiency is 93.25%, with f sw = 3 kHz (average value) in the AFE rectifier. Because of the value of k sw , the switching losses are reduced, and the efficiency in each power cell increases.
The weight factor tuning, k sw , is made empirically, considering the input current THD in the power cells and DC link voltage response time to reference changes [28]. Figure 8a,b shows that the input currents of each power cell follow the reference imposed for both values of k sw using FCS-MPC. These currents contain the 17th and 19th harmonics, concentrating the harmonic content on a fixed frequency, avoiding the AC network resonance problems, as shown in Figure 8a,b. This prototype was tested under two conditions for the input current loop in each power cell. The first condition is for ksw = 0.00 (FCS-MPC without a reduced switching frequency), and the second is for y ksw = 0.12; both values are used in (14) to evaluate the switching losses. The semiconductor used in the experimental setup was an IGBT IRG4BC20UDPBF.
For this analysis, the current and voltage at the semiconductor were the same. In Figure 7a, the case for ksw = 0.00, where the loss distribution is almost symmetric between conduction and switching, achieves an efficiency of 91.00% with fsw = 6 kHz (average value). Then, in Figure 7b, for ksw = 0.12, the efficiency is 93.25%, with fsw = 3 kHz (average value) in the AFE rectifier. Because of the value of ksw, the switching losses are reduced, and the efficiency in each power cell increases.
The weight factor tuning, ksw, is made empirically, considering the input current THD in the power cells and DC link voltage response time to reference changes [28]. Figure 8a,b shows that the input currents of each power cell follow the reference imposed for both values of ksw using FCS-MPC. These currents contain the 17th and 19th harmonics, concentrating the harmonic content on a fixed frequency, avoiding the AC network resonance problems, as shown in Figure 8a,b. Then, these harmonics are canceled out through the phase shift angle α, which allows for obtaining an almost sinusoidal current a g i ,1.87% THD for ksw = 0.00, and 2.03% for ksw = 0.12. The presence of unwanted harmonics in the input currents is due to a reduction in the switching frequency and the number of points by period (N = 400), obtaining a resolution of 0.9° by point. Then, these harmonics are canceled out through the phase shift angle α, which allows for obtaining an almost sinusoidal current i a g , 1.87% THD for k sw = 0.00, and 2.03% for k sw = 0.12. The presence of unwanted harmonics in the input currents is due to a reduction in the switching frequency and the number of points by period (N = 400), obtaining a resolution of 0.9 • by point. Then, these harmonics are canceled out through the phase shift angle α, which allows for obtaining an almost sinusoidal current a g i ,1.87% THD for ksw = 0.00, and 2.03% for ksw = 0.12. The presence of unwanted harmonics in the input currents is due to a reduction in the switching frequency and the number of points by period (N = 400), obtaining a resolution of 0.9° by point. (a) Input current phase a in each AFE rectifier and input current multicell AFE rectifier for k sw = 0.00, (b) input current phase a in each AFE rectifier and input current multicell AFE rectifier for k sw = 0.12, (c) harmonic spectrum input current phase a in each AFE rectifier and input current multicell AFE rectifier for k sw = 0.00, (d) harmonic spectrum input current phase a in each AFE rectifier and input current multicell AFE rectifier for k sw = 0.12.
Despite this, THD minimization is performed correctly, and with i a g the THD is low. In the same way i a g , it has a unitary displacement for both values of k sw , as shown in Figure 9a Figure 10 depicts the behavior of the DC voltage loop (master loop). In Figure 10a,b, the transient response of the DC voltage for each AFE rectifier is presented for ksw = 0.00 and ksw = 0.12, respectively. The VDC change reference is 55 (V) to 65 (V) and shows that the settling time is 400 ms with an overshoot of 5% in both cases, which is expected due to these PI tuning parameters. Using a reduced switching frequency in the inner loop, the input current does not show differences in the transient responses in the outer-loop voltage DC.
Owing to the control scheme used, the master-slave loop, any change in the reference voltages DC, 55 (V) to 65 (V), affects the input currents of the AFE rectifiers, as shown in Figure 10c,d.
Finally, the steady-state performance of the DC voltage loop for both ksw values is identical, with a ripple below 2% (Figure 10e-f). This DC voltage ripple is at a fundamental frequency because it tracks the input current reference, generating a small second harmonic in the input current in each power cell, thus ri i has a small fundamental component.

Conclusions
A harmonic minimization strategy for a multicell AFE rectifier based on FCS-MPC with a non-spread spectrum and reduced switching frequency is presented. The topology is tested considering a cost function that reduces the state changes in the semiconductors and input current reference preset, overcoming two drawbacks of the FCS-MPC: Spread spectrum and high switching frequency. The utilization of an input current reference preset for each AFE rectifier allows the concentration of current harmonics at a fixed value, avoiding a spread spectrum and achieving 2.03% THD in the input current multicell AFE rectifier by offline calculation of the phase shift angle α through THD minimization. Furthermore, the use of a function that considers the state changes in the semiconductors allows a reduction in the switching frequency in the input current loop managed with FCS-MPC, improving the efficiency of the multicell AFE rectifier, from 91.00% (ksw = 0.00) to 93.25% (ksw = 0.12). Finally, implementing a reduced switching strategy in a masterslave loop allows proper control of the DC link voltage in each AFE rectifier. Satisfactory experimental results prove the theoretical results.   Figure 10a,b, the transient response of the DC voltage for each AFE rectifier is presented for k sw = 0.00 and k sw = 0.12, respectively. The V DC change reference is 55 (V) to 65 (V) and shows that the settling time is 400 ms with an overshoot of 5% in both cases, which is expected due to these PI tuning parameters. Using a reduced switching frequency in the inner loop, the input current does not show differences in the transient responses in the outer-loop voltage DC.
Owing to the control scheme used, the master-slave loop, any change in the reference voltages DC, 55 (V) to 65 (V), affects the input currents of the AFE rectifiers, as shown in Figure 10c,d.
Finally, the steady-state performance of the DC voltage loop for both k sw values is identical, with a ripple below 2% (Figure 10e-f). This DC voltage ripple is at a fundamental frequency because it tracks the input current reference, generating a small second harmonic in the input current in each power cell, thus i ri has a small fundamental component.

Conclusions
A harmonic minimization strategy for a multicell AFE rectifier based on FCS-MPC with a non-spread spectrum and reduced switching frequency is presented. The topology is tested considering a cost function that reduces the state changes in the semiconductors and input current reference preset, overcoming two drawbacks of the FCS-MPC: Spread spectrum and high switching frequency. The utilization of an input current reference preset for each AFE rectifier allows the concentration of current harmonics at a fixed value, avoiding a spread spectrum and achieving 2.03% THD in the input current multicell AFE rectifier by offline calculation of the phase shift angle α through THD minimization. Furthermore, the use of a function that considers the state changes in the semiconductors allows a reduction in the switching frequency in the input current loop managed with FCS-MPC, improving the efficiency of the multicell AFE rectifier, from 91.00% (k sw = 0.00) to 93.25% (k sw = 0.12). Finally, implementing a reduced switching strategy in a masterslave loop allows proper control of the DC link voltage in each AFE rectifier. Satisfactory experimental results prove the theoretical results.