Adaptive Impedance-Conditioned Phase-Locked Loop for the VSC Converter Connected to Weak Grid †

† This paper is an extension of our paper “Analysis of steady-state power transfer capability and dynamic performance of VSC-HVDC with impedance-compensated synchronisation method connected to weak AC grid”, here we proposed Adaptive Impedance-Conditioned Phase-Locked Loop. Abstract: In this paper, an adaptive version of the impedance-conditioned phase-locked loop (IC-PLL), namely the adaptive IC-PLL (AIC-PLL), is proposed. The IC-PLL has recently been proposed to address the issue of synchronisation with a weak AC grid by supplementing the conventional synchronous reference frame phase-locked loop (SRF-PLL) with an additional virtual impedance term. The resulting IC-PLL aims to synchronise the converter to a remote and stronger point in the grid, hence increasing the upper bound on the achievable power transfer achieved by the VSC converter connected to the weak grid. However, the issue of the variable grid strength imposes another challenge in the operation of the IC-PLL. This is because the IC-PLL requires impedance estimation methods to estimate the value of the virtual impedance part. In AIC-PLL, the virtual impedance part is estimated by appending another dynamic loop in the exciting IC-PLL. In this method, an additional closed loop is involved so that the values of the virtual inductance and resistance are internally estimated and adapted. Hence, the VSC converter becomes effectively viable for the case of the grid strength variable, where the estimation of the grid impedance becomes unnecessary. The results show that the converter that relies on AIC-PLL has the ability to transfer power that is approximately equal to the theoretical maximum power while maintaining satisfactory dynamic performance.


Introduction
The integration of renewable energy sources, which are usually located in remote areas, is often realised using high voltage direct current (HVDC) based on voltage sources converter (VSC) technology [1].In the operation of the VSC converter, the phase angle of the AC grid voltage at the point of common coupling is considered to be critical to ensure correct synchronisation of the connected power converter with the grid.Through synchronisation, only information of the fundamental component is extracted and provided to the converters [2].This information is typically obtained using the so-called phase-locked loop (PLL).When the PLL is locked, the output signal of the PLL synchronises with the input signal, where both signals oscillate at the same frequency with a particular value of a phase shift [3].In addition, the phase angle of the grid voltage is utilised to transform the sinusoidally varying AC quantities into quasistationary dq-axis quantities by means of the Park transformation.Hence, three-phase AC currents are transformed into their corresponding active and reactive components that can then be controlled independently using standard PI/PID regulators [4][5][6].Therefore, the ability of the PLL to accurately synchronise with the grid and estimate the phase angle of the grid voltage at the point of common coupling directly impacts the performance of the overall closed-loop system, and, in particular, its ability to independently control the exchange of active and reactive power with the AC grid at the point of common coupling.Hence, if PLL loses synchronisation with the grid, then, as a consequence, the corresponding VSC converter will also lose synchronisation with the AC system to which it is connected [7].
The renewable energy sources are usually integrated into grids with long transmission lines, which leads to a large value of the Thevenin equivalent AC grid impedance, and such a system is called a "weak grid" [8,9].Typically, the strength of the grid is measured by the short circuit ratio (SCR).According to [10,11], the SCR is the ratio of the short circuit capacity to DC link rated power, and it is mathematically defined as SCR = S ac P dc = U 2 Z g P dc . ( where S ac is the short circuit capacity of the AC system at the point of common coupling and P dc is the rated DC power of the HVDC link.If the voltage at PCC is assumed to be identical to the base value, and the rated power of the HVDC is used as the base power of the AC system, Equation ( 1) can be further simplified as where U base and Z base are the base values of the voltage and impedance, respectively, and Z g (p.u.) is the value of the impedance in per unit.Based on [10], the strength of the AC system is strong if SCR > 3, 2 < SCR < 3 for a weak grid and SCR < 2 for a very weak grid.
Weak grid connections impose challenges on the operation of the VSC-HVDC system.The voltage at the PCC becomes more sensitive to power variations in the case of the weak grid connections; this, in turn, will affect the stability and dynamic performance of the system [12,13].The high sensitivity to power variations leads to high voltage fluctuations.Therefore, the utilised PLL needs to be sufficiently fast to lock with the variations in the voltage.However, fast PLL, i.e., large bandwidth, leads to high frequency components and noise to propagate through the system and causing system instability [14].In addition, there is a theoretical limitation for each value of SCR on the maximum power that the VSC-HVDC system can transmit to or from the AC system [10,15].Another challenge emerges when the converter connected to the weak AC grid, which is the mutual coupling in controlling the active power and voltage.The interactions between the active power control and voltage control increase as the value of the grid impedance increases [16].Therefore, it is essential to consider the PLL both in terms of the static (steady-state) power transfer and the dynamic performance of the power converter.
Hence, several modifications in the PLL are suggested to deal with this problem.In [17,18], the voltage sensorless technique was proposed.In this method, a virtual flux concept is utilised to synchronise the converter with the grid at the point of synchronisation without any needing for the physical sensor, where PLL uses flux instead of the voltage to generate the angle of the point of synchronisation.However, this technique needs for advanced estimation method for providing the information of the grid impedance.Another approach that is suggested to deal with a weak grid problem is modifying the SRF-PLL by attaching a damping factor term in order to suppress the oscillation that exhibits in the voltage at PCC due to the weak grid connections [19].It was shown that with a certain value of the damping factor, the system stability is enhanced.However, this approach is limited to a weak grid with a SCR > 1.83.
In [20,21], the impedance-conditioned phase-locked loop (IC-PLL) is proposed to address the issue of synchronisation with weak AC grid by supplementing the conventional synchronous reference frame phase-locked loop (SRF-PLL) with additional virtual impedance term.As a result, increasing the upper bound on the achievable power transfer achieved by the VSC converter connected to the weak grid [21].However, this approach requires for the grid impedance to be estimated accurately so that the virtual impedance branch compensates the high-value grid impedance.Hence, the VSC converter is synchronised to the point at the infinite bus voltage, where the voltage operates in a relatively robust manner concerning the perturbations that happen in the voltage at PCC. Refs.[22,23] show that the value of the virtual impedance has an impact on the dynamic performance of the system.The system provides the optimal dynamic response when the value of the virtual impedance equal to the value of the grid impedance.The task of grid synchronisation becomes particularly challenging in the cases where the grid impedance is varied, which is the case that IC-PLL needs for adapting the value of the virtual impedance so that the VSC converter maintains the synchronisation with the infinite bus voltage.
In the literature, the approaches that are used to estimate the value of the grid impedance is based on the deliberate creation of a disturbance at the PCC, and the value of impedance is calculated based on the grid response to this distortion.These disturbances can be based on power variation in both active and reactive power at the PCC [24] and a current spike at PCC [25].However, the accuracy of the estimation depends on the size of the disturbances, which may become challenging in the case of a weak grid system.In addition, these approaches require for additional signal processing method to deal with the influence of the nonlinear loads connected close to PCC.
Therefore, the proposed AIC-PLL has the ability to estimate the value of the grid impedance so that the VSC converter maintains the synchronisation with the infinite bus voltage, without any requirements for the sophisticated methods of the impedance value estimation.Furthermore, this method does not require any source of disturbance, which is essential in the other methods, for the estimation of the accurate value of the grid impedance.Therefore, the VSC converter that uses AIC-PLL has the ability to transfer power equals to maximum theoretical power with a satisfactory dynamic performance in the case of the grid impedance variation.
The paper is organised as follows.In Section 2, we provide a general description of the studied system.In Section 3, we explain the operation limits of the VSC-HVDC system, where the maximum theoretical power and the maximum power that the VSC-HVDC system can transfer are explained.Descriptions about different types of PLL, including the proposed AIC-PLL, are provided in Section 4. A study about stability limits for an AIC-PLLbased converter is provided in Section 5; in this section, a comparison between AIC-PLL and IC-PLL (virtual impedance equals to grid impedance) with the theoretical maximum power is given for a range of grid impedance.In Section 6, dynamic performance studies for AIC-PLL-and IC-PLL-based converters are given considering various parameters.The impact of the AIC-PLL low pass filter on the dynamic performance of the system is described in Section 7. Finally, in Section 8, we provide the conclusion.

Overview of the General System Configuration
The studied system is shown in Figure 1.The overall system consists of two main parts: the upper part, which represents the AC network (in this part, R c and L c represent the converter resistance and inductance), and R g and L g represent the grid resistance and inductance, respectively.The C f represents the AC capacitor connected to the filter bus.The symbols v, u and e represent the voltage vector of the VSC converter, the filter bus and AC source, respectively.V, U and E are their corresponding voltage magnitudes.The AC source is considered as the voltage reference, and it is a constant-frequency stiff voltage source.The phase angle of v, u are θ v and θ u , respectively.The symbols P and Q are the active and reactive powers from the VSC to the AC system.The quantity i c is the current vector of the phase reactor, and i g is the current vector to the AC source.In this system, the active power and voltage magnitude are controlled at the point of common coupling through outer loop controller, by which the desired value of the converter current i * c is manipulated.The presuperscript c for any quantity refers to the converter side for that quantity, and postsubscripts d and q refer to d and q components.

Operation Limits of the VSC-HVDC System
The operation limit is defined in terms of the maximum power that the VSC converter can transfer in steady-state while maintaining the stability of the system.For a general power system consisting of two voltage sources given by U and E, interconnected via impedance Z g = R g + jX g , as shown in Figure 2, there is a theoretical maximum power that is considered the theoretical operation limit that cannot be exceeded [26].This theoretical maximum power is given by where all the values of the voltages and the AC circuit parameters are in per-unit quantities, and the sign '+' is for the inverter operation and '-' is for the rectifier operation.However, the VSC-HVDC system may not be able to transfer power equals to the theoretical maximum power P max , which is due to the presence of the feedback element, where the dynamic of this element may affect on the stability of the system.Therefore, in the case of the VSC-HVDC system shown in Figure 1, P max represents the maximum power that is transferred between the voltage u at PCC and the voltage e at the infinite bus and

Grid Synchronisation Techniques for Converter Connected to Weak Grid
In the following subsections, two types of grid synchronisation methods are presented.The first one is IC-PLL, which is presented in general.The second one is the proposed AIC-PLL, where this method is described in detail.

Impedance-Conditioned PLL (IC-PLL)
In this section, an impedance-conditioned PLL (IC-PLL)-based system is considered.In this technique, the converter is not synchronised to the voltage at the point of common coupling (PCC); it is instead synchronised to the virtual remote point in the stiff grid.Hence, this provides better synchronisation (as a result, better stability), as the converter is synchronised to a virtual point near to the infinite bus so that the PLL receives a signal with less fluctuation than the signal that is received by PLL in the case of synchronising to the weak grid point [21].The location of the virtual point depends on the value of the virtual impedance.When this value increases, the virtual point shifts from PCC to infinite bus.
The IC-PLL consists of SRF-PLL, which is the upper part in Figure 3, and the virtual impedance as indicated in the lower part in the figure.In the IC-PLL, the dq components of the voltage at the virtual point is obtained by subtracting the dq components of the voltage u at PCC from the voltage drop across the virtual impedance.The virtual impedance can be defined as and the virtual voltage, which is indicated in Figure 3 by its dq components u v d u v q , can be defined as where the additional inputs to the PLL is the grid side current i g in the dq frame [20], The mathematical model of the IC-PLL is defined as where θ PLL is the phase angle deviation between the PLL orientation and the grid voltage.
The mathematical model of the low pass filter of the IC-PLL is defined as in Equation (6).
where ω FL,PLL is the angular frequency of the PLL low pass filter.

Adaptive Impedance-Conditioned PLL (AIC-PLL)
The exiting IC-PLL is modified so that another closed loop is included in order to adapt the value of the virtual resistance and inductance of the virtual impedance part.As it is shown in Figure 4, the value of θ PLL is fed into two compensators H L (s) and H R (s), in order to generate the virtual inductance and resistance values Lv and Rv , respectively.To understand how the AIC-PLL functions in terms of the phase angles of the voltages, the block diagram in Figure 4 is simplified to be represented as in Figure 5.In Figure 5, two feedback closed loops simplify the AIC-PLL in Figure 4, where: The value of θ uv is the phase angle of the virtual voltage, which is the voltage across the virtual impedance.
In the outer loop, the value of the θ uv −→ θ u through manipulating the values of Lv and Rv where Lv −→ L g , Rv −→ R g .The angle (θ u − θ uv ) is the phase angle of the voltage at the point of synchronisation, which is (θ u − θ uv = 0) when the converter is synchronised to the infinite bus voltage.By the inner loop, which represents the traditional SRF-PLL, the estimated angle value θ PLL converges to the point of synchronisation angle, where θ PLL −→ (θ u − θ uv ).As a result of this and in the steady-state, the VSC converter is synchronised to the infinite bus voltage, where θ uv = θ u and θ PLL = 0.In order to demonstrate how the voltages and currents are manipulated in the AIC-PLL, the vector diagram is plotted in Figure 6.In Figure 6, the symbol U v is the magnitude of the voltage u v across the virtual impedance with its phase angle θ uv , and this angle is measured with respect to the voltage u at PCC.The voltage u v is aligned with the voltage u when the value of the virtual impedance is equal to zero ( Rv = 0, Lv = 0).In this case, the value of the angle θ uv = 0, i.e., the converter is synchronised to the voltage at PCC.Hence, the value of θ PLL = θ u which is fed into compensators H L (s) and H R (s) to generate Lv and Rv , respectively.As these values increase the voltage u v shifts away from voltage u toward voltage E (as shown in Figure 6), and as result of this, θ uv → θ u and θ PLL → 0.
The modelling of the VSC-HVDC system utilises AIC-PLL is the same as that one utilises IC-PLL with considering the following model of the AIC-PLL where Lv = ±(H L (s) where the sign (+) is for the inverter operation and (-) is for the rectifier operation.The reason for that is the voltage u at the PCC leads the voltage E at the infinite bus in the case of the inverter operation, i.e. the phase angle θ PLL is positive, while in the case of the rectifier operation, the voltage u lags the voltage E, which results in the phase angle θ PLL to be negative.

Stability Limits of AIC-PLL-Based VSC Converter
In order to study the stability of the system for various types of PLLs, the operating points of the system are obtained first.The operating points are calculated by solving f(x 0 , u 0 ) = 0 for x 0 numerically, where the f(x, u) is the set of the nonlinear Equation (A16) that are provided in the Appendix B. The maximum theoretical power that is calculated by Equation (3) for a certain value of the grid impedance is approximately equal to the maximum power by which the nonlinear equations return a real solution.However, the system may not be able to operate according to the calculated operating points, i.e., these operating points are unstable.The operating points x 0 are considered stable if all the eigenvalues of the matrix A, which is provided in the Appendix C, has negative real parts, where this method is referred as the first method of Lyapunov [27].
The results of the small signal stability analysis for different types of PLLs are shown in Figure 7, where U * = 1 p.u. for Z g = [0.1,2] p.u. and ω FL,PLL = 400 rad/s.Figure 7 shows the maximum transferred power in per unit for two VSC converters utilising two types of PLLs, IC-PLL with Z v g = Z g and AIC-PLL, for a range of values of grid impedance Z g and for the inverter and rectifier operations.It can be observed that the values of the maximum active power at which the system maintains stable for both types of the IC-PLL-and AIC-PLL-based converters are equal, and they are approximately equal to the theoretical maximum power.Therefore, the converter that utilises AIC-PLL is capable of reaching the maximum theoretical power transfer in the same way that the IC-PLL does, in spite the fact that the AIC-PLL does not require any information about the value of the grid impedance.Moreover, it can be concluded from this result that the AIC-PLL is able to imitate the IC-PLL with Z v g = Z g in terms of the power transfer capability, as the converter that utilises AIC-PLL is also synchronised to the infinite bus voltage E. Therefore, the AIC-PLL possibly replaces the IC-PLL in the case that the maximum power transfer is demanded, and the estimation of the value of the grid impedance is challenging, in particular, the grid strength changes.

Dynamic Performance Study for AIC-PLL-Based VSC Converter
In this section, the dynamic performance of the AIC-PLL-based converter is investigated for different points in the grid strength.The performance of the AIC-PLL-based system is studied by examining the dynamic response of the system to the changing in the value of the grid impedance and the value of the active power.For each point of the grid impedance, an experiment is conducted, and two step changes are applied.The first step is on the grid impedance, and this is to simulate the variation that may occur in the grid impedance value in the real system, and how the AIC-PLL has the ability to recover the changing in this value.The second step change is for the active power, and this is to examine the effectiveness of the AIC-PLL-based converter in terms of dealing with variation in active power.In order to demonstrate the effectiveness of the proposed method, the time-domain response of the active power for the AIC-PLL-based converter is compared with two cases of the IC-PLL-based converters.The first one is the IC-PLL with a constant value of the virtual impedance, i.e., the value of Z v g does not change according to the changing in the grid impedance.The second case is when the value of the Z v g is changing according to the changing in the grid impedance; hence, the relation Z v g = Z g is maintained during the operation of the system.
The first experiment is when the value of the grid impedance changes from Z g = 1 → 1.1 p.u. in the inverter operation; then, another step change in active power is applied which is P * = 0.9 → 1 p.u. Figures 8-10 show the responses of active power and θ PLL , respectively.Figure 8 shows the result of the time-domain response of the active power for different converters utilise different types of PLLs.It is clear from the figure the converter that utilises the IC-PLL with Z v g = Z g has the optimal response as it shows less oscillation than the other two approaches with less settling time.However, for the system that relays on the IC-PLL without updating the value of the virtual impedance (IC-PLL Z v g0 = 1 p.u.), the result shows that the time-domain response exhibits the highest oscillatory response.In the case that the system uses the proposed method AIC-PLL, the result shows that the time-domain response of the active power suffers far less oscillation than the IC-PLL with Z v g = 1 p.u., and it has slightly more oscillation amplitude than the case of IC-PLL with Z v g = Z g .Therefore, from this result, it can be concluded that the proposed AIC-PLL has the ability to recover the changing that occurs in the grid impedance.
Figure 9 shows the time-domain response of the active power for the applied step change in the active power for the VSC converters with different types of PLLs for the same above experiment at a different time where the value of the grid impedance Z g = 1.1 p.u.It can be seen from Figure 9 that the dynamic response for the case of IC-PLL with (Z v g = 1) exhibits higher overshoot than the other two cases.However, for the case of the converter that utilises AIC-PLL, the results in Figure 9 show that the response exhibits relatively higher oscillation amplitude than the other two cases.It can be concluded from the results in Figures 8 and 9 that the proposed AIC-PLL has the ability to deliver the maximum power with satisfactory dynamic performance.
Figure 10 shows the response of the phase angle θ PLL that is generated by different types of PLLs.In this figure, two y-axes for the phase angle θ PLL are included; the left y-axis is for the IC-PLL (Z v g = 1 p.u.), as it generates a larger phase angle scale than the other two cases.For the other two cases of the PLLs, the right y-axis is devoted.It is clear from the figure that the time-domain response that is generated by IC-PLL (Z v g = 1 p.u.) exhibits higher oscillatory with higher settling time than the other two cases.In addition, the value of θ PLL in the case of IC-PLL (Z v g = 1 p.u.) does not converge to zero.However, the result shows that the response of the θ PLL for the IC-PLL with (Z v g = Z g ) has more oscillatory than the case of AIC-PLL.This is because in the second case, another closed loop is involved in the AIC-PLL (Figure 4) where the θ PLL is considered as the control signal in this loop, and this is not the case for IC-PLL.Figures 11 and 12 show the response of the active power for the step change in the grid impedance (Z g = 1.7 → 2 p.u.), and the step change in the value of the active power, respectively.It can be observed that the responses of the active power for the cases of IC-PLL with (Z v g = Z g ) and the AIC-PLL have far better responses than the case of IC-PLL with (Z v g = 1.7 p.u.), as the first two cases provide lower oscillatory and settling time than the second case.Figures 11 and 12 also show that the response of the active power in the case of AIC-PLL is slightly better than the case of IC-PLL with (Z v g = Z g ), as the former case provides less oscillatory and settling time than the latter case.Therefore, it can be concluded that in the case of the weak grid, the converter that utilises AIC-PLL has the ability to replace the ideal IC-PLL in the case of the grid variation where the estimation of the grid is complicated.Figure 13 is the time domain response for the produced angle of the three types of PLL.
From the result in Figure 13, it can be concluded that the response of the phase angles for different types of PLLs have the same indication as for the result in Figure 10.In addition, By comparing Figures 10 and 13, it is clear that the dynamic response of the angle in the case of IC-PLL with (Z v g = Z g ) has a higher oscillatory amplitude in the case of the second experiment than the first experiment.It reaches 2 degrees for the second experiment while it reaches about 0.5 degree in the first case, which is due to the larger value of the grid impedance in the second case.The dynamic response of the angle θ PLL has an impact on the dynamic response of the active power, and the larger the value of the angle, the higher impact on the response of the active power.As a result of this, the response of the active power in the case of the AIC-PLL is relatively better than the case of the IC-PLL (Z v g = Z g ) for the larger value of the grid impedance, which is evident in Figures 11 and 12.
For further validation and reliability of the proposed AIC-PLL, experiments for different values of operating points and different values of the changing in the value of the grid impedance are conducted and the values of the sum of square of error (SSE) for the active power tracking are calculated.Two different operating points are chosen, 50% and 100% of the maximum transferred power of different values of the grid impedance.A step change in the active power is applied which is 1% of the selected operating point.Other experiments are also conducted, where the value of the active power is the maximum and the step change in the grid impedance is applied.Different step change percentages are applied and they depend on the value of the grid impedance, the larger the value of the grid impedance the smaller the value of the step change.The results of this experiment are presented in Figures 14,16  In Figures 14-17, bar charts represent the values of the SSE.A line graph represents the relative errors between the value of SSE of IC-PLL and SSE of AIC-PLL.It is clear from the results that both methods are approximate equals in terms of the dynamic responses, which indicates by the inconsiderable value of the relative error.In the case of the inverter operation, it can be concluded from the results in Figures 14 and 16 that the dynamic response of the IC-PLL-based converter is better than the AIC-PLL-based one for the strong grid.This difference in the dynamic response is reduced as the value of the grid impedance increases to become positive for the value of the Z g ≥ 1.8 p.u.However, in the case of the rectifier operation, the results in Figures 15 and 17 show that the converter that relies on the AIC-PLL provides a better dynamic response than the case of the IC-PLL-based converter for the whole range of the grid impedance.This is indicated by the value of the relative error, which is positive.In the case of the inverter operation, Figure 18 shows that the values of SSE for the IC-PLL-based converter is less than the value of SSE for the case of the AIC-PLL-based converter for Z g ≤ 1.6 p.u., which is indicated by the value of the error.The results also show that the error is positive for Z g ≥ 1.8 p.u., which indicates that the proposed method has the ability to provide better dynamic performance as the value of the grid impedance increases.In the case of the rectifier operation, Figure 19 shows that the converter that utilises AIC-PLL has the ability to provide better dynamic performance than the case of the system that uses IC-PLL for the whole range of the grid impedance.This is clear from the relative error line graph, which is positive for the whole range of the grid impedance value.

The Impact of Changing the Value of PLL Bandwidth on the AIC-PLL Dynamic Performance
In this section, the effect of changing the value of the PLL bandwidth ω FL,PLL , which is related to the PLL compensator bandwidth, on the dynamic performance of the converter is considered.The compensator bandwidth is 55% of the bandwidth of the PLL low pass filter [21].Therefore, when the value of the ω FL,PLL changes, the controller parameters change accordingly.In order to understand how the impact of changing the value of ω FL,PLL on the dynamic performance of the system, the root locus of the closed-loop system's poles in the s-domain is examined by sweeping the ω FL,PLL = 50 → 2000 rad/s, and the results are plotted in Figure 20.The participation matrix are then calculated, and the states that have the highest participation factors to the plotted eigenvalues are revealed.In Figure 20, the only eigenvalues λ 1,20,6 are included, since they have the highest rates of change in their positions than other eigenvalues.From the participation matrix (the participation matrix are provided in Appendix D), these eigenvalues have the highest participation factors to the states that are related to the PLL.These states are the phase angle θ PLL , the augmented state of the PLL's PI controller γ pll and the virtual voltage u v d,q .It is clear from the result that all the positions of the eigenvalues are shifted towards the left as the value of the PLL bandwidth increases.This indicates that for the case of the AIC-PLL the value of the PLL bandwidth does not have an impact on the stability and the dynamic performance of the system.This is because the value of θ PLL is minimal, which is due to the including of the estimation closed-loop.Therefore, this will not have an obvious impact on the dynamic performance of the active power.In order to understand this effect, the time-domain responses of the active power and the phase angle θ PLL for different values of ω FL,PLL = 100, 2000 rad/s are plotted in Figures 21 and 22   It is clear from Figure 21 that the dynamic response of the active power for the converter that utilises AIC-PLL with different values of ω FL,PLL are approximately identical, which indicates the fact that changing the value of PLL bandwidth does not have any impact on the response of the active power.Figure 22 shows the time-domain response of the phase angle θ PLL for different value of ω FL,PLL , and it is clear that as the value of the bandwidth increases the θ PLL has a better response in terms of the oscillatory and the settling time.This is due to the increase in the value of the PI compensator parameters, which in turn, increases the speed of the PI controller.In addition, the result in Figure 22 shows that the range of the variation is inconsiderable to have an impact on the response of the active power.

Conclusions
In this paper, an adaptive impedance-conditioned phase-locked loop (AIC-PLL) is proposed.In the AIC-PLL, another dynamic closed loop is included, in which the generated phase angle is utilised to generate the estimated values of the grid resistance and inductance.By this technique, the need for the estimation method in order to estimate the value of the grid impedance becomes redundant, which is important in the case of the grid impedance variable.The nonlinear mathematical model of the system is developed and the model is linearised in order to be used in the analytical study.The steady-state power transfer capability and the dynamic performance of the AIC-PLL-based converter are also considered in this paper.The results show that the converter that relies on AIC-PLL is capable of transferring an amount of power that is approximately equal to the theoretical maximum power.In terms of the dynamic performance, the results demonstrate that the AIC-PLL-based VSC converter provides a satisfactory dynamic response for different values of the grid impedance.Therefore, the AIC-PLL has the ability to replace the traditional IC-PLL in the case of grid variation.e u dq < l a t e x i t s h a 1 _ b a s e 6 4 = " X B V q M X U p D 9 6 H J x E K x D a s 3 W o f V a 0 = " > A A A B 7 3 i c b V B N S 8 N A E J 3 U r 1 q / q h 6 9 B I v g q S R V 0 G P R i 8 c K 9 g P a W D a b S b t 0 s 0 l 3 N 0 I J / R N e P C j i 1 b / j z X / j t s 1 B W l a t e x i t > e u dq < l a t e x i t s h a 1 _ b a s e 6 4 = " X B V q M X U p D 9 6 H J x E K x D a s 3 W o f V a 0 = " > A A A B 7 3 i c b V B N S 8 N A E J 3 U r 1 q / q h 6 9 B I v g q S R V 0 G P R i 8 c K 9 g P a W D a b S b t 0 s 0 l 3 N 0 I J / R N e P C j i 1 b / j z X / j t s r 1 q / q h 6 9 B I v g q e x W Q Y 9 F L x 4 r 2 A 9 p 1 5 L N z r a h S X Z N s k J Z + i u 8 e F D E q z / H m / / G t N 2 D t j 4 Y e L w 3 w 8 y 8 I O F M G 9 f 9 d g o r q 2 v r G 8 X N 0 t b 2 z u 5 e e f + g p e N U U W j S m M e q E x A < l a t e x i t s h a 1 _ b a s e 6 4 = " b u A 6 w V j a w 2 q m a I n M w y 7 q t f x D y m U = " > where, For the case of AIC-PLL, two more terms are included in f(x, u) which are f 19,1 (x, u) = K Rvi θ PLL and f 20,1 (x, u) = K Lvi θ PLL .
4 M 0 p n B f n 3 f l Y t K 4 5 5 c w x + A P n 8 w e 8 J 5 T k < / l a t e x i t > t e x i t s h a 1 _ b a s e 6 4 = " l w a 4 b D 9 8 f A 7 q p 1 r B O D S g b e e Z n H Y

Figure 3 .
Figure 3. Block diagram of the impedance-conditioned PLL.
t e x i t s h a 1 _ b a s e 6 4 = " B 5 M M N t 6 v / x t P L m 8 B I 1 M M e 3 x V G y M = " > A A A B + 3 i c b V D L S s N A F J 3 4 r P U V 6 9 L N Y B F c l a Q K u i y 6 c V n B P q A J Y T K d t E P n E W Y m Y g n 5 F T c u F H H r j 7 j z b 5 y 2 W W j r g Q u H c + 7 l 3 n v i l F F t P O / b W V v f 2 N z a r u x U d / f 2 D w 7 d o 1 p X y 0 x h 0 s G S S d W P k S a M C t I x 1 D D S T x V B P G a k F 0 9 u Z 3 7 v k S h N p X g w 0 5 S E H I 0 E T S h G x k q R W w s S h X A e S E 5 G K I q L X B e R W / c a 3 h x w l f g l q Y M S 7 c j 9 C o Y S Z 5 w I g x n S e u B 7 q Q 4 M 0 p n B f n 3 f l Y t K 4 5 5 c w x + A P n 8 w e 8 J 5 T k < / l a t e x i t > t e x i t s h a 1 _ b a s e 6 4 = " l w a 4 b D 9 8 f A 7 q p 1 r B O D S g b e e Z n H Y r e x t L y y u r Z e 2 C h u b m 3 v 7 J p 7 + 0 0 Z p w K T B o 5 Z L N o + S M I o J w 1 F F S P t R B C I f E Z a / u B 6 U m 8 N i Z A 0 5 n d q l B A 3 g h 6 n I c W g t O W Z R y C w A l 7 u h g J w l t 4 P v e w h H I 9 n F G g 6 9 c y S X b G n s h b B y a G E c t U 9 8 6 s b x

Figure 7 .
Figure 7. Steady-state power transfer stability limits of VSC-HVDC system for different types of PLL.

Figure 8 .
Figure 8. Time-domain response of the active power for different types of PLLs for step change in Z g = 1 → 1.1 p.u. and for ω FL,PLL = 400 rad/s (inverter operation).

Figure 9 .
Figure 9. Time-domain response of the active power for different types of PLLs for step change in active power and for ω FL,PLL = 400 rad/s, Z g = 1.1 p.u. (inverter operation).

Figure 10 .
Figure 10.Time-domain response of the θ PLL for different types of PLLs for step change in Z g = 1 → 1.1 p.u. and for ω FL,PLL = 400 rad/s (inverter operation).The experiment is reconducted for the different step change where the value of the grid impedance change is Z g = 1.7 → 2 p.u., and the results are provided in Figures 11-13. .

Figure 11 .
Figure 11.Time-domain response of the active power for different types of PLLs for step change in Z g = 1.7 → 2 p.u. and for ω FL,PLL = 400 rad/s (inverter operation).

Figure 12 .
Figure 12.Time-domain response of the active power for different types of PLLs for step change in active power and for ω FL,PLL = 400 rad/s, Z g = 2 p.u. (inverter operation).

Figure 13 .
Figure 13.Time-domain response of the θ PLL for different types of PLLs for step change in Z g = 1.7 → 2 p.u. and for ω FL,PLL = 400 rad/s (inverter operation).
and 18 for the inverter operation and Figures 15, 17 and 19 for the rectifier operation.

Figure 14 .
Figure 14.SSE for the active power tracking for the IC-PLL-and AIC-PLL-based system for half value of the maximum power (inverter operation).

Figure 15 .
Figure 15.SSE for the active power tracking for the IC-PLL-and AIC-PLL-based system for half value of the maximum power (rectifier operation).

Figure 16 .
Figure 16.SSE for the active power tracking for the IC-PLL-and AIC-PLL-based system for the maximum power (inverter operation).

Figure 17 .
Figure 17.SSE for the active power tracking for the IC-PLL-and AIC-PLL-based system for the maximum power (rectifier operation).

Figures 18 and 19
Figures 18 and 19 represent the results of the value of SSE for both types of PLLs-based converters when the value of the grid impedance is changing for the inverter and rectifier operations, respectively.Thevaluesofthesechangesare ∆Z g = [0.5 0.5 0.3 0.3 0.3 0.3 0.25 0.25 0.2 0.2]•Z g , where Z g = [0.20.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2] p.u.The value of the relative errors are also presented as a line graph in order to show the difference between the SSE values of the IC-PLL and AIC-PLL for the range of the grid impedance.

Figure 18 .
Figure 18.SSE for the active power tracking for the IC-PLL-and AIC-PLL-based system for different change in the values of the grid impedance (inverter operation).

Figure 19 .
Figure 19.SSE for the active power tracking for the IC-PLL-and AIC-PLL-based system for different change in the values of the grid impedance (rectifier operation).

Figure 20 .
Figure 20.Loci of the closed-loop system poles for the range of ω FL,PLL = 50 → 2000 rad/s. ,

Figure 21 .
Figure 21.Time domain response of the active power for AIC-PLL for step change in Z g = 1.7 → 2 p.u. and for different values of the ω FL,PLL .

Figure 22 .
Figure 22.Time domain response of the θ PLL for AIC-PLL for step change in Z g = 1.7 → 2 p.u. and for different values of the ω FL,PLL .
8 5 h D 9 g f P 5 A w 8 m k J M = < / l a t e x i t > e i gdq < l a t e x i t s h a 1 _ b a s e 6 4 = " M f V / J E w / v 0 g C d g E k m I q B V 0 w h 7 q w = " >A A A B 8 H i c b V B N S w M x E J 2 t X 7 V + V T 1 6 C R b B U 9 m t g h 6 L X j x W s B / S r i W b z b a h S X Z N s k J Z + i u 8 e F D E q z / H m / / G t N2 D t j 4 Y e L w 3 w 8 y 8 I O F M G 9 f 9 d g o r q 2 v r G 8 X N 0 t b 2 z u 5 e e f + g p e N U E d o k M Y 9 V J 8 C a c i Z p 0 z D D a S d R F I u A 0 3 Y w u p 7 6 7 S e q N I v l n R k n 1 B d 4 I F n E C D Z W u n + g r J 8 N w s d J v 1 x x q + 4 M a J l 4 O a l A j k a / / N U L Y 5 I K K g 3 h W O u u 5 y b G z 7 A y j H A 6 K f V S T R N M R n h A u 5 Z K L K j 2 s 9 n B E 3 R i l R B F s b I l D Z q p v y c y L L Q e i 8 B 2 C m y G e t G b i v 9 5 3 d R E l 3 7 G Z J I a K s l 8 U Z R y Z G I 0 / R 6 F T F F i + N g S T B S z t y I y x A o T Y z M q 2 R C 8 x Z e X S a t W 9 c 6 q t d v z S v 0 q j 6 M I R 3 A M p + D B B d T h B h r Q B A I C n u E V 3 h z l v D j v z s e 8 t e D k M 4 f w B 8 7 n D x V C k J c = < / l a t e x i t > 1 B W x 8 M P N 6 b Y W a e n 3 C m t O N 8 W 4 W 1 9 Y 3 N r e J 2 a W d 3 b /+ g f H j U U n E q K T Z p z G P Z 8 Y l C z g Q 2 N d M c O 4 l E E v k c 2 / 7 o d u a 3 n 1 A q F o s H P U n Q i 8 h A s J B R o o 3 U e c S 0 n w X j a b 9 c c a r O H P Y q c X N S g R y N f v m r F 8 Q 0 j V B o y o l S X d d J t J c R q R n l O C 3 1 U o U J o S M y w K 6 h g k S o v G x + 7 9 Q + M 0 p g h 7 E 0 J b Q 9 V 3 9 P Z C R S a h L 5 p j M i e q i W v Z n 4 n 9 d N d X j t Z U w k q U Z B F 4 v C l N s 6 t m f P 2 w G T S D W f G E K o Z O Z W m w 6 J J F S b i E o m B H f 5 5 V X S q l X d i 2 r t /r J S v 8 n j K M I J n M I 5 u H A F d b i D B j S B A o d n e I U 3 a 2 y 9 W O / W x 6 K 1 Y O U z x / A H 1 u c P Y 1 a Q M g = = < / l a t e x i t > ✓ P LL e i cdq < l a t e x i t s h a 1 _ b a s e 6 4 = " R Z L 0 n y I 4 Q e s 0 G b 8 5 h D 9 g f P 5 A w 8 m k J M = < / l a t e x i t > c u dq < l a t e x i t s h a 1 _ b a s e 6 4 = " P Q 9 P 9 D X h s l s 9 i g O f 5 7 E i o h h 5 R o g = " > A A A B 7 3 i c b V B N S w M x E J 3 U r 1 q / q h 6 9 B I v g q e x W Q Y 9 F L x 4 r 2 A 9 o 1 5 L N Z t v Q b H a b Z I W y 9 E 9 4 8 a C I V / + O N / + N a b s H b X 0 w 8 H h v h p l 5 f i K 4 N o 7 z j Q p r 6 x u b W 8 X t 0 s 7 u 3 v 5 B + f C o p e N U U d a k s Y h V x y e a C S 5 Z 0 3 A j W C d R j E S + Y G 1 / d D v z 2 0 9 M a R 7 L B z N J m B e R g e Q h p 8 R Y q f N I 0 3 4 W j K f 9 c s W p O n P g V e L m p A I 5 G v 3 y V y + I a R o x a a g g W n d d J z F e R p T h V L B p q Z d q l h A 6 I g P W t V S S i G k v m 9 8 7 x W d W C X A Y K 1 v S 4 L n 6 e y I j k d a T y L e d E T F D v e z N x P + 8 b m r C a y / j M k k N k 3 S x K E w F N j G e P Y 8 D r h g 1 Y m I J o Y r b W z E d E k W o s R G V b A j u 8 s u r p F W r u h f V 2 v 1 l p X 6 T x 1 G E E z i F c 3 D h C u p w B w 1 o A g U B z / A K b 2 i M X t A 7 + l i 0 F l A + c w x / g D 5 / A G B C k D A = < / l a t e x i t > a l c u y x W b r I 4 c n A M J 3 A G H l x B B e 6 g C n V g 0 I d n e I U 3 R z o v z r v z M W 9 d c b K Z I / g D 5 / M H x W S N d Q = = < / l a t e x i t > PLL Model e i gdq < l a t e x i t s h a 1 _ b a s e 6 4 = " M f V / J E w / v 0 g C d g E k m I q B V 0 w h 7 q w = " > A A A B 8 H i c b V B N S w M x E J 2 t X 7 V + V T 1 6 C R b B U 9 m t g h 6 L X j x W s B / S r i W b z b a h S X Z N s k J Z + i u 8 e F D E q z / H m / / G t N 2 D t j 4 Y e L w 3 w 8 y 8 I O F M G 9 f 9 d g o r q 2 v r G 8 X N 0 t b 2 z u 5 e e f + g p e N U E d o k M Y 9 V J 8 C a c i Z p 0 z D D a S d R F I u A 0 3 Y w u p 7 6 7 S e q NI v l n R k n 1 B d 4 I F n E C D Z W u n + g r J 8 N w s d J v 1 x x q + 4 M a J l 4 O a l A j k a / / N U L Y 5 I K K g 3 h W O u u 5 y b G z 7 A y j H A 6 K f V S T R N M R n h A u 5 Z K L K j 2 s 9 n B E 3 R i l R B Fs b I l D Z q p v y c y L L Q e i 8 B 2 C m y G e t G b i v 9 5 3 d R E l 3 7 G Z J I a K s l 8 U Z R y Z G I 0 / R 6 F T F F i + N g S T B S z t y I y x A o T Y z M q 2 R C 8 x Z e X S a t W 9 c 6 q t d v z S v 0 q j 6 M I R 3 A M p + D B B d T h B h r Q B A I C n u E V 3 h z l v D j v z s e 8 t e D k M 4 f w B 8 7 n D x V C k J c = < / l a t e x i t > c i gdq < l a t e x i t s h a 1 _ b a s e 6 4 = " E u G H K K 3 N + O 1 S i o S o x + / p c / c P / M I = " > A A A B 8 H i c b V B N S w M x E J 2 t X 7 V + V T 1 6 C R b B U 9 m t g h 6 L X j x W s B / S r i W b z b a h S X Z N s k J Z + i u 8 e F D E q z / H m / / G t N 2 D t j 4 Y e L w 3 w 8 y 8 I O F M G 9 f 9 d g o r q 2 v r G 8 X N 0 t b 2 z u 5 e e f + g p e N U E d o k M Y 9 V J 8 C a c i Z p 0 z D D a S d R F I u A 0 3 Y w u p 7 6 7 S e q N I v l n R k n 1 B d 4 I F n E C D Z W u n 8 g r J 8 N w s d J v 1 x x q + 4 M a J l 4 O a l A j k a / / N U L Y 5 I K K g 3 h W O u u 5 y b G z 7 A y j H A 6 K f V S T R N M R n h A u 5 Z K L K j 2 s 9 n B E 3 R i l R B F s b I l D Z q p v y c y L L Q e i 8 B 2 C m y G e t G b i v 9 5 3 d R E l 3 7 G Z J I a K s l 8 U Z R y Z G I 0 / R 6 F T F F i + N g S T B S z t y I y x A o T Y z M q 2 R C 8 x Z e X S a t W 9 c 6 q t d v z S v 0 q j 6 M I R 3 A M p + D B B d T h B h r Q B A I C n u E V 3 h z l v D j v z s e 8 t e D k M 4 f w B 8 7 n D x I s k J U = < / l a t e x i t >

•
The inner loop represents the linearised version of the conventional SRF-PLL, in which the transfer function H PLL (s) H FL,PLL (s) • H C (s), where H FL,PLL (s) and H C (s) are the transfer functions of the PLL low pass filter and PLL compensator, respectively, depicts the virtual impedance part, where Lv = θ PLL • H L (s) and Rv 1 a 1,2 − K AD

Table A1 .
Participation matrix for the AIC-PLL.