Discontinuous Current Mode Modeling and Zero Current Switching of Flyback Converter

: The ﬂyback converters are widely used in low power applications. The switch typically requires 600 V breakdown voltage in order to perform large step-down voltage. Thus, slight variation on the switch control can either permanently damage the switch or decrease the efﬁciency of the power conversion. In order to achieve higher power efﬁciency, the previous literature suggested operating the ﬂyback converter in the discontinuous current mode (DCM). It is then required to understand the critical conditions of the DCM through analyzing the dynamic behavior and discontinuous current mechanism. This paper started from the current waveform analyses, proceeded to the derivation of zero current switching (ZCS) formulation, and ﬁnally reached the necessary conditions for the DCM. The entire DCM operation was divided into three phases that subsequently affect the result of the zero voltage switching (ZVS) and then to the ZCS. The experiment shows a power efﬁciency of over 96% when the output power is around 65 W. The switch used in this paper is a Gallium Nitride High-Electron-Mobility Transistor (GaN HEMT) that is advantageous at the high breakdown voltage up to 800 V. The important ﬁndings from the experiments include that the output power increases with the increasing input DC voltage and the duty cycle is rather linearly decreasing with the increasing switching frequency when both the zero voltage switching (ZVS) and ZCS conditions are satisﬁed simultaneously.


Introduction
The rapid advancement of electric vehicles [1][2][3], military technology [4], grid technology [5,6] and factory automation [7] have led to an increased demand for the dc-dc converter. Isolated converters are required, where isolation is needed between the input and output side. Flyback converters are widely used topology for low power and large step-down voltage applications. During the transfer of energy from the input to the output side, an intermediate flyback transformer is used. The transformer is designed such that the primary windings turns of the transformer are higher compared to the secondary winding turns for large step-down voltage applications.
The converter usually operates in two modes based on the output load. In continuous conduction mode (CCM), the transformer is unable to transfer the complete energy since the part of energy always remains in the core. In this mode, the semiconductor switch is stressed at a higher voltage [8][9][10]. In addition, it leads to hard switching operation, which decreases the conversion efficiency. In [11][12][13][14][15], an active clamp-based flyback converter is discussed to reduce the voltage stress on the switch. However, using the additional switch requires an additional gate driver circuit. Apart from that, this topology increases the current stress on the switch. That can considerably affect the switch lifetime especially if the Gallium Nitride High Electron Mobility Transistor (GaN HEMT) based power switch is used [16][17][18][19][20]. In terms of output voltage control of the converter, the bandwidth is limited by the right half-plane zero location. Considering these limitations in the CCM operation, the converter is preferred to operate in the discontinuous conduction mode (DCM). However, this mode of operation brings other challenges for the circuit designer, such as larger filter requirements at the input and output side [21][22][23][24], and increased electromagnetic interference [25,26]. The detailed comparison between both operations is discussed in [27,28]. In the DCM operation, the transformer is able to transfer the complete energy to the output side. In other words, the transformer secondary winding current becomes zero. However, due to the presence of leakage inductance and output capacitance of the switch, results in the voltage oscillation which is because of the resonance effect that is discussed in [29]. Few studies have presented some methods using divided resonant capacitor [30], the secondary-side resonant method [31], and dynamic resonant period control [32], for mitigating voltage spike and increasing power conversion efficiency to improve the traditional methods, such as RCD clamp circuit, or active clamp circuit. In [30], the design methodology for a flyback converter with divided resonant capacitor is analyzed by considering leakage and load variations, which is discussed to reduce the voltage spikes and improve the efficiency of the switch. This method further improves the overall conversion efficiency of the converter. In [31], a secondary-side resonant method is proposed using equivalent circuit analysis model to improve synchronous rectifier operation and reduce primary RMS current. In [32], a dynamic resonant period control for zero voltage switching is proposed, which can adjust the ON-time in auxiliary switch to reduce leakage energy loss and prevent large voltage stress on the component, while the efficiency of the converter is further improved by achieving the zero voltage during the switching ON of the switch. The designed methodology for the ZVS operation is discussed in [33,34]. According to these studies, taking equivalent circuit analysis model and design methodology as consideration for achieving ZVS and ZCS operation are important issue to reach the superior performance. The quasi-resonant flyback converter in [31][32][33][34] use multiple switches to activate the voltage oscillation on the secondary side. The quasi-resonant flyback converter in [30] is equipped with a resonance capacitance on the secondary side. The quasi-resonant flyback converter in [35] controls the duty calculated every switching period. Their methods are practical with additional sensors required. Our paper derives the originality of the DCM resonance due to the interaction between the output voltage and the output current with simple duty control and without additional transistor switch and sensor feedback. Our method is not quite in the domain of quasi-resonant flyback converters. We are looking for the low switching loss method which yields a high efficiency in the DCM operation for a conventional flyback converter in high switching frequency using GaN HEMT. Our method is simply achieved by having ZVS with ZCS occurred simultaneously in the instance of switching. The quasi-resonant flyback converter achieved only ZCS and not the ZVS.
To date, quite several flyback controllers are available in the market. In addition to the conventional single working-mode controller, some multiple working-mode controllers, such as UCC 28600 [36] and XDPS21071 [37] for Secondary-Side-Regulated (SSR), and LM 5180 for Primary-Side-Regulated (PSR) [38], have also been developed for improving the conversion efficiency of the flyback throughout the entire load [39,40]. It was commonly agreed that the flyback converter with low output current is suitable for discontinuous current mode (DCM) operation and continuous current mode (CCM) operation is suitable for large output current. In general, the DCM operation yields better power conversion efficiency. On the other hand, the DCM can cause larger voltage peak, which may damage the switch. The suitable operation modes depending on the application and the switch used. Take XDPS21071 [37] for example, it operates in a guaranteed DCM mode under all conditions. To maximize efficiency at light and medium loads, XDPS21071 also implemented frequency reduction mode and burst mode. For USB PD applications, CCM operation under fixed-frequency control makes EMI and system design relatively simple. Moreover, several of the previous literature present more complete analysis with the parasitic components including transformer parasitic capacitance, leakage inductance or the diode parasitic capacitance [41][42][43][44][45] in flyback converter to show the good agreement between simulation and measurement results.
This paper aims to provide an insight of the DCM mechanism and zero current switching approach without basing on the trial and error method and intend to utilize the theories to reduce the number of experiments, which are organized as follows. In Section 2, the detailed operation of the flyback converter is discussed in the ZCS. During the discussion, a template of the key waveforms is used in the OFF period of the switch. The template waveform is divided into three intervals based on the (1) drain to source voltage rising period, (2) current conduction period in the secondary winding and (3) zero current conduction period in the secondary winding. In these intervals, governing equations of the converters are derived, and the key parameters are calculated. In Section 3, a SPICE simulation analysis method is carried out. Based on the SPICE analysis, the critical conditions for the DCM operation, including the conditions of large resistor load and small duty cycle, can be verified. Afterward, experimental results are presented, and the comparison with SPICE analysis is provided in Section 4. The conclusion of this work is discussed in Section 5.

Materials and Methods
The transistor used in this paper is cascode power module derived from D-mode GaN HEMT described in [46], shown in Figure 1. An N-type metal oxide semiconductor (NMOS) in series with the D-mode GaN HEMT is connected to achieve the module operation similar to the enhancement mode. The NMOS is always remained on during regular operation. The GaN HEMT is then switched on and off by using a charge pump-based circuit and a conventional gate driver. Since the GaN HEMT is driven independently, the highly negative gate to source voltage surge during turn off is avoided, and in addition, high switching frequency operation is made possible. The parameter of GaN device is analyzed using a Keysight B1500A. The turn-on voltage (v GS ,on) for the D-mode GaN HEMT is −7 V, the drain-source parasitic capacitance (C DS ) is 30 pF. The breakdown voltage of the GaN HEMT is 800 V and the maximum current is 35 A. under all conditions. To maximize efficiency at light and medium loads, XDPS21071 also implemented frequency reduction mode and burst mode. For USB PD applications, CCM operation under fixed-frequency control makes EMI and system design relatively simple. Moreover, several of the previous literature present more complete analysis with the parasitic components including transformer parasitic capacitance, leakage inductance or the diode parasitic capacitance [41][42][43][44][45] in flyback converter to show the good agreement between simulation and measurement results. This paper aims to provide an insight of the DCM mechanism and zero current switching approach without basing on the trial and error method and intend to utilize the theories to reduce the number of experiments, which are organized as follows. In Section 2, the detailed operation of the flyback converter is discussed in the ZCS. During the discussion, a template of the key waveforms is used in the OFF period of the switch. The template waveform is divided into three intervals based on the (1) drain to source voltage rising period, (2) current conduction period in the secondary winding and (3) zero current conduction period in the secondary winding. In these intervals, governing equations of the converters are derived, and the key parameters are calculated. In Section 3, a SPICE simulation analysis method is carried out. Based on the SPICE analysis, the critical conditions for the DCM operation, including the conditions of large resistor load and small duty cycle, can be verified. Afterward, experimental results are presented, and the comparison with SPICE analysis is provided in Section 4. The conclusion of this work is discussed in Section 5.

Materials and Methods
The transistor used in this paper is cascode power module derived from D-mode GaN HEMT described in [46], shown in Figure 1. An N-type metal oxide semiconductor (NMOS) in series with the D-mode GaN HEMT is connected to achieve the module operation similar to the enhancement mode. The NMOS is always remained on during regular operation. The GaN HEMT is then switched on and off by using a charge pump-based circuit and a conventional gate driver. Since the GaN HEMT is driven independently, the highly negative gate to source voltage surge during turn off is avoided, and in addition, high switching frequency operation is made possible. The parameter of GaN device is analyzed using a Keysight B1500A. The turn-on voltage (vGS,on) for the D-mode GaN HEMT is −7 V, the drain-source parasitic capacitance (CDS) is 30 pF. The breakdown voltage of the GaN HEMT is 800 V and the maximum current is 35 A.   1000 V diode which is not a fast recovery diode. The output capacitor (C O ) is large enough that allows the output voltage to be assumed constant during analyses. Figure 2 depicts an equivalent circuit of the flyback converter. There are two diodes, the rectifier diode (DS)and the snubber diode (DB), used in the circuit. The rectifier diode is a fast recovery diode (FRD) and the snubber diode is a high breakdown voltage up to 1000 V diode which is not a fast recovery diode. The output capacitor (CO) is large enough that allows the output voltage to be assumed constant during analyses.

Transformer
The equivalent circuit of the transformer is modified from the Steinmetz equivalent circuit as shown in Figure 3. Assuming that RP and RS are very small and Rcore is very large, the power loss due to them are ignored from the analysis. The overall inductance on the primary side is LP which can be divided into two parts, namely the magnetization inductance LPm and the leakage inductance LPl, in terms of the coupling coefficient. The individual inductances are defined as follows.

Transformer
The equivalent circuit of the transformer is modified from the Steinmetz equivalent circuit as shown in Figure 3. Assuming that R P and R S are very small and R core is very large, the power loss due to them are ignored from the analysis. The overall inductance on the primary side is L P which can be divided into two parts, namely the magnetization inductance L Pm and the leakage inductance L Pl , in terms of the coupling coefficient. The individual inductances are defined as follows.
and Figure 2 depicts an equivalent circuit of the flyback converter. There are two diodes, the rectifier diode (DS)and the snubber diode (DB), used in the circuit. The rectifier diode is a fast recovery diode (FRD) and the snubber diode is a high breakdown voltage up to 1000 V diode which is not a fast recovery diode. The output capacitor (CO) is large enough that allows the output voltage to be assumed constant during analyses.

Transformer
The equivalent circuit of the transformer is modified from the Steinmetz equivalent circuit as shown in Figure 3. Assuming that RP and RS are very small and Rcore is very large, the power loss due to them are ignored from the analysis. The overall inductance on the primary side is LP which can be divided into two parts, namely the magnetization inductance LPm and the leakage inductance LPl, in terms of the coupling coefficient. The individual inductances are defined as follows.  Since the flyback converter uses windings in opposite dot-orientation as a convention, we thus define the current as follows.

of 23
In the flyback converter arrangement, i Pi is a non-negative value, i.e., i Pi ≥ 0, since i S ≥ 0 for the secondary winding outputs to a diode D S in series. The voltage on the primary winding is written as: The voltage on the mutual inductance is exerted by the magnetization current.
Thus, Equation (4) is then simplified into: The turn ratio a is defined as follows.
The leakage inductances can be measured from the short circuit test in order to distinguish it from the overall inductance. The coupling coefficient is estimated as follows.
The parameters of the transformer in this paper, measured from the open and short circuit test [47] using the RLC meter GWINSTEK LCR819, are listed in Table 1.

Wave Form Assumptions
The wave forms for the v DS , i S and i P are as shown in Figure 4. The wave forms are obtained empirically from the experiments, which yield good efficiencies from the input and output power relations.
During the switch turn-on time, the inductor current rises in a ramp-up function which correlates with the inductance L P and input voltage V DD as follows.
During the switch turn-off time, the output current i S is in a sinusoidal alike rampdown function. The peak of the ramp function is denoted by i S,max . The current flows to the capacitor C O within a time period called the continuous current mode time t CCM . During the switch turn-off time, the output current iS is in a sinusoidal alike rampdown function. The peak of the ramp function is denoted by iS,max. The current flows to the capacitor CO within a time period called the continuous current mode time tCCM.
There are three phases during the turn-off process of the switch, which are (1) the drain-source voltage rising phase, (2) the current flowing on the secondary winding phase, and, (3) the zero current in the secondary winding phase.

Steady State Assumptions
We had applied two assumptions in the steady state of the flyback converter as follows.
(1) The ratio of the peak value of currents is: where  denotes the transformer peak current attenuation. It shall be noted that the attenuation does not imply the energy loss; however, it has the effect to the current flowing time on the secondary winding.
(2) Current flows in the secondary winding only during the diode conduction time which is referred to as the continuous current time tCC. This assumption can be written into two equations separately as follows.
Substituting Equation (12) into (10), we obtain:  There are three phases during the turn-off process of the switch, which are (1) the drain-source voltage rising phase, (2) the current flowing on the secondary winding phase, and, (3) the zero current in the secondary winding phase.

Steady State Assumptions
We had applied two assumptions in the steady state of the flyback converter as follows.
(1) The ratio of the peak value of currents is: where ζ denotes the transformer peak current attenuation. It shall be noted that the attenuation does not imply the energy loss; however, it has the effect to the current flowing time on the secondary winding. (2) Current flows in the secondary winding only during the diode conduction time which is referred to as the continuous current time t CC . This assumption can be written into two equations separately as follows.
The voltage gain is then written as follows.
The transformer peak current attenuation ζ, which may also be deemed as the power efficiency, may be evaluated from the experiment as follows.
The experimental examples are as shown in Table 2. The necessary condition for the ZVS is aV O /V DD ≥ 1. Referring to Figure 4, the drain-source voltage v DS will have a steady state value at V DD when the current on both the primary i P and the secondary winding i S are zero, the only current flowing to the switch is the current from the snubber. The drain-source voltage v DS will drop from V DD + aV O to V DD . Assuming the damping of the voltage oscillation is small, the minimum voltage of v DS is V DD − aV O which must be a non-positive voltage. At the time when v DS = 0, the switch turns on again that is known as the ZVS.

Drain-Source Voltage Rising Phase
In the drain-source voltage rising phase we have assumed that the current on the secondary winding is zero. The equivalent circuit is as shown in Figure 5. During this phase, the diode transits from its reverse bias state to the forward bias state. The junction capacitor C j0 must be refilled with the reverse recovery charge Q rr . The drain-source capacitor C DS needs also also need the reverse recovery charge on the way to turn the switch off.
The KVL equation yields that: where:  The KVL equation yields that: Where: The current flowing in the snubber is written as follows.
The KCL equation can be stated as follows.
From Equation (19), we obtain the following equation.
( ) Substituting (21) by neglecting the term diB/dt in Equation (23), we have: It is then written in the standard form of the 2nd order system equation as follows.
where the resonant frequency is: The rising time is assumed one tenth of the oscillation period time, which is approximately 36 degree phase forward. The current flowing in the snubber is written as follows.
The KCL equation can be stated as follows.
From Equation (19), we obtain the following equation.
Substituting (21) by neglecting the term di B /dt in Equation (23), we have: It is then written in the standard form of the 2nd order system equation as follows.
where the resonant frequency is: The rising time is assumed one tenth of the oscillation period time, which is approximately 36 degree phase forward.
The nominal values of the parameters and the calculation result is shown in Table 3.
Measurement (Element) 10 pF Equation (26)  Referred to Figure 6, the output diode D S start conducting as the −v P ≥ av O . The transformer is transforming the voltage from the secondary winding back to the primary winding providing the equivalence L Sm = L Pm /a 2 and i Sm = a i Pm . It is important to note that the snubber diode is not a fast recovery diode, which will allow the reverse current through. Then the following equations are derived assuming that C B > 10 C DS and the core loss is neglected, which results in i B > 10 i D . In addition, L Pm >> L Pl is assumed during the derivation and the voltage drop on the leakage inductor is ignored. From Equation (3), we obtain that: In addition: The nominal values of the parameters and the calculation result is shown in Table 3. Referred to Figure 6, the output diode DS start conducting as the −vP ≥ avO. The transformer is transforming the voltage from the secondary winding back to the primary winding providing the equivalence LSm = LPm/a 2 and iSm = a iPm. It is important to note that the snubber diode is not a fast recovery diode, which will allow the reverse current through. Then the following equations are derived assuming that CB > 10 CDS and the core loss is neglected, which results in iB > 10 iD. In addition, LPm >> LPl is assumed during the derivation and the voltage drop on the leakage inductor is ignored. From Equation (3), we obtain that: In addition: On the secondary winding side, the current is: Substituting the above equation into Equation (28)   On the secondary winding side, the current is: Substituting the above equation into Equation (28) then into (29), we have: Knowing that di Sm /dt = v Si /L Sm = a v P /L Pm , we substitute Equation (30) into the Equation (31) to obtain that: Taking time derivative to the above equation, we have: Considering the L Pm >> a 2 L Sl , the above equation can be written into a standard form of a 2nd order differential equation as follows.
In the above equation, the natural frequency and the damping ratio are as follows.
It is worth to note that the damping ratio derived in the above equation is in the form for quality factor of the current amplification. That is to say the transformer is activating in this phase; the current on the primary winding will affect the current on the seconding winding. The nominal values of the parameters and the calculation results are shown in Table 4. Equation (34) is valid when the current i P on the primary winding becomes negative until the current i P becomes positive. At the time when the current i P is zero, there is no more magnetization required on the secondary winding and Equation (30) will be revised into as follows. Thus, the current i S will immediately change from decreasing function into an increasing function as shown in Figure 7. Shortly when the current i P on the primary winding becomes negative again after time t d , Equation (34) is once again activated. The frequency of the current derived from the parameters of the transformer and the snubber, as shown in Table 4, indicates that the minimum time to complete the current hurdle is 2 µs. Thus, the maximum switching frequency f S in the current arrangement shall be less than 500 kHz when the duty ratio is 50%.

Zero Current in the Secondary Winding Phase and Zero Current Switching
As stated in the previous section that the necessary condition for the zero-voltage switching is aVO/VDD ≥ 1. The snubber diode DB simultaneously turns off when no current is flowing in in the secondary winding as shown in Figure 8. In this zero current in the

Zero Current in the Secondary Winding Phase and Zero Current Switching
As stated in the previous section that the necessary condition for the zero-voltage switching is aV O /V DD ≥ 1. The snubber diode D B simultaneously turns off when no current is flowing in in the secondary winding as shown in Figure 8. In this zero current in the secondary winding phase, assuming that i B is negligibly small, the steady state voltage for v DS is supposed V DD when the initial value of v DS is V DD + aV O .

Zero Current in the Secondary Winding Phase and Zero Current Switching
As stated in the previous section that the necessary condition for the zero-voltage switching is aVO/VDD ≥ 1. The snubber diode DB simultaneously turns off when no current is flowing in in the secondary winding as shown in Figure 8. In this zero current in the secondary winding phase, assuming that iB is negligibly small, the steady state voltage for vDS is supposed VDD when the initial value of vDS is VDD + aVO.
The KVL equation yields that: Assuming that iB is negligibly small compared with diB/dt, Equation (21)   The capacitor C oss withdraws the charge in according to the equation as follows.
The KVL equation yields that: Assuming that i B is negligibly small compared with di B /dt, Equation (21) yields that: We can reformulate Equation (39) as follows.
The resonant frequency is: The switch turns off when the first derivative of v DS becomes zero is called ZCS. According to Equation (41), the time required to complete the half time period of resonance is defined as t Z which can be expressed as follows.
We shall note that the damping ratio of Equation (43) is in a form of voltage amplification of resonance. The nominal values of the parameters and the calculation result is as shown in Table 5. As stated previously, the zero-voltage switching and further ZVS can be successful only when we have a larger turn ratio a subjected to the same voltage output V O . Thus, the transformer design is a critical issue to the flyback converter in order to achieve a high-power conversion efficiency. Table 5. Parameters used to estimate the rising time.

Symbol
Original Value Unit Equation (

Analysis
The analyses were used as tools to bridge the differences between the experiment and the derivations with assumptions. The first analysis is the SPICE analysis. The circuit parameters shown in the SPICE analysis are identical to those used in the experiment except the switch transistor, the input DC voltage V DD , the switching frequency, the duty cycle and the load resistor. The second analysis based on the SPICE analysis is applied to verify the critical conditions for the DCM. The DCM operation is valid when the load resistor is large and the duty cycle of the switching is small. The corresponding analyses were also compared with the experiments. The satisfactory consistency allowed the designer to use the equations for verification of the DCM existence in different flyback converter designs.

SPICE Simulation Analysis
The flyback converter is simulated using the OrCAD, and the schematic diagram of the circuit is shown in Figure 9. During the simulation, parameters are considered the same as used for the above analysis. However, parasitic inductances are added at the input power supply (L in,par ) and switch (L M1,par ) to mimic their non-ideality due to the connecting wire and the lead of the switch, respectively. A voltage source is connected in series with the output capacitance to reduce the simulation time for achieving the steady-state. The steady-state waveform of the circuit is shown in Figure 10. The waveforms represent the gate voltage (v G ), switch voltage (v DS ), output diode current (i S ) and output voltage (V O ) with their respective colors, as shown in the schematic. It is observed that the i S becomes zero within the (1 − δ)T interval, which leads to ZCS of the switch. The capacitor C o is provided with the initial condition (IC) of 56.3 VDC as the steady state output voltage and the SPICE simulation runs for only 1ms. We added a parasitic capacitance 50 pF to the primary winding of the transformer to increase the reality. The flyback converter result is for the purpose of comparing the analysis with the experiment and theoretical data using the identical circuit parameters, therefore it satisfies neither ZVS nor ZCS condition. state. The steady-state waveform of the circuit is shown in Figure 10. The waveforms represent the gate voltage (vG), switch voltage (vDS), output diode current (iS) and output voltage (VO) with their respective colors, as shown in the schematic. It is observed that the iS becomes zero within the (1 −δ)T interval, which leads to ZCS of the switch. The capacitor Co is provided with the initial condition (IC) of 56.3 VDC as the steady state output voltage and the SPICE simulation runs for only 1ms. We added a parasitic capacitance 50 pF to the primary winding of the transformer to increase the reality. The flyback converter result is for the purpose of comparing the analysis with the experiment and theoretical data using the identical circuit parameters, therefore it satisfies neither ZVS nor ZCS condition.

Critical Condition for DCM
The derivations provided in this section are based on the assumption that the power efficiency is 100%. The output voltage for the CCM is well-known as follows.
According to Equation (9), the maximum current IP,max on the inductor LP can be written in terms of switching frequency fs, duty cycle δ and input DC Voltage VDD as follows.

Critical Condition for DCM
The derivations provided in this section are based on the assumption that the power efficiency is 100%. The output voltage for the CCM is well-known as follows.
According to Equation (9), the maximum current I P,max on the inductor L P can be written in terms of switching frequency f s , duty cycle δ and input DC Voltage V DD as follows.
According to Equation (17) providing the transformer peak current attenuation ζ = 1, the output resistance R O can be written in terms of switching frequency f S , output voltage V O , input DC Voltage V DD , turn ratio a and duty cycle δ as follows.
Substituting Equation (45) into the above equation, we obtain the critical condition for output resistance R O which locates at the border of CCM and DCM as follows.
Substituting Equation (46) into the above equation, we can rewrite the condition for DCM as follows.
According to Equation (45), if the output voltage V O is higher than δ/a(1 − δ)V DD then the output current which reduces the operation will become DCM. Thus, the duty cycle δ should follow also the equation below to achieve the DCM.
The SPICE circuit is operated at different V DD and R O to find out the boundary condition also known as critical condition. During the operation, the V O and f S are maintained constant 20 V and 150 kHz, respectively. The current i S can be observed at different simulations to distinguish the kinds of operations. The simulation results compared to the derivation in equation (50) and experiments are summarized in Figure 11. Afterward, the boundary condition between CCM and DCM operation is determined for the provided V DD and R O . the output current which reduces the operation will become DCM. Thus, the duty cycle δ should follow also the equation below to achieve the DCM.
The SPICE circuit is operated at different VDD and RO to find out the boundary condition also known as critical condition. During the operation, the VO and fS are maintained constant 20 V and 150 kHz, respectively. The current iS can be observed at different simulations to distinguish the kinds of operations. The simulation results compared to the derivation in equation (50) and experiments are summarized in Figure 11. Afterward, the boundary condition between CCM and DCM operation is determined for the provided VDD and RO. Figure 11. Determination of BCM using SPICE which is compared to Equation (50). Figure 11. Determination of BCM using SPICE which is compared to Equation (50).

Results and Comparisons
In order to validate the proposed method, a medium voltage experimental setup is prepared as shown in Figure 12, and waveforms are shown in Figure 13. In the experiment, we used a D-mode GaN HEMT transistor fabricated by Elite advanced laser Co. The gate voltage in light blue color is switching from 0 to −12 V with the charge pump gate drive recommended in [48]. The circuit parameters follow the parameters provided in Tables 1-5. The circuit parameters follow the parameters provided in Tables 1-5. An operating condition (V DD , f S, δ and R O ) is considered (150 V, 150 kHz, 66% and 50 Ohm), respectively. The measured V O is found to be 53.4 V. The power output is 57 W under the efficiency 97.3% power conversion. The waveform matches closely to the theoretical waveform. As stated previously, at the time when the current i P is zero, there is no more magnetization required on the secondary winding and Equation (30) will be revised into Equation (37), the current i S will immediately change from decreasing function into an increasing function as shown in Figure 13. The dynamic waveforms due to the load change and different snubber designs are shown in Figure 14. In order to validate the proposed method, a medium voltage experimental setup is prepared as shown in Figure 12, and waveforms are shown in Figure 13. In the experiment, we used a D-mode GaN HEMT transistor fabricated by Elite advanced laser Co. The gate voltage in light blue color is switching from 0 to −12 V with the charge pump gate drive recommended in [48]. The circuit parameters follow the parameters provided in Tables 1-5. The circuit parameters follow the parameters provided in Tables 1-5. An operating condition (VDD, fS, δ and RO) is considered (150 V, 150 kHz, 66% and 50 Ohm), respectively. The measured VO is found to be 53.4 V. The power output is 57 W under the efficiency 97.3% power conversion. The waveform matches closely to the theoretical waveform. As stated previously, at the time when the current iP is zero, there is no more magnetization required on the secondary winding and Equation (30) will be revised into Equation (37), the current iS will immediately change from decreasing function into an increasing function as shown in Figure 13. The dynamic waveforms due to the load change and different snubber designs are shown in Figure 14.  The other high voltage experimental setup yields waveforms are shown in Figure 15. An operating condition (VDD, fS, δ and RO) is considered (300 V, 280 kHz, 48% and 50 Ohm), respectively. The measured VO is found to be 56.3 V. The detailed key parameters comparison among the theoretical, OrCAD analysis, and experimental results are provided in The other high voltage experimental setup yields waveforms are shown in Figure 15. An operating condition (VDD, fS, δ and RO) is considered (300 V, 280 kHz, 48% and 50 Ohm), respectively. The measured VO is found to be 56.3 V. The detailed key parameters comparison among the theoretical, OrCAD analysis, and experimental results are provided in The other high voltage experimental setup yields waveforms are shown in Figure 15. An operating condition (V DD , f S , δ and R O ) is considered (300 V, 280 kHz, 48% and 50 Ohm), respectively. The measured V O is found to be 56.3 V. The detailed key parameters comparison among the theoretical, OrCAD analysis, and experimental results are provided in Table 6. From Table 6, it is observed that the t CC obtained from the theoretical is higher than both the SPICE analysis and experiment. The reason for the differences due to the oscillation waveform of the i S of the SPICE analysis is somehow different from the other two. The oscillation causes the peak of i S to reach a value higher than ai P,max . Therefore, the time required for the transformer to transfer the same amount of energy to the output side is less. The t r parameter from the theoretical, SPICE analysis and experiment are found to be 150 and 130 ns, respectively. This is because the C DS value during the simulation might be less than that of the experiment. The f 2 frequency obtained from the SPICE is twice higher than the theoretical, whereas the value obtained from the experiment is 1.6 times higher. The t Z parameter obtained from the theoretical, SPICE and experiment are 710, 700 and 530 ns, respectively. The reason for having less t Z time during the experiment because the t CC time is larger. In summary, the theoretical yields values, a bit closer to the experiment than the SPICE does, however the total period of switching time was obtained incorrectly from the theoretical. The switching time period of the experiment is 3.57 µs. It is incorrect when we add up the t CC and t Z in the "theoretical" column of Table 6; the switch turn-off time of the theoretical became 2.2 µs which is supposed 1.86 µs subjected to the duty ratio 48%. On the other hand, the SPICE analysis can yield closer match to the experiments on the timing.  Table 3 130 130 ns Natural frequency of the current resonance in secondary winding 500 in Table 4 1000 800 kHz t Z Zero current time in secondary winding 710 in Table 5 700 530 ns The power efficiency of the result shown in Figure 15 is 96.2% for 65 W output power. The power input is calculated by average the multiplication on the 10,000 samples, from the purple curve in Figure 15a, for 6 to 10 periods of switching as follows.
The power input is calculated by average the multiplication on the 10,000 samples, from the green curve in Figure 15a, for 6 to 10 periods of switching as follows.
The power efficiency is calculated from the equation as follows.
Efficiency (%) = P in /P out × 100% Even though we demonstrated the efficiency without considering the EMI filter with AC/DC converter. However, with input AC voltage being 220 V can convert AC into the DC V DD = 300 V, the EMI filter will only consume less than 0.1 W from the total power of 65 W. The overall efficiency is still higher than 96%. It is also worth to note that the output diode with average 1 A go through it will consume 1 W. Thus, other circuit elements including the snubber circuit consumes only 1.5 W.
Even though we demonstrated the efficiency without considering the EMI filter with AC/DC converter. However, with input AC voltage being 220 V can convert AC into the DC VDD = 300 V, the EMI filter will only consume less than 0.1 W from the total power of 65 W. The overall efficiency is still higher than 96%. It is also worth to note that the output diode with average 1 A go through it will consume 1 W. Thus, other circuit elements including the snubber circuit consumes only 1.5 W. Many other experiments have been performed to examine the ZCS performance for the flyback converter which are summarized as shown in Figure 16. It is observed from the experiments that the output power increases with the increasing input DC voltage as shown in Figure 16a. The maximum power efficiency occurs at around VDD = 150 V which is equivalent to the AC input voltage 110 V that is commonly adopted in America, Canada, Japan and Taiwan. The maximum power output is at higher AC input voltage which yields higher DC output VDD from the AC/DC converter. It is also observed from the experiments that both the power and power efficiency will be degraded subjected to the snubber resistor quality or precision as shown in Figure 16b, however not much. The result as depicted in Figure 16c shows that the duty cycle is rather linearly decreasing with the increasing switching frequency. In order to adjust the output voltage in the closed loop control of flyback converter, we need to adjust the switching frequency according to Equation (17). The algorithm is quite simple to implement in the logic ICs or microprocessors due to the linearity of the duty cycle vs. switching frequency. It may be naming the ratio between duty cycle vs. switching frequency as the duty line equation as follows.
The corresponding D as shown in Figure 16c is 191.4, which implies that for the cur- Many other experiments have been performed to examine the ZCS performance for the flyback converter which are summarized as shown in Figure 16. It is observed from the experiments that the output power increases with the increasing input DC voltage as shown in Figure 16a. The maximum power efficiency occurs at around V DD = 150 V which is equivalent to the AC input voltage 110 V that is commonly adopted in America, Canada, Japan and Taiwan. The maximum power output is at higher AC input voltage which yields higher DC output V DD from the AC/DC converter. It is also observed from the experiments that both the power and power efficiency will be degraded subjected to the snubber resistor quality or precision as shown in Figure 16b, however not much. The result as depicted in Figure 16c shows that the duty cycle is rather linearly decreasing with the increasing switching frequency. In order to adjust the output voltage in the closed loop control of flyback converter, we need to adjust the switching frequency according to Equation (17). The algorithm is quite simple to implement in the logic ICs or microprocessors due to the linearity of the duty cycle vs. switching frequency. It may be naming the ratio between duty cycle vs. switching frequency as the duty line equation as follows. Equation (52) indicates that the output voltage is decreasing with the increasing switching frequency, which is in consistent with the output power decreasing as shown in Figure 16c. The circuit allows the designer to adjust the switching frequency and the duty cycle are recommended in variable frequency pulse width modulation (VFPWM) [49]. With the VFPWM, we are able to control both the switching frequency and the duty cycle through simple voltage inputs separately. The DCM with ZCS fulfillment can then be achieved.  The corresponding D as shown in Figure 16c is 191.4, which implies that for the current circuit parameters does not allow the circuit to be switching in the frequency higher than 500 kHz. The result is in consistent with the f 2 in Table 4. Equation (17) can then be rewritten as follows providing that the efficiency is assumed 100%.
Equation (52) indicates that the output voltage is decreasing with the increasing switching frequency, which is in consistent with the output power decreasing as shown in Figure 16c. The circuit allows the designer to adjust the switching frequency and the duty cycle are recommended in variable frequency pulse width modulation (VFPWM) [49]. With the VFPWM, we are able to control both the switching frequency and the duty cycle through simple voltage inputs separately. The DCM with ZCS fulfillment can then be achieved.

Analysis and Discussion
The design methodology of the DCM control directly relates to the determination of the switching frequency and the duty. The target is to achieve the best efficiency through the proper selection of transformer and snubber circuit parameters. The low switching loss strategy proposed in this paper can yield a high efficiency in the DCM operation for a conventional flyback converter with high switching frequency using GaN HEMT. Our method is simply achieved by having ZVS with ZCS occurred simultaneously in the instance of switching. The step-by-step design methodology is depicted in Figure 17. In this method we started from studying the flyback converter specifications which include mainly the input voltage (typically 150/300 V), the power density (W/cc), the output power (W) and the output voltage (V). From the specifications, the output load (Ohm), the input voltage, the output voltage and the switching frequency together determines the critical condition for CCM or the BCM. It is then using the transformer turn ratio and input voltage to determine the minimum breakdown voltage for the GaN HEMT as well as the current rating required. After the transistor has been verified in its feasible working range, then ZVS and ZCS are determined from the equations stated in Section 2. According to either the PSpice simulation or experiments, we then determine the redesign of the snubber or the selection of transformers.

Conclusions
The flyback converter can yield higher power efficiency during the DCM than that of the CCM for less than 100 W low power output.

Conclusions
The flyback converter can yield higher power efficiency during the DCM than that of the CCM for less than 100 W low power output. The new knowledges that are conveyed in this paper including the DCM resonance mechanism and the relation among switching frequency, duty, ZVS and ZCS. The understanding of the DCM resonance mechanism is the key to fulfill ZVS and ZCS simultaneously and thus the switching loss of the flyback converter can be reduced. This paper provides an insight of the DCM mechanism. The current jumps to its first maximum after the switch turns off and bumps back, later on, to its second maximum. This paper explains the reason why the current bumps back and how that prolongs the current flowing time. The precise calculation of the current flowing time proceeds the drain-source voltage of the switch to swing down toward zero voltage. This paper shows that the drain-source voltage swing on the switch is critical to the ZVS. The condition enabling the ZVS to occur is to increase the turn ratio a of the transformer. In contrast with the quasi-resonant fly back converter wherein it makes use of the parasitic elements to manipulate the inductor voltage partially resemble a resonance action. The DCM resonant behaves as a nature from the current in its secondary winding. The control of the DCM can be implemented by controlling the switching frequency. The duty cycle following the switching frequency change can be adjusted in a linear way achieved by using the VFPWM that the authors have presented before. Nevertheless, the output resistance on the load is an important factor that affects the output voltage. For the heavy load application, the transformer made with small inductance is preferred in order to allow the DCM to occur. This paper demonstrated the particular applications own as high as 97.6% power efficiency. The high-power efficiency for fast charging application may be targeting at the 99% efficiency. This can be accomplished by further redesign the transformer, use the AMR (active MOS rectifier) or ideal diode on the secondary winding to replace the normal FRD (fast recovery diode), and/or integrate the power module together with the gate drive into a SiP (system in chip) packaging. These possibilities to promote the power efficiency to its extreme will be included in our future work.