A Family of Transformerless Quadratic Boost High Gain DC-DC Converters

: This paper presents three new and improved non-isolated topologies of quadratic boost converters (QBC). Reduced voltage stress across switching devices and high voltage gain with single switch operation are the main advantages of the proposed topologies. These topologies utilize voltage multiplier cells (VMC) made of switched capacitors and switched inductors to increase the converter’s voltage gain. The analysis in continuous conduction mode is discussed in detail. The proposed converter’s voltage gain is higher than the conventional quadratic boost converter, and other recently introduced boost converters. The proposed topologies utilize only a single switch and have continuous input current and low voltage stress across switch, capacitors, and diodes, which leads to the selection of low voltage rating components. The converter’s non-ideal voltage gain is also determined by considering the parasitic capacitance and ON state resistances of switch and diodes. The efﬁciency analysis incorporating switching and conduction losses of the switching and passive elements is done using PLECS software (Plexim, Zurich, Switzerland). The hardware prototype of the proposed converters is developed and tested for veriﬁcation.


Introduction
High gain DC-DC converters are now used in several applications when high DC voltage is required. These converters can work in the power range of few milliwatts to a megawatt range. They are used in solar photovoltaic (PV) applications, robotics, aircraft, medical equipment, high voltage DC systems, and electric vehicles. These converters are made up of different combinations of inductors, capacitors, diodes, and switches that are connected suitably so that energy transfer can take place between inductors and capacitors. The energy is stored in the switched inductors and then transferred to the capacitors to obtain a high voltage [1] at the output. Conventional switch mode boost converter (CBC) and other variants like single-ended primary-inductor converter (SEPIC) and ZETA converters cannot produce high voltage gain, and the active and passive components have high voltage and current stress. Moreover, the efficiency also decreases significantly at higher duty ratios. Several topologies utilize a combination of switched capacitors [2] and switched inductors to obtain high voltage. Topologies that utilize coupled inductors and transformers are also used to obtain a very high voltage. A voltage multiplier cell (VMC) is also used to boost or buck-boost [3] the voltage at low duty cycles. High gain with reduced stress voltage and current stress on the switching devices and passive components, common ground, continuous input current, and reduced number of components are desirable features that are required in any high gain DC-DC converter. The converter has high efficiency and reduced stress across capacitors. A modified boost converter using switched inductors VMC is proposed in [4]. A single switch modified boost and SEPIC converters with continuous input current and low voltage stress across the switch are proposed in [5,6]. Hybrid structures with switched inductors [7] and multilevel structures using switched capacitors [8] are used to increase the gain of the converter. A VMC made up of a switched inductor limits the high ripple in input current, whereas in switched capacitor topologies high spike in charging current is noticed [9]. Some topologies use voltage doublers before the output to reduce the stress and increase the voltage gain, at the cost of an increase in the number of components [10]. The topologies proposed in [11,12] have quadratic voltage gain and utilize only a single switch. In [13], a three-winding coupled inductor is used but that makes the circuit complex. The problems associated with leakage inductance of the coupled inductor is addressed in [14] without using the snubber circuit. A transformer with a voltage doubler is designed to obtain very high voltage is developed in [15]. A converter is proposed in [16] which can work in triple duty mode, but to obtain a high gain, the number of switches is high. To achieve high gain, boost converters with different types of VMC combinations are shown in [17]. Single input, dual output DC-DC converters have the advantage of two outputs [18] with reduced stress on the output capacitors. The interleaved high gain boost converter has H-bridge structure with unidirectional switches. The converters utilize many VMCs to output to increase the voltage gain, which is a disadvantage. These converters utilize at least [19][20][21] two switches that can be operated at the same or different duty cycle. In quasi-Z-source topologies, the duty cycle is mostly limited up to less than 0.5. These converters need a careful operation as the converter can become [22,23] unstable at smaller duty ratios close to the maximum limit. In these converters, the input current is continuous. The converter gain is affected by several factors such as parasitic resistance of inductors and capacitors and ON-state resistance of switches and diodes. Hence, a non-ideal model [24] should be developed to calculate the gain in non-ideal conditions. Quadratic boost converters (QBC) produce high voltage gain at low duty ratios. High voltage gain at low duty ratios reduces the current and voltage stress high efficiency can be achieved. These converters mostly utilize VMC and several inductors and capacitors to achieve the high voltage gain. Non-isolated topologies of these converters are suitable in microgrid operations [25][26][27][28] for medium power applications. These converters can be put at the front end of the inverter to maintain the DC-link voltage. In [29] an ultra-high gain DC-DC converter is proposed with three inductors and two switches. Table 1 presents the summary of important high gain DC-DC converters discussed above in the literature. From the table, it can be observed that topologies can be differentiated based on the features such as voltage gain, switch voltage stress, components count, and common ground. It is to be mentioned that the desirable features such as high voltage gain and low voltage stress with a reduced number of components may not always be present in all topologies. A tradeoff between high gain and the number of components always exists. Similarly, other features like common ground and continuous input current may also be important in different applications. In this paper, a family of quadratic boost converters with switched capacitors is proposed. Further, the structure can be extended to increase the voltage gain. The proposed converter's gain is double the gain of a conventional quadratic boost converter (CQBC), and the voltage stress is half the output voltage. The converters have only one switch and continuous input current, which makes them suitable for solar PV and microgrid applications. Moreover, no transformer or coupled inductor is used to achieve such a high gain. In Sections 2-4 the structure and working of the proposed three converters are discussed in detail. In Section 5, the comparison of the proposed converter with other high gain converters in terms of voltage gain, voltage, and current stresses are described. In Section 6, the experimental results of all three converters are presented. In Section 7, the conclusion is discussed.

Proposed Converter I
The power circuit in Figure 1a comprises one active switch S, two inductors L 1 and L 2 , four capacitors C 1 , C 2 , C 3 , and C o and five diodes D 1 , D 2 , D 3 , D 4 , and D 5 . The converter is operated at high-frequency f s . The network consisting of D 2 , C 2 , C 3 , and D 5 constitutes a voltage boosting cell. The advantage of this circuit is that it has a single switch S with lower complexity with continuous input current and utilizing energy with a single input DC source. The power circuit in Figure 1a comprises one active switch S, two inductors L1 and L2, four capacitors C1, C2, C3, and Co and five diodes D1, D2, D3, D4, and D5. The converter is operated at high-frequency fs. The network consisting of D2, C2, C3, and D5 constitutes a voltage boosting cell. The advantage of this circuit is that it has a single switch S with lower complexity with continuous input current and utilizing energy with a single input DC source.

Analysis in CCM Mode
There are two modes of operation based on the switching signal. The first is when the switch is ON, and the second one is when the switch is OFF. Important waveforms for the proposed converter are shown in Figure 2.
When the switch S is turned ON, the equivalent circuit is depicted in Figure 1b. The diode D3 and D4 are conducting, and other diodes are reverse biased. Both the inductor currents rise while capacitor C1, C2, and C3 discharge to feed the load R and the related equations are as follows:

Analysis in CCM Mode
There are two modes of operation based on the switching signal. The first is when the switch is ON, and the second one is when the switch is OFF. Important waveforms for the proposed converter are shown in Figure 2.

MODE I [0-DT]
When the switch S is turned ON, the equivalent circuit is depicted in Figure 1b. The diode D 3 and D 4 are conducting, and other diodes are reverse biased. Both the inductor currents rise while capacitor C 1 , C 2 , and C 3 discharge to feed the load R and the related equations are as follows: The switch S is turned OFF, as shown in Figure 1c. The diodes D 1 , D 2 , and D 5 are conducting and the rest diodes are OFF. The inductor currents fall, and C 1 , C 2 , and C 3 discharge and load R are fed by C o . The related equations are as follows: From Equations (1) and (3), we obtain Applying the principle of voltage-second balance on the inductors L 1 and L 2 The relations obtained from (6) and (7) can be used to find the voltage gain It is assumed that the circuit is ideal by applying the energy conservation principle where I L 1 is the average current of inductor L 1 and I o = V O R is the load current.
The average value of the inductor current I L 2 can be calculated by applying a charge balance on the capacitor C 1 .
The current stress on the switch of the proposed converter I is given by (10).
Energies 2021, 10, x FOR PEER REVIEW 6 of 26 The current stress on the switch of the proposed converter I is given by (10). The voltage stress or blocking voltage of a power device is important for deciding the voltage rating of the switch. The voltage stress across the power switch (VS) and diodes (D1, D2, D3, D4, and D5) of the converter I can be derived as It can be inferred from (11) that the stress across D1, D3, D4, and D5 and switch S is equal to half of the output voltage.

Passive Components Selection
The peak-to-peak ripple values of the inductor current can be expressed as With known values of D, the input source , and switching frequency fs, the design The voltage stress or blocking voltage of a power device is important for deciding the voltage rating of the switch. The voltage stress across the power switch (V S ) and diodes (D 1 , D 2 , D 3 , D 4 , and D 5 ) of the converter I can be derived as It can be inferred from (11) that the stress across D 1 , D 3 , D 4 , and D 5 and switch S is equal to half of the output voltage.

Passive Components Selection
The peak-to-peak ripple values of the inductor current can be expressed as With known values of D, the input source V in , and switching frequency f s , the design values of inductors L 1 and L 2 can be calculated.
For achieving the boundary condition, I L 1 = ∆i L1 2 and I L 2 = ∆i L2 2 . The condition of continuous conduction mode can be achieved using (9) and (12): The peak-to-peak ripple across the capacitors C 1 , C 2 , C 3 , and C o is ∆v C1 , ∆v C2 , ∆v C3 , and ∆v C4 , respectively, and can be expressed as With known values of D, the input source V in and switching frequency f s, the design values of capacitances can be calculated from Equation (14).

Boundary Condition Mode
It is assumed that the inductor current I L 1 remains continuous while inductor current I L 2 goes in discontinuous conduction mode with zero current at the end of every switching period.
The DC value of the inductor current L 2 can be found as The boundary normalized inductor time constant on the inductor L 2 is defined as The boundary normalized inductor time can be derived from (10) and (12): To operate the converter in CCM mode, τ L2 must be greater than τ L2 b Otherwise, the converter goes in DCM, as depicted in Figure 3.
The peak-to-peak ripple across the capacitors C1, C2, C3, and Co is ∆v C1 , ∆v C2 , ∆v C3 , and ∆v C4 , respectively, and can be expressed as With known values of D, the input source V in and switching frequency fs, the design values of capacitances can be calculated from Equation (14).

Boundary Condition Mode
It is assumed that the inductor current I L 1 remains continuous while inductor current 2 goes in discontinuous conduction mode with zero current at the end of every switching period.
The DC value of the inductor current 2 can be found as The boundary normalized inductor time constant on the inductor 2 is defined as The boundary normalized inductor time can be derived from (10) and (12): To operate the converter in CCM mode, 2 must be greater than τ L2 b Otherwise, the converter goes in DCM, as depicted in Figure 3.

Proposed Converter II
The proposed converter II is shown in Figure 4a and has an equal number of components of converter I. The power circuit consists of one switch s, two inductors L 1 and L 2 , five diodes D 1 , D 2 , D 3 , D 4 , and D 5 , and four capacitors C 1 , C 2 , C 3 , and an output capacitor C o supplying energy to load R. The proposed converter has the inductor on the input side, which makes the current continuous with very low ripple. ergies 2021, 10, x FOR PEER REVIEW 8 of 26

Proposed Converter II
The proposed converter II is shown in Figure 4a and has an equal number of components of converter I. The power circuit consists of one switch s, two inductors L1 and L2, five diodes D1, D2, D3, D4, and D5, and four capacitors C1, C2, C3, and an output capacitor Co supplying energy to load R. The proposed converter has the inductor on the input side, which makes the current continuous with very low ripple.

Analysis in CCM Mode
The two modes of operation follow.

Mode I [0-DT]
When the switch is turned ON, the equivalent circuit is depicted in Figure 4b. The diodes D2 and D5 are conducting while D1, D3, and D4 are reversed biased. The switch S is conducting an interval of DT where D is the duty ratio, and T is the switching signal period. The currents of both inductors rise and capacitors C1, C2, and C3 discharge to charge output capacitor C0 to feed load R. The related equations follow:

Analysis in CCM Mode
The two modes of operation follow.

Mode I [0-DT]
When the switch is turned ON, the equivalent circuit is depicted in Figure 4b. The diodes D 2 and D 5 are conducting while D 1 , D 3 , and D 4 are reversed biased. The switch S is conducting an interval of DT where D is the duty ratio, and T is the switching signal period. The currents of both inductors rise and capacitors C 1 , C 2 , and C 3 discharge to charge output capacitor C 0 to feed load R. The related equations follow: Contrarily, the switch is in OFF condition, and diodes D 1 , D 3 , and D 4 are conducting while diode D 2 and D 5 are in reverse biased, as shown in Figure 4c. The important waveforms for this converter are shown in Figure 5. The switch is conducting for an interval of (1 − D) T. The currents of both inductors fall to charge capacitors C 1 , C 2 , and C 3 , while C 0 separately feeds the load R. The related equations follow: Using (15) and (17), the capacitor voltages are Applying the principle of voltage-second balance on the inductors L 1 and L 2 by using (14)- (18) gives Results obtained from (20) and (21) are used to find voltage gain of the proposed converter II: It is assumed that the circuit is ideal by applying the energy conservation principle: where I L 1 is the average current of inductor L 1 and I o = V O R is the load current. The average value of the inductor current 2 could be calculated by applying charge balance on the capacitor C1: The current stress on the switch of proposed converter II is given by (27). The voltage stress or blocking voltage of a power device is important to decide the ratings of the semiconductor devices. The stress of the power switch (VS) and across D1, D2, D3, D4, and D5 of the converter II can be shown as follows It can be inferred from (28) that the stress across diodes D1, D3, D4, and D5 and switch S is equal and half of the output voltage.

Passive Component Selection
The peak-to-peak ripple values of the inductor current can be expressed as The average value of the inductor current I L 2 could be calculated by applying charge balance on the capacitor C 1 : The current stress on the switch of proposed converter II is given by (27). The voltage stress or blocking voltage of a power device is important to decide the ratings of the semiconductor devices. The stress of the power switch (V S ) and across D 1 , D 2 , D 3 , D 4 , and D 5 of the converter II can be shown as follows It can be inferred from (28) that the stress across diodes D 1 , D 3 , D 4 , and D 5 and switch S is equal and half of the output voltage.

Passive Component Selection
The peak-to-peak ripple values of the inductor current can be expressed as With known values of D, the input source V in and switching frequency f s , the design values of inductors L 1 and L 2 can be calculated.
The boundary condition is achieved when the minimum inductor current reaches zero, i.e., I L 1 = ∆i L1 2 and I L 2 = ∆i L2 2 . The condition of continuous conduction mode can be achieved as The peak-to-peak ripple across the capacitors C 1 , C 2 , C 3 , and C o is ∆v C1 , ∆v C2 , ∆v C3 and ∆v C4 , respectively, and can be expressed as With known values of D, the input source V in , and switching frequency f s , the design values of capacitances can be calculated using (31) with the assumption of C 2 = C 3 .

Boundary Condition
It is assumed that the inductor current I L 1 remains continuous while inductor current I L 2 goes in discontinuous conduction mode with zero current at the end of every switching period.
The DC value of the inductor current L 2 can be found as The boundary normalized inductor time constant on the inductor L 2 is defined as The boundary normalized inductor time can be derived from (27) and (29): To operate the converter in CCM mode, τ L2 must be greater than τ L2 b ; otherwise, the converter goes in DCM, as depicted in Figure 6.

Proposed Converter III
Proposed converter III is an extension of proposed converter II in which inductor L2 is replaced with a switched inductor boost cell consisting of D3, D4, L2, and L3 as shown in Figure 7a, with single switch S and energy increased by boosting cell to feed load R. The

Proposed Converter III
Proposed converter III is an extension of proposed converter II in which inductor L 2 is replaced with a switched inductor boost cell consisting of D 3 , D 4 , L 2 , and L 3 as shown in Figure 7a, with single switch S and energy increased by boosting cell to feed load R. The proposed converter has two voltage multiplier cells that increase output voltage by four times.

Proposed Converter III
Proposed converter III is an extension of proposed converter II in which inductor L2 is replaced with a switched inductor boost cell consisting of D3, D4, L2, and L3 as shown in Figure 7a, with single switch S and energy increased by boosting cell to feed load R. The proposed converter has two voltage multiplier cells that increase output voltage by four times.

Analysis in CCM Mode
The continuous conduction mode of the converter can be discussed in detail with two modes of operation.

Mode I [0-DT]
When the switch is turned ON, the equivalent circuit is depicted in Figure 7b and Figure 8. The diodes D2, D3, D5, and D7 are conducting while D1, D5, and D6 are reversed biased. All three inductor currents rise and capacitors C1 to C4 discharge to feed the load R. The switch S conducts for the DT period. The related equations follow:

Analysis in CCM Mode
The continuous conduction mode of the converter can be discussed in detail with two modes of operation.

Mode I [0-DT]
When the switch is turned ON, the equivalent circuit is depicted in Figures 7b and 8. The diodes D 2 , D 3 , D 5 , and D 7 are conducting while D 1 , D 5 , and D 6 are reversed biased.
All three inductor currents rise and capacitors C 1 to C 4 discharge to feed the load R. The switch S conducts for the DT period. The related equations follow:

Mode I [DT-T]
Contrarily, the switch is in OFF condition, and diodes D 1 , D 5 , and D 6 are conducting while diode D 2 , D 3 , D 5 , and D 7 are in reverse biased, as shown in Figures 7c and 8. The switch is conducting for an interval of (1-D) T. Both the inductor currents fall to charge capacitors C 1 , C 2, and C 3 , while C 0 separately feeds the load R. The related equations follow: Applying the principle of voltage-second balance on the inductors L 1 and L 2 and L 3 and by using (33)-(36), V o and V C1 can be obtained as shown in (39) and (40). Results obtained from (37) and (38) are used to find the voltage gain of the proposed converter III: 2 (41) Results obtained from (37) and (38) are used to find the voltage gain of the proposed converter III: It is assumed that the circuit is ideal by applying the energy conservation principle: where I L 1 is the average current of inductor L 1 and I o is the load current. The DC component of the inductor currents of L 2 and L 3 (I L 2 = I L 3 ) can be calculated by applying charge balance on capacitors C 1 and C 2 : The current stress on the switch of the proposed converter III is given by (43). The voltage stress or blocking voltage of a power device is important to decide the semiconductor device rating.
The stress of the power switch(S) and diodes of the converter III can be derived as It can be inferred from (44) that the stress across D 5 , D 6 , D 7 and S is equal and half of the output voltage.

Passive Component Selection
The peak-to-peak ripple values of the inductor current and capacitor voltages can be expressed as With known values of D, the input source V in , and switching frequency f s , the design values of inductors L 1 and L 2 = L 3 can be calculated.
The boundary condition is achieved when the minimum inductor current reaches zero, i.e., I L 1 = ∆i L1 2 and I L 2 = ∆i L2 2 . The condition of continuous conduction mode can be achieved as The peak-to-peak ripple across the capacitors C 1 , C 2 , C 3 , C 4 , and C o are ∆v C1 , ∆v C2 , ∆v C3 , ∆v C4 , and ∆v Co , respectively, and can be expressed as With known values of D, the input source V in , and switching frequency f s , the design values of capacitances can be calculated using (47) with the assumption of C 3 = C 4 .

Boundary Condition
It is assumed that the inductor current I L 1 remains continuous while inductor current I L 2 = I L 3 goes in discontinuous conduction mode with zero current at the end of every switching period.
The DC value of the inductor current L 2 = L 3 in this mode can be found as The boundary normalized inductor time constant on the inductor L 2 = L 3 is defined as The boundary normalized inductor time can be derived from (43) and (45): To operate the converter in CCM mode, τ L2,3 must be greater than τ L2,3 b Otherwise, the converter goes in DCM, as depicted in Figure 9.

Boundary Condition
It is assumed that the inductor current I L 1 remains continuous while inductor current I L 2 = I L 3 goes in discontinuous conduction mode with zero current at the end of every switching period.
The DC value of the inductor current L 2 = L 3 in this mode can be found as The boundary normalized inductor time constant on the inductor L 2 = L 3 is defined as The boundary normalized inductor time can be derived from (43) and (45): To operate the converter in CCM mode, τ L2,3 must be greater than τL2,3b Otherwise, the converter goes in DCM, as depicted in Figure 9.

Comparison of the Proposed Topologies
Several DC-DC converters have been proposed to achieve high gain and improved high efficiency. In this section, the comparison of the proposed converter with other recently introduced topologies in Table 2 is shown. The converters are compared based on voltage gain, switch voltage stress, current stress, and component count. Converter I and III have lower components than the proposed converter in [7]. The proposed converter in [30] has more components than all the proposed converters. In addition, it utilizes many power switches, which makes the circuit bulky. The curve of the proposed converter III is CCM DCM Figure 9. Boundary between CCM and DCM mode of operation.

Comparison of the Proposed Topologies
Several DC-DC converters have been proposed to achieve high gain and improved high efficiency. In this section, the comparison of the proposed converter with other recently introduced topologies in Table 2 is shown. The converters are compared based on voltage gain, switch voltage stress, current stress, and component count. Converter I and III have lower components than the proposed converter in [7]. The proposed converter in [30] has more components than all the proposed converters. In addition, it utilizes many power switches, which makes the circuit bulky. The curve of the proposed converter III is the highest among all the curves of Figure 10. Proposed converters I and II also have a high voltage gain compared to the other topologies above D = 0.3. The gain of converters I and II is also high as compared to other converters, which substantially increases above D = 0.4. The proposed converter in [7] has three inductors, but the gain is much less than the proposed family of converters. Similarly, the topology of [8] uses two inductors, but the gain is limited at higher duty ratios. The conventional quadratic boost converter (QBC) has a low gain compared to the proposed topologies. The voltage stress across the switch as a function of voltage gain is shown in Figure 11a. As the gain increases, the voltage stress across the switch of converters I and II is much less than the other topologies, except for the topologies proposed in [8,30]. Moreover, for voltage gain up to 12 times, the stress across the converter III is less than other converters proposed in [6,7,14,18,30]. The low voltage stress across components results in increased efficiency and low cost of the converter. The efficiency of the converter depends on factors such as voltage/current ratings, components count, and the type of converter. The comparison concerning the switch current stress is shown in Figure 11b. The proposed converters have lower current stress than the converter proposed in [6]. The switch current stress of all three proposed converters and the converter presented in [14] is the same as QBC, but QBC has low voltage gain and high voltage stress. The curve in Figure 12 presents the variation of efficiency with the output power at constant load resistance. The efficiency of proposed converter I and II is higher as compared to the proposed converter III. This is because of the presence of more components in the third topology. The efficiency of all three converters decreases with the increase in the output power. With the rise in the output power, the current in the internal circuit increases, which increases the conduction losses in the circuit. The efficiency of proposed converter II is greater than I, III, [6][7][8]14], and quadratic boost converter (QBC). The converter [18] has the highest efficiency among the listed converters because it has the lowest current and voltage stress on the switch, but it has a more components, which makes the circuit bulky.   The measured and ideal voltage gain for converters I and II are presented in Figure 13a. At lower duty, the difference between the ideal and measured voltage gain is very low; however, the difference increases with the duty ratio increase. This happens because, at a higher duty ratio, the internal losses in the circuit become higher. The measured gain is taken in experimental conditions. Loss calculation is done on PLECS software by putting the switching and conduction loss data into the lookup table of the developed thermal model. In PLECS software, accurate loss analysis can be done by using the real models of switches and diodes from the datasheet to calculate the conduction and switching losses. The bifurcation of power loss in different components for converter I and II are shown in Figure 13b. The measured and ideal voltage gain for converters I and II are presented in Figure  13a. At lower duty, the difference between the ideal and measured voltage gain is very low; however, the difference increases with the duty ratio increase. This happens because, at a higher duty ratio, the internal losses in the circuit become higher. The measured gain is taken in experimental conditions. Loss calculation is done on PLECS software by putting the switching and conduction loss data into the lookup table of the developed thermal model. In PLECS software, accurate loss analysis can be done by using the real models of switches and diodes from the datasheet to calculate the conduction and switching losses. The bifurcation of power loss in different components for converter I and II are shown in Figure 13b.

Experimental Verification of the Proposed Converters
The laboratory prototype of each proposed converter was developed and tested under laboratory conditions. The hardware setup is shown in Figure 14. The measured and ideal voltage gain for converters I and II are presented in Figure  13a. At lower duty, the difference between the ideal and measured voltage gain is very low; however, the difference increases with the duty ratio increase. This happens because, at a higher duty ratio, the internal losses in the circuit become higher. The measured gain is taken in experimental conditions. Loss calculation is done on PLECS software by putting the switching and conduction loss data into the lookup table of the developed thermal model. In PLECS software, accurate loss analysis can be done by using the real models of switches and diodes from the datasheet to calculate the conduction and switching losses. The bifurcation of power loss in different components for converter I and II are shown in Figure 13b.

Experimental Verification of the Proposed Converters
The laboratory prototype of each proposed converter was developed and tested under laboratory conditions. The hardware setup is shown in Figure 14.

Experimental Verification of the Proposed Converters
The laboratory prototype of each proposed converter was developed and tested under laboratory conditions. The hardware setup is shown in Figure 14.

Proposed Converter I
The design specification of the proposed converter I is presented in Table 3. The laboratory hardware prototype of the converter is shown in Figure 15.

Proposed Converter I
The design specification of the proposed converter I is presented in Table 3. The laboratory hardware prototype of the converter is shown in Figure 15.

Proposed Converter I
The design specification of the proposed converter I is presented in Table 3. The laboratory hardware prototype of the converter is shown in Figure 15.

Proposed Converter II
The design specification of the proposed converter II is presented in Table 4. The laboratory hardware prototype of the converter is shown in Figure 17.

Proposed Converter II
The design specification of the proposed converter II is presented in Table 4. The laboratory hardware prototype of the converter is shown in Figure 17.

Proposed Converter III
The design specification of the proposed converter III is presented in Table 5. The laboratory hardware prototype of the converter is shown in Figure 19.

Proposed Converter III
The design specification of the proposed converter III is presented in Table 5. The laboratory hardware prototype of the converter is shown in Figure 19.

Proposed Converter III
The design specification of the proposed converter III is presented in Table 5. The laboratory hardware prototype of the converter is shown in Figure 19. Table 5. Design specification of converter III (adapted from [31]).     In the first converter case, the hardware prototype's measured output voltage is 127 volts at a 0.4 duty ratio. However, in the second topology, the output voltage is measured as 130 volts at the same input voltage and duty ratio as that of the first converter; due to higher load resistance, the voltage is higher in the second converter case. In the first converter case, the load resistance is only around 60% of the load resistance, as in the second converter case. Thus, the current is high in the first converter circuit, which increases the first converter's internal losses compared to that of the second converter. With the increase in the load current, the output voltage decreases because of the rise in the circuit's internal losses.

Maximum
In the third converter case, the measured output voltage is 128 volts at a duty ratio of 0.2 and load resistance of 200 Ω, which is almost 15% lower than the calculated voltage for the ideal condition. The deviation from the ideal voltage is the same as explained before, which is internal power loss. These internal losses depend on the number of components in the circuit, ESR (equivalent series resistance) of the passive components, diode forward voltage drop, switching frequency and load, etc. The findings of the experimental results are provided in Table 6.

Conclusions
The paper presents three different high gain DC-DC converter topologies of the quadratic gain family. While two of the topologies have twice the quadratic boost gain, the third has four times the quadratic boost gain, making them extremely effective for low duty high gain operation at high efficiency. None of the topologies uses any transformers and has a gain of more than ten times at a duty ratio of less than 0.5. Topology II is found In the first converter case, the hardware prototype's measured output voltage is 127 volts at a 0.4 duty ratio. However, in the second topology, the output voltage is measured as 130 volts at the same input voltage and duty ratio as that of the first converter; due to higher load resistance, the voltage is higher in the second converter case. In the first converter case, the load resistance is only around 60% of the load resistance, as in the second converter case. Thus, the current is high in the first converter circuit, which increases the first converter's internal losses compared to that of the second converter. With the increase in the load current, the output voltage decreases because of the rise in the circuit's internal losses.
In the third converter case, the measured output voltage is 128 volts at a duty ratio of 0.2 and load resistance of 200 Ω, which is almost 15% lower than the calculated voltage for the ideal condition. The deviation from the ideal voltage is the same as explained before, which is internal power loss. These internal losses depend on the number of components in the circuit, ESR (equivalent series resistance) of the passive components, diode forward voltage drop, switching frequency and load, etc. The findings of the experimental results are provided in Table 6.

Conclusions
The paper presents three different high gain DC-DC converter topologies of the quadratic gain family. While two of the topologies have twice the quadratic boost gain, the third has four times the quadratic boost gain, making them extremely effective for low duty high gain operation at high efficiency. None of the topologies uses any transformers and has a gain of more than ten times at a duty ratio of less than 0.5. Topology II is found to have comparatively high efficiency as compared to topology 1 and III. The stress in switches in the three topologies are less for a wide operating range as compared to many recently proposed high gain quadratic converters. The efficiency of converter I and converter II at 100 W is found to be 92% and 93.2% respectively. The efficiency of converter III is close to 87%. The continuous input current along with reduced voltage stress makes all of the proposed topologies suitable for renewable energy applications.