Asymmetric Multilevel Inverter Topology and Its Fault Management Strategy for High-Reliability Applications

: As the applications of power electronic converters increase across multiple domains, so do the associated challenges. With multilevel inverters (MLIs) being one of the key technologies used in renewable systems and electriﬁcation, their reliability and fault ride-through capabilities are highly desirable. While using a large number of semiconductor components that are the leading cause of failures in power electronics systems, fault tolerance against switch open-circuit faults is necessary, especially in remote applications with substantial maintenance penalties or safety-critical operation. In this paper, a fault-tolerant asymmetric reduced device count multilevel inverter topology producing an 11-level output under healthy conditions and capable of operating after open-circuit fault in any switch is presented. Nearest-level control (NLC) based Pulse width modulation is implemented and is updated post-fault to continue operation at an acceptable power quality. Reliability analysis of the structure is carried out to assess the beneﬁts of fault tolerance. The topology is compared with various fault-tolerant topologies discussed in the recent literature. Moreover, an artiﬁcial intelligence (AI)-based fault detection method is proposed as a machine learning classiﬁcation problem using decision trees. The fault detection method is successful in detecting fault location with low computational requirements and desirable accuracy.


Introduction
The increased adoption of power electronics in all areas in the electrical power domain has made various feasible innovations such as electric vehicles [1,2], HVDC transmission systems, large-scale transformation towards renewable energy resources [3]. With the DC-AC conversion playing a significant role, the development of multilevel inverters (MLIs) is an essential process. Succeeding the conventional two-level and three-level inverter topologies, MLIs possess the advantages of better power quality, efficient conversion, reduced thermal management, smaller filter size as well as in-built redundancy and voltage boosting features [4,5]. The classical MLI topologies are the Neutral Point Clamped (NPC), the Flying Capacitor (FC), and the Cascaded H-bridge (CHB) topologies. Since their inception, a vast diversity of newer structures has been proposed to eliminate the disadvantages of classical topologies. They include reduced device count, lower per-unit total standing voltage, and greater efficiency converters. Recent developments in MLI design are also focused on EMI, volume, weight and cooling, and packaging requirements [6].
Implementing a large number of power semiconductor switches leads to an increased susceptibility towards fault and makes monitoring and diagnosis more complex [7]. This can be unacceptable in safety-critical applications such as onboard power systems. Isolated

Proposed Structure
The proposed 11-level topology is depicted in Figure 1. Observably, the structure comprises six unidirectional switches and three bidirectional switches, requiring 12 IGBT components. A pair of bidirectional switches S 8 and S 9 are redundant, with these switches being used exclusively under faulty states. The structure utilizes three DC sources with per unit magnitudes of 0.5, 1, and 1, respectively. The structure can generate an 11-level output voltage waveform, with five levels each of positive and negative polarity, respectively, and a zero level. The switching strategy under healthy operation is described in Table 1, and the corresponding conduction diagram is presented in Figure 2. The ratio of the magnitude of the dc sources is as V 2 = V dc and V 1 = 0.5V dc . The total standing voltage (TSV) of the structure is 20V dc , with the per-unit TSV having a magnitude of 20/2.5 = 8V dc .
Energies 2021, 14, x FOR PEER REVIEW 3 of 21 based on artificial intelligence techniques is also presented, which can localize a fault under varying load and modulation index conditions. After fault mitigation, continued operation with an acceptable quality waveform on the output can be performed.

Proposed Structure
The proposed 11-level topology is depicted in Figure 1. Observably, the structure comprises six unidirectional switches and three bidirectional switches, requiring 12 IGBT components. A pair of bidirectional switches S8 and S9 are redundant, with these switches being used exclusively under faulty states. The structure utilizes three DC sources with per unit magnitudes of 0.5, 1, and 1, respectively. The structure can generate an 11-level output voltage waveform, with five levels each of positive and negative polarity, respectively, and a zero level. The switching strategy under healthy operation is described in Table 1, and the corresponding conduction diagram is presented in Figure 2. The ratio of the magnitude of the dc sources is as V2 = Vdc and V1 = 0.5Vdc. The total standing voltage (TSV) of the structure is 20Vdc, with the per-unit TSV having a magnitude of 20/2.5 = 8Vdc.

Fault-Tolerant Strategy
The modulation scheme must be reconfigured after an open-circuit fault is detected on any of the switches to sustain operation with acceptable output power quality and THD. The strategy for faults across individual switches is given in Table 2. The opencircuit fault can result in a reduced output power rating due to the loss of the peak level ±5Vdc in particular cases. The blocking voltages of the switches are given as The total TSV (total standing voltage) of the structure calculated as the sum of individual maximum blocking voltages is obtained as 18Vdc, with the per-unit TSV having a magnitude of 18/2.5 = 7.2Vdc. The switch voltage stresses do not increase post-fault and remain at their healthy condition or lower values.

Fault-Tolerant Strategy
The modulation scheme must be reconfigured after an open-circuit fault is detected on any of the switches to sustain operation with acceptable output power quality and THD. The strategy for faults across individual switches is given in Table 2. The open-circuit fault can result in a reduced output power rating due to the loss of the peak level ±5V dc in particular cases.  4 ±V 2 , ±(V 1 + V 2 ), zero ±(V 2 + V 1 ) S 5 or S 6 ±V 2 , ± 2V 2 , zero The blocking voltages of the switches are given as The total TSV (total standing voltage) of the structure calculated as the sum of individual maximum blocking voltages is obtained as 18V dc , with the per-unit TSV having a magnitude of 18/2.5 = 7.2V dc . The switch voltage stresses do not increase post-fault and remain at their healthy condition or lower values.

Modulation Strategy
Implementing a low-frequency modulation technique effectively reduces voltage transients, snubber requirements, switching losses and has a positive effect on the reliability of the inverter [33]. Selective harmonic elimination (SHE-PWM) and nearest level control (NLC-PWM) are two techniques based on low frequency modulation. SHE is better at reducing the filter size by mitigating the lower order harmonics, but it requires solving complex transcendental equations which is computationally intensive. Moreover, the closed-loop implementation of NLC-PWM is simpler. This work uses NLC-PWM in light of the above issues. The switching angles θ i [34,35] are calculated using: where MI stands for the modulation index with i = 1,2, . . . (N − 1)/2 (N = number of levels). The modulation index MI is equal to Post-fault, modulation is reconfigured to generate new switching angles to maintain the output power quality with reduced or inconsecutive levels.

1.
Fault in S 1 or S 2 or S 5 or S 6 The generation of levels ±V 1 , ± (V 1 + V 2 ), ± (2V 2 + V 1 ) cannot be sustained following a fault that occurs in this situation. The levels ±V 2 and ±2V 2 are produced post-fault. The respective conduction diagram under R-L load is shown in Figure 3. The load power rating is reduced as a result of the loss of the peak level. Modulation reconfiguration can give a satisfactory output voltage THD.

Modulation Strategy
Implementing a low-frequency modulation technique effectively reduces voltage transients, snubber requirements, switching losses and has a positive effect on the reliability of the inverter [33]. Selective harmonic elimination (SHE-PWM) and nearest level control (NLC-PWM) are two techniques based on low frequency modulation. SHE is better at reducing the filter size by mitigating the lower order harmonics, but it requires solving complex transcendental equations which is computationally intensive. Moreover, the closed-loop implementation of NLC-PWM is simpler. This work uses NLC-PWM in light of the above issues. The switching angles θi [34,35] are calculated using: where MI stands for the modulation index with i = 1,2, …(N−1)/2 (N = number of levels). The modulation index MI is equal to Post-fault, modulation is reconfigured to generate new switching angles to maintain the output power quality with reduced or inconsecutive levels.
1. Fault in S1 or S2 or S5 or S6 The generation of levels ±V1, ± (V1 + V2), ± (2V2 + V1) cannot be sustained following a fault that occurs in this situation. The levels ±V2 and ±2V2 are produced post-fault. The respective conduction diagram under R-L load is shown in Figure 3. The load power rating is reduced as a result of the loss of the peak level. Modulation reconfiguration can give a satisfactory output voltage THD.   Figure 3. Bypassing of faulted S1 by body diode and following conduction states.

Fault in S3 or S4
The levels ±V1, ±2V2, and ± (2V2 + V1) are lost in this case. The conduction diagram following this fault is given in Figure 4. Indeed, the fault leads to a similar reduction in load power rating.

Fault in S 3 or S 4
The levels ±V 1 , ±2V 2 , and ± (2V 2 + V 1 ) are lost in this case. The conduction diagram following this fault is given in Figure 4. Indeed, the fault leads to a similar reduction in load power rating.

Fault IN S7
Following a fault in S7, the levels ±V1, ±2V2 cannot be further produced. However, a fault in this location does not affect the load power rating, as the peak level ± (2V2 + V1) is preserved. The conduction diagram for this scenario is illustrated in Figure 5.

Reliability Assessment
A reliability assessment is instrumental in evaluating the robustness of a circuit towards environmental stresses and gradual degradation. It is instrumental in predicting the expected lifespan of the inverter.

Component Failure Rate Evaluation
The failure rates of various components are influenced by numerous factors, such as voltage stress, thermal behavior, environment, as described in MIL-HDBK-217F [36]. The failure rate of a semiconductor switch is derived as: λ s = λ b ×π T ×π A ×π R ×π S ×π Q ×π E (8) where the base failure rate λb is given as 0.00074. The thermal parameter πT is given by:

Fault IN S 7
Following a fault in S 7 , the levels ±V 1 , ±2V 2 cannot be further produced. However, a fault in this location does not affect the load power rating, as the peak level ±(2V 2 + V 1 ) is preserved. The conduction diagram for this scenario is illustrated in Figure 5.

Fault IN S7
Following a fault in S7, the levels ±V1, ±2V2 cannot be further produced. However, a fault in this location does not affect the load power rating, as the peak level ± (2V2 + V1) is preserved. The conduction diagram for this scenario is illustrated in Figure 5.

Reliability Assessment
A reliability assessment is instrumental in evaluating the robustness of a circuit towards environmental stresses and gradual degradation. It is instrumental in predicting the expected lifespan of the inverter.

Component Failure Rate Evaluation
The failure rates of various components are influenced by numerous factors, such as voltage stress, thermal behavior, environment, as described in MIL-HDBK-217F [36]. The failure rate of a semiconductor switch is derived as: where the base failure rate λb is given as 0.00074. The thermal parameter πT is given by:

Reliability Assessment
A reliability assessment is instrumental in evaluating the robustness of a circuit towards environmental stresses and gradual degradation. It is instrumental in predicting the expected lifespan of the inverter.

Component Failure Rate Evaluation
The failure rates of various components are influenced by numerous factors, such as voltage stress, thermal behavior, environment, as described in MIL-HDBK-217F [36]. The failure rate of a semiconductor switch is derived as: where the base failure rate λ b is given as 0.00074. The thermal parameter π T is given by: )) (9) where T J is the junction temperature of the device. The application factor π A corresponds to switching and is considered as 0.7. The power rating factor π R is given as where P r is the power rating of the switch. The voltage stress factor π S is given using where V S = V CE (applied collector to emitter voltage)/V CEO (rated collector to emitter voltage with base open). The quality factor π Q is taken as unity for JANTX specifications. The environment factor (π E ) is considered as benign ground environment with a value of unity.

Thermal Power Loss
The non-ideal behavior of switches is manifested in the form of their conduction losses and switching losses. It, in turn, elevates the junction temperature of the device, resulting in decreased reliability and efficiency. The total conduction loss in an IGBT diode module in a fundamental period can be evaluated using Equation (12).
In the preceding expression, V sw represents the ON-state switch voltage drop, R s stands for the ON-state switch resistance; similar terms are denoted for the diode D. The module current is given by i(t). Further, the switching losses in the module can be computed by the following equations: (13) Here, N ON k and E ON k are taken as the number of transitions to OFF states and the associated energy loss, respectively, for the kth device, with the second term for ON transitions. The fundamental frequency is being denoted by f. The total thermal losses as an algebraic sum of the average conduction and switching losses is given by: The Foster thermal model was compiled in the PLECS environment. Figures 6 and 7, respectively, denote the thermal description of the IGBT module IKW20N60H3 implemented. Heat sinks with reduced thermal resistances are not added. To simulate a worst-case scenario, the junction-to-ambient thermal resistance of the IGBT module itself is implemented for analysis. Following the thermal model, the π R and π T values are obtained.

Reliability Evaluation
The different failure rate parameters, and hence the failure rates of the various switches, are computed and are described in Table 3. The reliability function of the inverter under any switch open-circuit faults is evaluated using the following result: The first term in the expression is for the healthy operation of the topology. The second term is for the case of post-fault in either of S1/S2. The third term of the equation represents conditions after a fault in S3/S4. Similarly, the third term of the equation represents a fault in one of S5/S6. The equation's fourth term represents a fault in S7. In a situation where there is no fault management, the reliability of the inverter is substantially suppressed, as predictable by Equation (16).

Reliability Evaluation
The different failure rate parameters, and hence the failure rates of the various switches, are computed and are described in Table 3. The reliability function of the inverter under any switch open-circuit faults is evaluated using the following result: The first term in the expression is for the healthy operation of the topology. The second term is for the case of post-fault in either of S1/S2. The third term of the equation represents conditions after a fault in S3/S4. Similarly, the third term of the equation represents a fault in one of S5/S6. The equation's fourth term represents a fault in S7. In a situation where there is no fault management, the reliability of the inverter is substantially suppressed, as predictable by Equation (16).

Reliability Evaluation
The different failure rate parameters, and hence the failure rates of the various switches, are computed and are described in Table 3. The reliability function of the inverter under any switch open-circuit faults is evaluated using the following result: The first term in the expression is for the healthy operation of the topology. The second term is for the case of post-fault in either of S1/S2. The third term of the equation represents conditions after a fault in S 3 /S 4 . Similarly, the third term of the equation represents a fault in one of S 5 /S 6 . The equation's fourth term represents a fault in S 7 . In a situation where there is no fault management, the reliability of the inverter is substantially suppressed, as predictable by Equation (16).
The distinction of reliability between fault management and its lack thereof can be visualized in Figure 8. The distinction of reliability between fault management and its lack thereof can b visualized in Figure 8.

Comparative Analysis
In this section, the proposed topology is assessed competitively concerning fault-tol erant MLIs mentioned the in recent literature. Multiple parameters for assessment includ the number of DC sources, power semiconductor switches, and levels generated. Th comparison can be visualized using Table 4. The proposed topology shows advantages in terms of per-unit level device utilization and component requirements with the additiona benefit of improved reliability. The literature works compared with the proposed topol ogy include [16][17][18][37][38][39][40][41]. While the DC source requirement in [18,39] are same as th proposed topology, still they can produce only seven level output voltage. The topologie presented in [17,38,40,41] utilizes two DC sources, but they can only produce a maximum level of 5, 5, 7, and 9 respctively. Moreover, although the switch requirement in [17,[37][38][39][40] is less compared to proposed topology, the ouptut voltage levels generated are also quit a bit lower. Comparison with a CHB topology with DC sources ±Vdc, ±2Vdc, ±2Vdc is also included. The CHB topology exhibits only partial fault tolerance in terms of post-faul peak level availability and reduced performance in case of faults in multiple switche while requiring 12 active IGBTs compared to 8, as in the case of the proposed topology Consider a three-CHB with DC sources ±Vdc, ±2Vdc, ±2Vdc. The proposed topology can continue to produce a five-level output of 0, ±2Vdc, ±4Vdc in the event of both S1-S2, both S5-S6, and even all four S1, S2, S5, and S6 simultaneous failure by employing the redundan switches S8 and S9, while the loss of four switches will catastrophically affect th performance of the CHB inverter. Moreover, only eight IGBTs are active in the proposed topology during healthy conditions, and the other four are redundant, which results in higher reliability than the three-CHB inverter comprising 12 active IGBTs.

Comparative Analysis
In this section, the proposed topology is assessed competitively concerning faulttolerant MLIs mentioned the in recent literature. Multiple parameters for assessment include the number of DC sources, power semiconductor switches, and levels generated. The comparison can be visualized using Table 4. The proposed topology shows advantages in terms of per-unit level device utilization and component requirements with the additional benefit of improved reliability. The literature works compared with the proposed topology include [16][17][18][37][38][39][40][41]. While the DC source requirement in [18,39] are same as the proposed topology, still they can produce only seven level output voltage. The topologies presented in [17,38,40,41] utilizes two DC sources, but they can only produce a maximum level of 5, 5, 7, and 9 respctively. Moreover, although the switch requirement in [17,[37][38][39][40] is less compared to proposed topology, the ouptut voltage levels generated are also quite a bit lower. Comparison with a CHB topology with DC sources ±V dc , ±2V dc , ±2V dc is also included. The CHB topology exhibits only partial fault tolerance in terms of post-fault peak level availability and reduced performance in case of faults in multiple switches while requiring 12 active IGBTs compared to 8, as in the case of the proposed topology. Consider a three-CHB with DC sources ±Vdc, ±2V dc , ±2V dc . The proposed topology can continue to produce a five-level output of 0, ±2V dc , ±4V dc in the event of both S 1 -S 2 , both S 5 -S 6 , and even all four S 1 , S 2 , S 5 , and S 6 simultaneous failure by employing the redundant switches S 8 and S 9 , while the loss of four switches will catastrophically affect the performance of the CHB inverter. Moreover, only eight IGBTs are active in the proposed topology during healthy conditions, and the other four are redundant, which results in higher reliability than the three-CHB inverter comprising 12 active IGBTs.

Fault Detection
The proposed fault detection technique involves the acquisition of the mean load voltage and Root Mean Square (RMS) load voltage supplied by the MLI. The detection problem is a Multiclass Classification problem in machine learning, with fault location as the output and mean and RMS voltages as inputs. Various supervised learning classification algorithms have been developed, namely expert systems, linear regression, artificial neural networks (ANNs), a support vector machine (SVM), k-nearest neighbour (KNN), fuzzy logic, and decision trees (DTs). This work implements a decision tree model for the classification problem. DTs are one of the most versatile and popular models which can perform both classification and regression. A decision tree is in the structure of a tree, where each feature is represented as a node. A decision rule is represented as a branch (link), and each leaf classifies the output. The structure of a DT is depicted in Figure 9. The basic principle involves asking a series of true/false questions or decisions. Data are further categorized across every step. Each branch corresponds to a result of the test. Each leaf node assigns a classification of the output. DTs often mimic the human thinking flow, making them simple to understand and they help one in interpreting the implications of the data. The three steps performed are dataset preparation, training, and testing.

Fault Detection
The proposed fault detection technique involves the acquisition of the mean load voltage and Root Mean Square (RMS) load voltage supplied by the MLI. The detection problem is a Multiclass Classification problem in machine learning, with fault location as the output and mean and RMS voltages as inputs. Various supervised learning classification algorithms have been developed, namely expert systems, linear regression, artificial neural networks (ANNs), a support vector machine (SVM), k-nearest neighbour (KNN), fuzzy logic, and decision trees (DTs). This work implements a decision tree model for the classification problem. DTs are one of the most versatile and popular models which can perform both classification and regression. A decision tree is in the structure of a tree, where each feature is represented as a node. A decision rule is represented as a branch (link), and each leaf classifies the output. The structure of a DT is depicted in Figure 9. The basic principle involves asking a series of true/false questions or decisions. Data are further categorized across every step. Each branch corresponds to a result of the test. Each leaf node assigns a classification of the output. DTs often mimic the human thinking flow, making them simple to understand and they help one in interpreting the implications of the data. The three steps performed are dataset preparation, training, and testing.

Decision node
Decision node

Decision node Leaf node
Leaf node Leaf node Leaf node Leaf node Branch Figure 9. Structure of proposed multilevel inverter topology.
Assuming training vectors ∈ , = 1, … with a label vector ∈ , the functioning of a decision tree involves recursively partitioning the features such that identically labelled or similar target outputs are aggregated together. Consider the data composed of Nm samples at node m and symbolised by Qm. A split = ( , ) with j and tm as the feature and partition, respectively, partitions the data into the subsets ( ) and ℎ ( ).
The obtained candidate split is verified by its quality using a loss function H(), Assuming training vectors x i ∈ R n , i = 1, . . . l with a label vector y ∈ R l , the functioning of a decision tree involves recursively partitioning the features such that identically labelled or similar target outputs are aggregated together. Consider the data composed of N m samples at node m and symbolised by Q m . A split θ = (j, t m ) with j and t m as The obtained candidate split is verified by its quality using a loss function H(), The impurity minimisation is performed by the following parameter: Recursion is performed for the subsets Q le f t m (θ * ) and Q right m (θ * ) until the maximum allowable depth is achieved that is N m < min samples or N m = 1. For a classification application implementing 0 . . . (K − 1) outputs for node m, assume that the proportions of class k outputs in node m given by Then, the loss function corresponding to the Gini classification index is given by

Dataset Preparation
The mean and RMS values are acquired and are used as input to the model. Multiple inputs are obtained by varying the DC source voltages by 0%, ±1%, ±2%, ±5%, and ±10% to account for variations in load and dynamic behavior. Moreover, the above procedure is repeated for modulation indexes of 1, 0.9, 0.8, 0.7, 0.6, and 0.5. Distinct values across these parameters are obtained for fault in all seven switches and healthy operation. This gives a total of 432 input datasets, of which 75% are used for training the model. Selected sample datasets are displayed in Table 5 for S 3 fault conditions. A plot of the total dataset obtained is shown in Figure 10. Classification 1 to 7 is used for respective faults in switches, with '0 for no fault. to account for variations in load and dynamic behavior. Moreover, the above procedure is repeated for modulation indexes of 1, 0.9, 0.8, 0.7, 0.6, and 0.5. Distinct values across these parameters are obtained for fault in all seven switches and healthy operation. This gives a total of 432 input datasets, of which 75% are used for training the model. Selected sample datasets are displayed in Table 5 for S3 fault conditions. A plot of the total dataset obtained is shown in Figure 10. Classification 1 to 7 is used for respective faults in switches, with '0′ for no fault.

Training
The training was implemented on a Colab TM computational environment using the Python Scikit-learn library. Gini index classification was used as a metric. The importance of the features can be visualized in Figure 11. Observably, the mean voltage is a more important feature than the RMS values. The obtained decision tree structure is shown in Figure 12. The tree has 39 nodes and 38 branches with eight leaf nodes determining the fault location as the output. The training was implemented on a Colab TM computational environment using the Python Scikit-learn library. Gini index classification was used as a metric. The importance of the features can be visualized in Figure 11. Observably, the mean voltage is a more important feature than the RMS values. The obtained decision tree structure is shown in Figure 12. The tree has 39 nodes and 38 branches with eight leaf nodes determining the fault location as the output.

Testing and Results
After training, testing was carried out to verify the performance of the prediction model. The Confusion matrix obtained post-training is given as: The diagonal values are the correct predictions, and the non-diagonal elements are false positives and false negatives. As a result, the testing accuracy as a ratio of the number of correct predictions and total predictions was approximately 98.14%. An error of 1.86% is within satisfactory ranges for load and modulation index variation. Thus, the model can predict open-circuit fault locations with acceptable accuracy and low computational and hardware requirements. The trained classification model was implemented in the MATLAB-Simulink environment for fault detection on the inverter model. The obtained simulation results are given in Figure 13. The simulation results indicate that the fault is detected within one fundamental period.
The method can also be expanded for multiple switch faults. The advantages of the given method include the requirement of only two measured signals, mean and RMS voltage, from the inverter, thus requiring minimal additional sensor and signal processing hardware requirements. Thus, the proposed method can work with minimal cost and complexity.

Testing and Results
After training, testing was carried out to verify the performance of the prediction model. The Confusion matrix obtained post-training is given as: The diagonal values are the correct predictions, and the non-diagonal elements are false positives and false negatives. As a result, the testing accuracy as a ratio of the number of correct predictions and total predictions was approximately 98.14%. An error of 1.86% is within satisfactory ranges for load and modulation index variation. Thus, the model can predict open-circuit fault locations with acceptable accuracy and low computational and hardware requirements. The trained classification model was implemented in the MATLAB-Simulink environment for fault detection on the inverter model. The obtained simulation results are given in Figure 13. The simulation results indicate that the fault is detected within one fundamental period.
The method can also be expanded for multiple switch faults. The advantages of the given method include the requirement of only two measured signals, mean and RMS voltage, from the inverter, thus requiring minimal additional sensor and signal processing hardware requirements. Thus, the proposed method can work with minimal cost and complexity.

Simulation Results
The operation of the proposed topology was verified in the MATLAB-Simulink TM R2016b environment on an Intel ® Core TM i5-3210M 2.50 GHz platform. The simulation parameters are listed in Table 6. Results under both normal and faulty operation are presented with the execution of the NLC-PWM modulation control. The load voltage and load current waveform and their respective harmonic profiles are given in Figure 14. The load voltage, load current, and the switch current waveforms in the scenario of S1/S2 or S5/S6 fault are shown in Figure 15. Similarly, the corresponding waveforms for faults in S3/S4 and S7 are shown in Figures 16 and 17, respectively.

Simulation Results
The operation of the proposed topology was verified in the MATLAB-Simulink TM R2016b environment on an Intel ® Core TM i5-3210M 2.50 GHz platform. The simulation parameters are listed in Table 6. Results under both normal and faulty operation are presented with the execution of the NLC-PWM modulation control. The load voltage and load current waveform and their respective harmonic profiles are given in Figure 14. The load voltage, load current, and the switch current waveforms in the scenario of S 1 /S 2 or S 5 /S 6 fault are shown in Figure 15. Similarly, the corresponding waveforms for faults in S 3 /S 4 and S 7 are shown in Figures 16 and 17, respectively.       Figure 17. Simulation voltage and current waveforms under S7 fault.

Experimental Verification
The operation of the proposed topology was verified through a hardware prototype depicted in Figure 18 using NLC (nearest level control) at 50 Hz fundamental frequency with Table 7 parameters. IGBTs IGB20N60H3 were used as switches. TMS320F28335 was used as the controller while TLP250H gate drivers were implemented. The output waveforms were displayed in a Yokogawa DL1640 oscilloscope. A total input DC source voltage of 50 V with V1 = 10 V and V2 = 20 V was fed to the module. An EN50160 power analyzer was used to determine the harmonic distortion in the load voltage waveforms. A load of 20 Ω + 50 mH was connected at the output. The output waveforms for S1 open-circuit fault for modulation indexes MI = 1 and MI = 0.7 are given in Figure 19. Similarly, the output waveforms for S3 fault and S7 fault are given in Figures 20 and 21, respectively. The fault-tolerant operation was successful, even with the variation of MI. Moreover, the waveform distortion arising from the open-circuit fault was corrected in one fundamental period. The harmonic spectrum of load voltages for healthy conditions, S1 post-fault, S3 post-fault, and S7 post-fault, are given in Figure 22. Observably, the THD is higher post-fault but is at acceptable values and can be supplied to critical loads with low filter requirements.

Experimental Verification
The operation of the proposed topology was verified through a hardware prototype depicted in Figure 18 using NLC (nearest level control) at 50 Hz fundamental frequency with Table 7 parameters. IGBTs IGB20N60H3 were used as switches. TMS320F28335 was used as the controller while TLP250H gate drivers were implemented. The output waveforms were displayed in a Yokogawa DL1640 oscilloscope. A total input DC source voltage of 50 V with V 1 = 10 V and V 2 = 20 V was fed to the module. An EN50160 power analyzer was used to determine the harmonic distortion in the load voltage waveforms. A load of 20 Ω + 50 mH was connected at the output. The output waveforms for S 1 opencircuit fault for modulation indexes MI = 1 and MI = 0.7 are given in Figure 19. Similarly, the output waveforms for S 3 fault and S 7 fault are given in Figures 20 and 21, respectively. The fault-tolerant operation was successful, even with the variation of MI. Moreover, the waveform distortion arising from the open-circuit fault was corrected in one fundamental period. The harmonic spectrum of load voltages for healthy conditions, S 1 post-fault, S 3 post-fault, and S 7 post-fault, are given in Figure 22. Observably, the THD is higher post-fault but is at acceptable values and can be supplied to critical loads with low filter requirements.  Figure 17. Simulation voltage and current waveforms under S7 fault.

Experimental Verification
The operation of the proposed topology was verified through a hardware prototype depicted in Figure 18 using NLC (nearest level control) at 50 Hz fundamental frequency with Table 7 parameters. IGBTs IGB20N60H3 were used as switches. TMS320F28335 was used as the controller while TLP250H gate drivers were implemented. The output waveforms were displayed in a Yokogawa DL1640 oscilloscope. A total input DC source voltage of 50 V with V1 = 10 V and V2 = 20 V was fed to the module. An EN50160 power analyzer was used to determine the harmonic distortion in the load voltage waveforms. A load of 20 Ω + 50 mH was connected at the output. The output waveforms for S1 open-circuit fault for modulation indexes MI = 1 and MI = 0.7 are given in Figure 19. Similarly, the output waveforms for S3 fault and S7 fault are given in Figures 20 and 21, respectively. The fault-tolerant operation was successful, even with the variation of MI. Moreover, the waveform distortion arising from the open-circuit fault was corrected in one fundamental period. The harmonic spectrum of load voltages for healthy conditions, S1 post-fault, S3 post-fault, and S7 post-fault, are given in Figure 22. Observably, the THD is higher post-fault but is at acceptable values and can be supplied to critical loads with low filter requirements.  Figure 18. Experimental setup. Figure 18. Experimental setup.  Figure 19. Experimental voltage and current waveforms under S1 fault.

Conclusions
In this paper, an asymmetric multilevel inverter topology is introduced. The fault tolerance of the proposed topology against switch open-circuit faults due to gating failure is verified through simulation results. Reliability analysis of the topology is presented to illustrate the advantage of fault tolerance. The topology is compared against previous works in terms of device count and other parameters to demonstrate its superiority. Additionally, a fault detection strategy using the supervised machine learning technique decision trees is put forth. The fault localization model inputs the load mean voltage and its RMS as diagnostic variables and outputs the fault location. The testing results demonstrate that the classification model successfully detects the fault location with an accuracy of 0.981481. Therefore, the fault detection strategy can be expanded to a real-time system in the future with low computational requirements and minimal additional hardware.

Conclusions
In this paper, an asymmetric multilevel inverter topology is introduced. The fault tolerance of the proposed topology against switch open-circuit faults due to gating failure is verified through simulation results. Reliability analysis of the topology is presented to illustrate the advantage of fault tolerance. The topology is compared against previous works in terms of device count and other parameters to demonstrate its superiority. Additionally, a fault detection strategy using the supervised machine learning technique decision trees is put forth. The fault localization model inputs the load mean voltage and its RMS as diagnostic variables and outputs the fault location. The testing results demonstrate that the classification model successfully detects the fault location with an accuracy of 0.981481. Therefore, the fault detection strategy can be expanded to a real-time system in the future with low computational requirements and minimal additional hardware.