Improvement of DC Fault Current Limiting and Interrupting Operation of Hybrid DC Circuit Breaker Using Double Quench

: In this paper, direct current (DC) fault current limiting and interrupting operation of hybrid DC circuit breaker (DCCB) using double quench, which consists of DCCB, a series resonance circuit, power electronic switch, surge arrestor, two separated current limiting reactor/resistor, and two superconducting elements, were suggested. The suggested hybrid DCCB can perform the interrupting operation after twice or once DC fault current limiting operation according to DC fault current amplitude. To verify the effective operation of the suggested hybrid DCCB, the modeling for the components of DCCB, the surge arrestor, and the SCE was carried out and its DC operational characteristics were analyzed. Through the analysis of the modeling results for the suggested hybrid the advantages of hybrid DCCB were discussed.


Introduction
Recently, direct current (DC) grid, called as low voltage DC (LVDC), medium voltage DC (MVDC), or high voltage DC (HVDC) system, has been receiving attention due to the increase of DC load and DC distributed power source and thus the various protection devices for DC grid such as DC circuit breaker (DCCB) have been developed. One of the important technologies in DCCBs is that the increased DC current is to make rapid zero crossings. Another one is to effectively remove the arc in mechanic contact comprising the DCCB. To achieve these technologies in DCCB, the hybrid DCCBs or the modified DCCBs, which utilize the power electronic switches with higher ratings, have been introduced continuously [1][2][3][4][5].
Moreover, the DCCBs, which can achieve the fault current limiting operation shortly before the fault current interruption, have been suggested and the improvement of the DCCB's performance through the combination of the superconducting elements (SCEs) has been constantly reported [6][7][8][9][10].
In this paper, the hybrid DCCB using double quench of SCEs, which has a mechanical switch (MS), power electronic switch (PS), two SCEs, and two separated current limiting reactor/resistor (CLRs), were proposed and the effect of twice DC fault current limiting operations according to the amplitude of DC fault current on the interrupting operation of the DCCB was analyzed through the PSCAD/EMTDC (power system computer-aided design/electro-magnetic transient including direct current) simulation.
With the PSCAD/EMTDC modeling for the mathematical characteristic equation of each component, the double quench generation of the SCEs comprising the hybrid DCCB was confirmed to be contributed to the successful DC fault current interruption along with twice DC fault current limiting operation through the comparative analysis with the case of the hybrid DCCB without two SCEs and two separated CLRs. The structure of the hybrid DCCB using double quench consists of two CLRs and two SCEs as DC current limiting components, MS, LC series circuit and PS as DC current interrupting components, and surge arrestor (SA) as overvoltage prevention as shown in Figure 1. The series resonance circuit has a parallel connection with MS to induce zero current crossings in MS in case of the DC fault current occurrence. PS, connected in series the controller. The SCE 1 acts as both the fault detector and the initial DC fault current limiter. The quench occurrence in SCE 1 directly after the fault happens makes the CLR 1 act as the first fault current limiter through SCE 2 . In case that the larger DC fault current flows into SCE 2 despite the quench occurrence of the SCE 1 , the quench in SCE 2 occurs sequentially and the second DC fault current limiting operation of the hybrid DCCB can be achieved. After the DC fault current limiting operation through single quench in SCE 1 or double quench in both SCE 1 and SCE 2 comprising the hybrid DCCB according to the amplitude of the DC fault current, the DC fault current interrupting operation through the MS is achieved by its opening operation and then, finally separated from the DC fault current path by the opening of PS. The SA pre-vents the over-voltage across the DCCB during the DC current limiting and the interrupting operation. The structure of the hybrid DCCB using double quench consists of two CLRs and two SCEs as DC current limiting components, MS, LC series circuit and PS as DC current interrupting components, and surge arrestor (SA) as overvoltage prevention as shown in Figure 1. The series resonance circuit has a parallel connection with MS to induce zero current crossings in MS in case of the DC fault current occurrence. PS, connected in series the controller. The SCE1 acts as both the fault detector and the initial DC fault current limiter. The quench occurrence in SCE1 directly after the fault happens makes the CLR1 act as the first fault current limiter through SCE2. In case that the larger DC fault current flows into SCE2 despite the quench occurrence of the SCE1, the quench in SCE2 occurs sequentially and the second DC fault current limiting operation of the hybrid DCCB can be achieved. After the DC fault current limiting operation through single quench in SCE1 or double quench in both SCE1 and SCE2 comprising the hybrid DCCB according to the amplitude of the DC fault current, the DC fault current interrupting operation through the MS is achieved by its opening operation and then, finally separated from the DC fault current path by the opening of PS. The SA pre-vents the over-voltage across the DCCB during the DC current limiting and the interrupting operation.

Modeling of Hybrid Direct Current Circuit Breaker (DCCB) Using Double Quench
To analyze the current limiting and the interrupting characteristics, the PSCAD/EMTDC modeling for the suggested hybrid DCCB using a double quench of two SCEs was carried out. MS, SCE, and SA were considered as the main modeling components.

Modeling of Hybrid Direct Current Circuit Breaker (DCCB) Using Double Quench
To analyze the current limiting and the interrupting characteristics, the PSCAD/EMTDC modeling for the suggested hybrid DCCB using a double quench of two SCEs was carried out. MS, SCE, and SA were considered as the main modeling components.
For the MS's dynamic arc behavior, the arc conductance (GMS) was reflected into the PSCAD/EMTDC modeling from Mayr's arc model as expressed in Equation (1) and modeled to generate directly after the MS current (i MS ) exceeded 8 kA. In Equation (1), G 0 , Q 0 , and τ a represent the conductance of insulation material between two conducting plates, Energies 2021, 14, 4157 3 of 11 the heat energy, and the time constant of arc, respectively [11,12]. The resistance of each SCE, which generates in case that the current in SCM (i SCM1 , i SCM2 ) exceeds the critical current (I C1 , I C2 ), was reflected into its PSCAD/EMTDC modeling with the resistance equation, represented in Equation (2). R N and τ b in Equation (2) express the normal resistance and time constant of SCE, respectively [13,14].
In addition, the PSCAD/EMTDC modeling for the SA was considered with the resistance of Equation (3) derived from its voltage and current relation with the breakdown voltage (V B ) and the nonlinear index (γ) [15]. The current in the MS (i MS ) directly after the DC fault occurrence can be obtained as Equation (5) from the second differential equation for the current of the MS (i MS ) as shown in Equation (4). In Equations (5) and (6), n and k represent the cycle number of the zero current point in the current of MS and the ratio of the voltage variation induced in the MS (∆v MS ) over the current variation of MS (∆i MS ), respectively.
To verify the merits of the suggested hybrid DCCB using double quench, the simulated DC system was constructed as shown in Figure 2. The specifications for the simulated DC system were listed in Table 1. For DC short-circuit simulation with different amplitude of DC fault current, SW 21 or SW 22 was closed individually for 0.01 s for larger DC fault current and lower DC fault current after SW 1 was closed. The values of the parameters, described in the modeling of MS, SCE 1 , SCE 2 , and SA comprising the hybrid DCCB, were listed in Table 2 together with CLR 1 , CLR 2 , and series resonance circuit.

Results and Discussion
The improvement of the DC current limiting and interrupting operations of the suggested hybrid DCCB was analyzed from the simulation results for the larger DC fault current and the lower DC fault current situations. Figure 3 shows the DC fault current limiting and interrupting operation of the suggested hybrid DCCB in case of the larger DC fault current occurrence. With the arc conductance in Equation (1) calculated using the voltage and the current of the MS, the voltage (v MS ) and the current (i MS ) of the MS were displayed in Figure 3b,c, respectively.
The fault starting time is indicated with t 1 in Figure 3. After t 1 , the time for the current of the SCE 1 (i SCE1 ) to arrive at the critical current (I C1 ) is marked with t C1 . After that time, the voltage of the MS sharply increases and the arc starting time is notated with t Arc as seen in Figure 3b. As t Arc , the current of the MS (i MS ) as seen in Figure 3c increases with the parabola form together with the resonance due to the LC series resonance circuit. Though the increase of the MS's current, the current in the SCE 1 (i SCE1 ) due to its quench occurrence decreases, which makes the current in the SCE 2 (i SCE2 ) or the CLR 1 (i CLR1 ) increase on the other way. The increased current of the SCE 2 is observed to approach its critical current (I C2 ) at t C2 . The decrease of the SCE 2 s current due to its quench occurrence again causes the current of the CLR 2 to be increased as seen in Figure 3a. Through twice or double quench occurrence in two SCEs and the series resonance, the current of the MS (i MS ) smoothly increases with the series resonance frequency due to the series LC circuit and then, approaches the zero current point at t SA . On the other hand, the voltage of the DCCB (v DCCB ) sharply starts to increase at the moment of the zero current point and exceeds the breaking voltage (V B ) as seen in Figure 3b. However, the operation of the surge arrestor, as seen in the current occurrence of the surge  The fault starting time is indicated with t1 in Figure 3. After t1, the time for the current of the SCE1 (iSCE1) to arrive at the critical current (IC1) is marked with tC1. After that time, the voltage of the MS sharply increases and the arc starting time is notated with tArc as seen in Figure 3b. As tArc, the current of the MS (iMS) as seen in Figure 3c increases with the parabola form together with the resonance due to the LC series resonance circuit. Though the increase of the MS's current, the current in the SCE1 (iSCE1) due to its quench occurrence decreases, which makes the current in the SCE2 (iSCE2) or the CLR1 (iCLR1) increase on the other way. The increased current of the SCE2 is observed to approach its critical current (IC2) at tC2. The decrease of the SCE2′s current due to its quench occurrence again causes the current of the CLR2 to be increased as seen in Figure 3a. Through twice or double quench occurrence in two SCEs and the series resonance, the current of the MS (iMS) smoothly increases with the series resonance frequency due to the series LC circuit and then, approaches the zero current point at tSA. On the other hand, the voltage of the DCCB (vDCCB) sharply starts to increase at the moment of the zero current point and exceeds the breaking voltage (VB) as seen in Figure 3b. However, the operation of the surge arrestor, as seen in the current occurrence of the surge arrestor (iSA) from Figure 3a, is confirmed to be contributed to suppressing the overvoltage of the DCCB.
After the MS opens, the current of the SCM1 (iSCE1) starts to decrease with the amplitude of the resonance frequency due to the series LC resonance circuit and then, finally approaches to zero value at t2. In the end, the current of DCCB of the hybrid DCCB reaches zero value at t3 as seen in Figure 3a. After the MS opens, the current of the SCM 1 (i SCE1 ) starts to decrease with the amplitude of the resonance frequency due to the series LC resonance circuit and then, finally approaches to zero value at t 2 . In the end, the current of DCCB of the hybrid DCCB reaches zero value at t 3 as seen in Figure 3a.
For the comparative analysis with the hybrid DCCB without the SCMs and the CLRs, the currents of the DCCB and the MS (i DCCB w/o , i MS w/o ) and the voltage of the MS (v MS w/o ) were included in Figure 3. As seen in Figure 3, the MS in the case of the hybrid DCCB without the SCMs and the CLRs can be seen to be not open or fail to be open.
In the case of the lower DC fault current occurrence, which was simulated by closing SW 22 after SW 1 was closed as shown in Figure 2, the DC fault current limiting and interrupting operations of the suggested hybrid DCCB were displayed in Figure 4. Both the time (t C1 ) for the current of the SCE 1 (i SCE1 ) to arrive at the critical current (I C1 ) and the time (t Arc ) for the voltage of the MS (v MS ) rapidly to start to increase is seen to be a little longer compared to the larger DC fault current occurrence as analyzed in Figure 3. Furthermore, the second fault current limiting operation did not happen since the current of the SCE 2 (i SCE2 ) did not exceed its critical current (I C2 ) as seen in Figure 4a. After t Arc , the current in the MS (i MC ), which kept zero value before t Arc , starts to increase with the resonance frequency of series LC circuit and then, approaches zero point at t SA by the increase of the current (i LC ) in series LC circuit as seen in Figure 4c. Simultaneously, as soon as the current of the MS approaches zero point at t SA , the voltage of the MS (v MS ), as shown in Figure 4b, exceeds the breaking voltage (V B ), and then, the current of the surge arrestor (i SA ) starts to flow as displayed in Figure 4a.
After t SA , the zero current time of the SCM 1 (t 2 ) and the zero current time of the DCCB (t 3 ) were accompanied. This time t 3 was called the complete opening time.
Due to the lower DC fault current, the voltage and current levels in components comprising the hybrid DCCB as analyzed in Figure 4 were observed to have a small scale compared to the larger DC fault current. Therefore, the complete opening time (t 3 ) in the case of the lower DC fault current occurrence seems to be shorter than the case of the larger DC fault current. To compare the hybrid DCCB without two SCMs and two separated CLRs, the DC fault current limiting and interrupting waveforms of the suggested hybrid DCCB were displayed in Figure 5 together. In the case of the larger DC fault current occurrence, as shown in Figure 5a, the complete opening operation at t 3 after the zero current in the MS through the series resonance of LC together with the twice DC fault current limiting operations of two SCMs was achieved. On the other hand, the DC fault current interrupting operation (i MS w/o , i DCCB w/o ) in the case of the hybrid DCCB without two SCMs and two CLRs was not achieved.
To compare the hybrid DCCB without two SCMs and two separated CLRs, the DC fault current limiting and interrupting waveforms of the suggested hybrid DCCB were displayed in Figure 5 together. In the case of the larger DC fault current occurrence, as shown in Figure 5a, the complete opening operation at t 3 after the zero current in the MS through the series resonance of LC together with the twice DC fault current limiting operations of two SCMs was achieved. On the other hand, the DC fault current interrupting For the comparative analysis with the hybrid DCCB without the SCMs and the CLRs, the currents of the DCCB and the MS (iDCCB w/o , iMS w/o ) and the voltage of the MS (vMS w/o ) were included in Figure 3. As seen in Figure 3, the MS in the case of the hybrid DCCB without the SCMs and the CLRs can be seen to be not open or fail to be open.
In the case of the lower DC fault current occurrence, which was simulated by closing SW22 after SW1 was closed as shown in Figure 2, the DC fault current limiting and interrupting operations of the suggested hybrid DCCB were displayed in Figure 4. Both the time (tC1) for the current of the SCE1 (iSCE1) to arrive at the critical current (IC1) and the time (tArc) for the voltage of the MS (vMS) rapidly to start to increase is seen to be a little longer compared to the larger DC fault current occurrence as analyzed in Figure 3. Furthermore, the second fault current limiting operation did not happen since the current of the SCE2 (iSCE2) did not exceed its critical current (IC2) as seen in Figure 4a. After tArc, the current in the MS (iMC), which kept zero value before tArc, starts to increase with the resonance frequency of series LC circuit and then, approaches zero point at tSA by the increase of the current (iLC) in series LC circuit as seen in Figure 4c.   rated CLRs, the DC fault current limiting and interrupting waveforms of the suggested hybrid DCCB were displayed in Figure 5 together. In the case of the larger DC fault current occurrence, as shown in Figure 5a, the complete opening operation at t3 after the zero current in the MS through the series resonance of LC together with the twice DC fault current limiting operations of two SCMs was achieved. On the other hand, the DC fault current interrupting operation (iMS w/o , iDCCB w/o ) in the case of the hybrid DCCB without two SCMs and two CLRs was not achieved.
Energies 2021, 14, x FOR PEER REVIEW 10 of 11 To compare the hybrid DCCB without two SCMs and two separated CLRs, the DC fault current limiting and interrupting waveforms of the suggested hybrid DCCB were displayed in Figure 5 together. In the case of the larger DC fault current occurrence, as shown in Figure 5a, the complete opening operation at t3 after the zero current in the MS Unlike the case of the larger DC fault current occurrence, the DC fault current interrupting operation (i MS w/o , i DCCB w/o ) without two SCMs and two CLRs in case of the lower DC fault current occurrence was observed to succeed as shown in Figure 5b, which was made to zero current by the series LC resonance. However, it is compared to take a longer time compared to the case of the hybrid DCCB using the double quench although the quench in only SCE 1 comprising the hybrid DCCB using the double quench due to the lower DC fault current occurred.

Conclusions
In this paper, the hybrid DC circuit breaker using double quench was suggested and its DC fault current limiting and interrupting operation according to DC fault current amplitude was analyzed through the PSCAD/EMTDC modeling for its components. In the case of the larger DC fault current occurrence, the DC fault current interrupting operation through zero current generation in the MS using the series resonance together with the twice DC fault current limiting operations of two SCMs was successively achieved. On the other hand, the DC fault current interrupting operation in case with the hybrid DCCB without two SCMs and two CLRs was not achieved. In case of lower DC fault current occurrence, the DC fault current interrupting operation of the suggested hybrid DCCB was also made through once DC fault current limiting operation. However, the opening time was shorter than the case of the larger DC fault current.
In the future, the studies considering the application of the suggested hybrid DCCB into the multi-terminal MVDC system, which requires several DCCBs with different capacities, will be in progress.