Variable-Frequency Pulse Width Modulation Circuits for Resonant Wireless Power Transfer

: In this paper, we develop a variable-frequency pulse width modulation (VFPWM) circuit for input control of 6.78-MHz resonant wireless power transfer (WPT) systems. The zero-voltage switching control relies on the adjustments of both duty cycle and switching frequency for the class-E ampliﬁer used in the WPT as the power transmission unit. High-frequency pulse wave modulation integrated circuits exist, but some have insufﬁciently high frequency or unfavorable resolution for duty cycle tuning. The novelty of this work is the VFPWM circuit design that we put together. A voltage-controlled oscillator (VCO) of radio frequency and capacitor-coupled difference ampliﬁers are used to simultaneously perform the frequency and duty cycle tuning required in resonant WPT applications. Different circuit topologies of VFPWM are compared analytically and numerically. The most favorable circuit topology, enabling independent control of the frequency and duty cycle, is employed in experiments. The experimental results demonstrate the validity of the novel VFPWM, which is capable of operating at 6.78-MHz and has a duty ratio adjustable from 20% to 45% of the range applicable in the resonant WPT applications.


Introduction
Wireless power transfer (WPT) [1] offers a novel means of delivering energy from a power source to a target load through the air instead of the wire that is conventionally used for electricity-powered devices. The WPT method has excellent flexibility and noncontact characteristics. In the near future, it will be an ideal technical solution for powering electrical equipment in various applications within certain fields; for example, it will be ideal for portable electronic devices, implantable medical devices, integrated circuits (ICs), solar-powered satellites, electric vehicles, and unmanned aerial vehicles. Inductive power transfer (IPT) is based on the changing magnetic field generated by alternating currents in the primary coil when the voltage and current induced through the air gap in the secondary coil. IPT is the most widely used WPT technology.
The class-E power amplifier [2,3] is simple and highly efficient in WPT applications, providing an additional degree of design freedom that enables optimal WPT operation over a wide range of operating conditions [4]. However, class-E power amplifiers still suffer from sensitivity to the changes in load impedance values due to changing distance from the receiver to the transmitter or changes in the orientation of the receiver. Compensation methods include replacing the capacitor on the receiver side and adjusting the switching frequency, as proposed in [3], controlling the duty cycle and the DC feed inductance, as proposed in [5,6], and implementing a voltage-controlled capacitor and a NIC (Negative Impedance Converter), as proposed in [7]. High efficiency can be achieved by applying zero-voltage switching (ZVS) and zero-current switching (ZCS) by monitoring and tuning the inductive link dynamically. The ZVS produces soft switching at a switching frequency in the megahertz range. Furthermore, the impedance matching approach [8], charging/discharging the ultra-capacitor bank [9], and regulating the self/mutual inductance [10] are useful for tracking the maximum efficiency and improving system stability. Class-E power amplifiers belong to the class of high-frequency, high-efficiency electronic power circuits [11,12] that simultaneously consider the effects of the transistor's parasitic elements [13,14].
Class-E power amplifiers use transformers with loosely coupled windings, where the coupling coefficient k can range from 0 to 0.9. Changes in the coupling coefficient over a wide range may cause the inverter to operate under non-ZVS conditions, thereby decreasing the efficiency. The challenging task is to ensure ZVS operation over a wide range of coupling coefficients. Because operation occurs in a relatively high-frequency range, the power efficiency is limited by the switching device and the associated control scheme. Compared with silicon-based devices, GaN high-electron-mobility transistors (HEMTs) have a much lower gate charge and lower output capacitance. GaN HEMTs have excellent performance for input signals with different duty cycles, making it possible to realize high-efficiency operations and considerably improve efficiency [15,16]. The currents flowing through the magnetizing inductance and load are distributed such that the transistor operates at ZVS over a wide range of loads and coupling coefficients. The adjustable duty cycle control scheme achieves maximum power transfer in the resonant wireless power transfer system.
The pulse width modulation (PWM) duty control method is a widely used approach in IC design because digital signal processors can easily provide the required signal. However, most platforms for generating PWM signals only support applications in the tens of kilohertz range. These solutions are not suitable for applications where GaN operates in the megahertz frequency range. One means of overcoming this limitation is using a fieldprogrammable gate array (FPGA) device, which can generate high-precision PWM signals with key parameters such as duty cycle and frequency even if the operating frequency increases to tens of megahertz [17]. The main advantages of FPGA-based controllers are rapid response, precise switching, and flexible adjustment of the dead time and switching frequency. These advantages are suitable for driving numerous semiconductor-switching devices in practical applications. Tavares et al. [18] presented a static power converter developed using an FPGA platform; this converter was able to generate a PWM gating signal with a frequency reaching 2 MHz for driving GaN power field-effect transistors (FETs).
PWM is usually implemented using a voltage comparator that compares a reference voltage with a generated sawtooth signal. However, when the operating frequency increases, the comparator should complete the comparison within a few tens of nanoseconds. This causes PWM controllers based on the ramp comparator to malfunction, meaning that additional effort must be spent to adapt to megahertz operation. Digital PWM (DPWM) is implemented using a counter and comparison structure and resembles analog PWM based on sawtooth signals. The functionality is as follows: if the duty cycle command exceeds the counter value, which is equivalent to a sawtooth signal, the output is ON; when the counter reaches the duty cycle, the output turns OFF. Compared with the sequential encoding method, one-hot encoding and Gray encoding methods with fewer states are used to create varying pulses [19]. However, high resolution cannot be obtained, because the minimum time step is equal to the clock period of the counter. In addition, the power consumption is directly proportional to the clock frequency [20]. To address this issue, a delay-line-based voltage-to-duty-cycle (V2D) technique was presented that did not use any comparators. Cheng et al. [21] presented a delay-line DPWM architecture based on a phase-locked loop (PLL) and carry chain flag. This architecture had three parts: the first coarse delay module based on a counter, the second coarse delay module based on a PLL, Energies 2021, 14, 3656 3 of 25 and the fine delay module based on a carry chain. The main purpose is to compensate for the propagation delay through the tool command language, because propagation delays in the internal logics and interconnects may increase the duty cycle, thereby affecting the regulation performance of the converter, especially when the delay is of the same magnitude as the switching period. The duty-cycle increment phenomenon caused by superposition of critical path delays affects the regulation performance of converters with a switching frequency of tens of megahertz or higher. Huang et al. [22,23] used two voltage-to-delay cells to convert the voltage difference into a delay-time difference. A charge pump was used to charge or discharge the loop filter depending on whether the feedback voltage was larger or smaller than the reference voltage. A V2D controller based on delay-line control techniques was implemented to replace the classical ramp-comparator-based V2D controller and achieve a wide duty cycle, which was employed in a digitally controlled voltage-mode buck converter. The main advantages of delay-line DPWM are high resolution and low power consumption. However, this method exhibits low linearity and non-monotonic behavior in some cases. For a class-E dc-dc converter, the accuracy of the frequency, phase, and pulse width of the signal is critical in circuit applications.
Within the similar context of delay-line DPWM, this paper proposes a PWM method enabling a switching frequency of up to 7 MHz for driving a GaN power FET. In the first stage, a voltage-controlled oscillator (VCO) is used to generate periodic square signals of variable frequency. The frequency of the output voltage can be varied using the input dc voltage. The duty cycle generator of the second stage is designed to have two functions: to generate a duty cycle of less than 50% and achieve wide range correction. This paper is organized as follows. Section 2 briefly introduces the class-E amplifier circuit and the specifications and characteristics of the GaN FET. Section 3 describes the proposed circuit and provides derivations. Then, we illustrate and simulate different capacitor-coupled difference amplifiers (CCDAs) in Section 4. The experimental results obtained to validate the duty generation circuit are provided in Section 5. Finally, the conclusions and some high-frequency GaN-based potential power applications that could take advantage of the present work are presented in Section 6.

Class-E Amplifier Circuit and the Gate Drive
The high-level block diagram for the resonant wireless power transfer system shown in Figure 1a consists of four modules, including the tuning strategy for the WPT, the xCCDA design, the VFPWM feedback control, and the class-E amplifier for wireless power transfer. The class-E amplifier as shown in Figure 1b, which consists of a VFPWM circuit that generates the switching signal to the gate drive, is used in resonant WPT applications. The nominal values of the circuit parameters on the switching power supply side (or the transmitter side) and the equivalent values on the impedance load side (or the receiver side together with the transmitter antenna) are shown in Table 1. The load impedance is simplified into a resistor R L with a capacitor C 2 . The capacitor C DS is the parasitic capacitor of the D-mode GaN HEMT. A charge pump gate drive with output voltage v GS from 0 to a negative voltage (e.g., −7 V) is used to turn the GaN HEMT on and off according to the signal v s from 5 to 0 V. The GaN HEMT, which has no body diode, is periodically switched to form a sinusoidal resonant current i 2 . In the equivalent circuit, as shown Figure 1, the power transfer efficiency (PTE) is defined as the output power on the receiver P out = i 2 v L divided by the input power on the transmitter P in = i 1 V DD . The switching of the GaN HEMT transistor M 1 , including the switching frequency and turn-on time duty, directly determines the distance and efficiency of the WPT application. The experimental layout is shown in Figure 2. In our previous paper [24], the governing equations of the ZVS control for a class-E WPT unit was derived. The ZVS and its derivative, the zerocurrent switching (ZCS), conditions are achieved by adjusting the duty cycle and resonant frequency simultaneously. In the previously published paper [25], a minimum power input control strategy was proposed, which results in the switching frequency f o and the duty cycle δ the WPT being based on empirical data or equations that can yield the optimal power transfer efficiency. and the duty cycle δ the WPT being based on empirical data or equations that can yield the optimal power transfer efficiency.
The switching frequency f o and the duty cycle δ are subsequently converted into the input voltages of the PWM generator, which consists of the VCO and capacitor-coupled difference amplifier to form a variable-frequency PWM module. The VFPWM module generates a switching signal v S to the gate driver. In Figure 1, is the zero-order hold transfer function matrix that converts the switching frequency f o and the duty cycle δ into the corresponding voltages V F and Vδ, which is described in detail in the following sections with respect to different VFPWM topologies.     The switching frequency f o and the duty cycle δ are subsequently converted into the input voltages of the PWM generator, which consists of the VCO and capacitor-coupled difference amplifier to form a variable-frequency PWM module. The VFPWM module generates a switching signal v S to the gate driver. In Figure 1, G z is the zero-order hold transfer function matrix that converts the switching frequency f o and the duty cycle δ into the corresponding voltages V F and V δ , which is described in detail in the following sections with respect to different VFPWM topologies.

Charge Pump Gate Drive
The charge pump gate drive presented by Okamoto [26] is useful in class-E amplifiers. The previous disadvantage of charge pump circuits-the leakage of current through the diode reverse saturation current-is not a problem because of the high-frequency switching. However, the class-E amplifier still suffers the effect of linking to the high voltage switching of . As illustrated in Figure 3, we first assume that is floating. The corresponding gate drive design parameters are presented in Table 1.
As shown in Figure 3, the gate drive receives the PWM signal from a PWM circuit. This PWM circuit is capable of operating at an adjustable frequency around 6.78 MHz, and the duty cycle is adjustable from 20% to 50%, meaning that the gate drive can be successfully switched to perform the WPT task. High-frequency PWM ICs such as the TI SLUS489 with the maximum frequency of 2 MHz cannot meet the required frequency of 6.78 MHz. The other commercially PWM IC, the AD9560, is a high-speed, digitally programmable pulse width modulator with an output pulse width proportional to an 8-bit data input value. The pulse width can be changed every clock cycle by up to 50 MHz. The drawbacks of this IC include the requirement of a high-speed digital processor such as the ESP8266 Wi-Fi module to fulfill the 6.78-MHz control, which means that it cannot be used in low-cost applications, and that the 8-bit resolution for the output pulse width is insufficient for resonant tuning in 6.78-MHz resonant WPT applications in practice. The purpose of this paper is to construct a low-cost, PWM, high-frequency-resolution circuit feasible for 6.78-MHz resonant WPT applications. A VCO or voltage-to-frequency converter may be useful for the frequency control needed for resonant WPT; however, the ICs are

Charge Pump Gate Drive
The charge pump gate drive presented by Okamoto [26] is useful in class-E amplifiers. The previous disadvantage of charge pump circuits-the leakage of current through the diode reverse saturation current-is not a problem because of the high-frequency switching. However, the class-E amplifier still suffers the effect of C GD linking to the high voltage switching of v DS . As illustrated in Figure 3, we first assume that v DS floating. The corresponding gate drive design parameters are presented in Table 1.
As shown in Figure 3, the gate drive receives the PWM signal from a PWM circuit. This PWM circuit is capable of operating at an adjustable frequency around 6.78 MHz, and the duty cycle is adjustable from 20% to 50%, meaning that the gate drive can be successfully switched to perform the WPT task. High-frequency PWM ICs such as the TI SLUS489 with the maximum frequency of 2 MHz cannot meet the required frequency of 6.78 MHz. The other commercially PWM IC, the AD9560, is a high-speed, digitally programmable pulse width modulator with an output pulse width proportional to an 8-bit data input value. The pulse width can be changed every clock cycle by up to 50 MHz. The drawbacks of this IC include the requirement of a high-speed digital processor such as the ESP8266 Wi-Fi module to fulfill the 6.78-MHz control, which means that it cannot be used in low-cost applications, and that the 8-bit resolution for the output pulse width is insufficient for resonant tuning in 6.78-MHz resonant WPT applications in practice. The purpose of this paper is to construct a low-cost, PWM, high-frequency-resolution circuit feasible for 6.78-MHz resonant WPT applications. A VCO or voltage-to-frequency converter may be useful for the frequency control needed for resonant WPT; however, the ICs are usually designed for a 50% duty cycle. To achieve WPT with a transmission of 100 cm and greater, such as that shown in Figure 2, adjustments to both the frequency and duty cycle are required. We require a circuit that converts the VCO signal into the variable-frequency pulse width modulation (VFPWM) wave form. In the following sections, we first introduce the difference amplifier coupled with capacitors that can convert a 50% duty cycle square wave into a PWM signal. usually designed for a 50% duty cycle. To achieve WPT with a transmission of 100 cm and greater, such as that shown in Figure 2, adjustments to both the frequency and duty cycle are required. We require a circuit that converts the VCO signal into the variable-frequency pulse width modulation (VFPWM) wave form. In the following sections, we first introduce the difference amplifier coupled with capacitors that can convert a 50% duty cycle square wave into a PWM signal.

The Minimum Power Input Control Strategy
By controlling the duty ratio δ and the switching frequency simultaneously, minimum power input control [25], which trades off the PDL (Power Delivered to Load) for the switching loss of the GaN HEMT, can be used to obtain the optimal PTE (Power Transfer Efficiency). The minimum power input control strategy, which concerns the feedback from PRU (Power Receiving Unit), consists of the following steps.
Step 1. According to the PRU feedback regarding the distance between the PTU (Power Transmitting Unit) and PRU and the power transfer requirement from the PRU, we determine the input voltage VDD. The input voltage, according to the experimental data [24], as shown in Figure 4, should be tuned to a low voltage for short-range WPT and a high voltage for long-range WPT.

The Minimum Power Input Control Strategy
By controlling the duty ratio δ and the switching frequency simultaneously, minimum power input control [25], which trades off the PDL (Power Delivered to Load) for the switching loss of the GaN HEMT, can be used to obtain the optimal PTE (Power Transfer Efficiency). The minimum power input control strategy, which concerns the feedback from PRU (Power Receiving Unit), consists of the following steps.
Step 1. According to the PRU feedback regarding the distance between the PTU (Power Transmitting Unit) and PRU and the power transfer requirement from the PRU, we determine the input voltage V DD . The input voltage, according to the experimental data [24], as shown in Figure 4, should be tuned to a low voltage for short-range WPT and a high voltage for long-range WPT. Step 2. The input power of the PTU is determined from the feedback power requirement from all PRUs. Consequently, the duty cycle δ (or duty ratio %) is determined from the input power and the given input voltage VDD from Step 1. As shown in Figure 5,  Step 2. The input power of the PTU is determined from the feedback power requirement from all PRUs. Consequently, the duty cycle δ (or duty ratio %) is determined from the input power and the given input voltage V DD from Step 1. As shown in Figure 5, which is interpolated in [25], it is observed that the duty ratio δ% increases monotonically, in general, with increasing PTU input power. Step 2. The input power of the PTU is determined from the feedback power requirement from all PRUs. Consequently, the duty cycle δ (or duty ratio %) is determined from the input power and the given input voltage VDD from Step 1. As shown in Figure 5, which is interpolated in [25], it is observed that the duty ratio δ% increases monotonically, in general, with increasing PTU input power. Step 3. From the given input voltage VDD and the duty ratio δ% calculated in step 2, we determine the switching frequency f0 according to the empirical function shown in Figure 6, which is interpolated in [25]. Step 3. From the given input voltage V DD and the duty ratio δ% calculated in step 2, we determine the switching frequency f o according to the empirical function shown in Figure 6, which is interpolated in [25].  The goal of the minimum power input control strategy is to optimize the power efficiency of the WPT system when multiple PTUs and multiple PRUs are interacting. The control strategy will calculate the best switching frequency and duty ratio % for each individual PTU.

Parameters of the Class-E Amplifier and WPT System
Two arrangements of PTU/PRU inductor settings are used in the experiments. The data were reported in [24] and are reproduced in Table 2. The distance between the PTU and the PRU, as well as the orientation of the PRU toward the PTU, affects the coupling coefficient in the wireless power transfer. The tuning of both switching frequency fo and the duty ratio δ must respond to the coupling coefficient change dynamically in order to  The goal of the minimum power input control strategy is to optimize the power efficiency of the WPT system when multiple PTUs and multiple PRUs are interacting. The control strategy will calculate the best switching frequency f o and duty ratio δ% for each individual PTU.

Parameters of the Class-E Amplifier and WPT System
Two arrangements of PTU/PRU inductor settings are used in the experiments. The data were reported in [24] and are reproduced in Table 2. The distance between the PTU and the PRU, as well as the orientation of the PRU toward the PTU, affects the coupling coefficient in the wireless power transfer. The tuning of both switching frequency f o and the duty ratio δ must respond to the coupling coefficient change dynamically in order to achieve the impedance matching condition. The nominal input/output parameters of the class-E amplifier and WPT system in this research are shown in Table 3. The nominal values are only reference values for typical 10 W and 40 cm distance resonant WPT applications.

CCDAs
Two types of CCDA, common mode and difference mode, are discussed in detail in this section.

Difference-Mode CCDA
The difference-mode CCDA (dCCDA), illustrated in Figure 7, consists of the standard arrangement of a difference amplifier and a capacitor inserted between the noninverting and inverting terminals. The capacitor is referred to as a differential-mode capacitor.

CCDAs
Two types of CCDA, common mode and difference mode, are discussed in detail in this section.

Difference-Mode CCDA
The difference-mode CCDA (dCCDA), illustrated in Figure 7, consists of the standard arrangement of a difference amplifier and a capacitor inserted between the noninverting and inverting terminals. The capacitor is referred to as a differential-mode capacitor.
Assuming an operational amplifier of zero offset voltage, an output resistance that is negligibly small, and an input resistance that is much larger than , we obtain The difference voltage is or The output voltage is The voltage on the inverting terminal of the operational amplifier is then derived as Assuming an operational amplifier of zero offset voltage, an output resistance that is negligibly small, and an input resistance that is much larger than R, we obtain The voltage on the inverting terminal of the operational amplifier is then derived as Let T dm = αRC dm ; Equation (5) can then be expressed as Substituting Equation (1) into (5) and then Equation (3) for Energies 2021, 14, 3656 10 of 25 Let v 2 (s) = V Z /s be a square-wave pulse train, V Z range from 0 to V PS , and v 1 (s) The corresponding output of the operational amplifier is Figure 8 illustrates the response of v o and v d when the resistance R is large. In other applications with a low R, the difference amplifier is governed by the amplifier equation

Common-Mode CCDA
The common-mode CCDA (cCCDA), illustrated in Figure 9, consists of a standard arrangement of a difference amplifier and two capacitors added to the terminals. The capacitors are referred to as common-mode capacitors. Assuming the operational amplifier has zero offset voltage, the output resistance is negligibly small, and the input resistance is much larger than , we obtain

The amplification is
The analytical results are depicted in Figure 8.

Common-Mode CCDA
The common-mode CCDA (cCCDA), illustrated in Figure 9, consists of a standard arrangement of a difference amplifier and two capacitors added to the terminals. The capacitors are referred to as common-mode capacitors. Assuming the operational amplifier has zero offset voltage, the output resistance is negligibly small, and the input resistance is much larger than R, we obtain where: From the inverting terminal, the following is obtained: , , Figure 9. The cCCDA circuit.
From the inverting terminal, the following is obtained: The difference voltage is After the substitution of v 2 (t) = V Z and v 1 (t) = V re f for v d (t) ≤ 0, the common-mode capacitor starts to charge to a positive voltage from time t = 0 in a steady state, such that When v d (t) > 0, that is, after time t ≥ βT, the voltage of the common-mode capacitor rises for A dm Because δ + β = 0.5, after the time t ≥ T/2, we have v 2 (t) = 0, and the voltage of the common-mode capacitor decreases. Consequently, the minimum voltage on the common-mode capacitor is Assuming that v d is negligibly small during the time T/2 ≥ t ≥ βT, Assuming that e and From Equations (16) and (19), the constraint for V re f is 0 < V re f < V Z /2. The smaller the V re f , the higher the duty cycle δ. From Equation (19), it is confirmed that δ max = 0.5, which is identical to the VCO output when V re f = 0 V. The sensitivity of δ with respect to V re f is derived as follows: ∂δ Equation (20) shows that we must reduce either R or C cm and let α = 1 to ensure small sensitivity of V re f to the duty cycle δ. When δ = 0 and α = 1, the higher bound for V re f is obtained as follows: For example, if T = 1/(4·MHz), T cm = 10 kΩ·15 pF, and V Z = 5 V, the higher bound is calculated to be 2.24 V.
Let V 2 (s) = V Z /s be a square-wave pulse train, V Z range from 0 to V PS , and 0 < V re f < V PS ; consequently, the corresponding output is The analytical results are depicted in Figure 10. It is difficult to compare Figures 8 and 10, because they have two similar characteristics: fast charging of the coupled capacitor when the operational amplifier is functioning as a voltage amplifier, and slow charging of the capacitor when the operational amplifier is outputting zero voltage. However, they are different with respect to their time constant during slow charging. The analytical results are depicted in Figure 10. It is difficult to compare Figure 8 and Figure 10, because they have two similar characteristics: fast charging of the coupled capacitor when the operational amplifier is functioning as a voltage amplifier, and slow charging of the capacitor when the operational amplifier is outputting zero voltage. However, they are different with respect to their time constant during slow charging.

CCDA Application
To validate the applicability of the CCDAs, in this section, two designs are illustrated, analyzed, and applied using the cCCDA and dCCDA.

VCO to VFPWM Using Low-Resistance dCCDA Feedback
The block diagram of the dCCDA is shown in Figure 11. The transfer function of a low-resistance dCCDA typically yields a difference amplifier unity gain when = 1.

CCDA Application
To validate the applicability of the CCDAs, in this section, two designs are illustrated, analyzed, and applied using the cCCDA and dCCDA.

VCO to VFPWM Using Low-Resistance dCCDA Feedback
The block diagram of the dCCDA is shown in Figure 11. The transfer function of a low-resistance dCCDA typically yields a difference amplifier unity gain when α = 1. The nonlinear function (V ( ) ) increases monotonically with increasing i.e., the voltage input to control the frequency range of the SN54LS628 VCO. Whe voltage ( ) increases, the feedback signal ( ( ) ) increases and the frequen decreases simultaneously. To be consistent with our WPT application shown in  The function of a practical VCO, such as the IC-SN54LS628, as shown in Figure 12 as an example, can be simplified into the following expression: The nonlinear function g V I(rng) increases monotonically with increasing V I(rng) , i.e., the voltage input to control the frequency range of the SN54LS628 VCO. When the voltage V I(rng) increases, the feedback signal g V I(rng) increases and the frequency f o decreases simultaneously. To be consistent with our WPT application shown in Figure 1, we defined V F ≡ V I( f req) − g V I(rng) and G Z0 as the gain of the switching frequency to voltage transfer function. The nonlinear function (V ( ) ) increases monotonically with increasing ( ) , i.e., the voltage input to control the frequency range of the SN54LS628 VCO. When the voltage ( ) increases, the feedback signal ( ( ) ) increases and the frequency decreases simultaneously. To be consistent with our WPT application shown in Figure 1, we defined ≡ ( ) − ( ( ) ) and as the gain of the switching frequency to voltage transfer function. The output of the dCCDA with low resistance and = 1 is presented as a simple difference amplifier as follows: The dCCDA can be derived from the intrinsic parasitic capacitance of the operational amplifier. As shown in Figure 13, when ( ) = 0, the output of the VCO has a frequency of . When ( ) = − , the output of the VCO is in the frequency range ( ( ) − ( − )). The sampling time for of the dCCDA is then written as follows: The duty cycle of of the dCCDA can expressed as The output v o of the dCCDA with low resistance and α = 1 is presented as a simple difference amplifier as follows: The dCCDA can be derived from the intrinsic parasitic capacitance of the operational amplifier. As shown in Figure 13, when V I(rng) = 0, the output of the VCO has a frequency of G Z0 V F . When V I(rng) = V PS − V re f , the output of the VCO is in the frequency range G Z0 V I( f req) − g V PS − V re f . The sampling time for v 2 of the dCCDA is then written as follows: The switching frequency is The VFPWM has a slew rate limit on the voltage output of the dCCDA; however, the slew rate limit due to the need to charge the difference-mode capacitor does not harm the VCO's digital output. By contrast, the slew rate limit can prevent high-frequency noise in the feedback loop to the VCO. In practice, adding some more difference-mode capacitance to the dCCDA is preferable in order to improve the stability of the VFPWM. The corresponding SPICE analysis is shown in Figure 14. In the SPICE circuit model, a VCO with a center frequency of 5.5 MHz, a frequency range of 2.5 MHz, and a sensitivity of 1.0 MHz/V is used. Because the output of the VCO is 1 V, we amplify the output to 5 V before feeding it to the dCCDA. The result shows that the duty ratio is no more than 50%. The switching frequency f o is The VFPWM has a slew rate limit on the voltage output of the dCCDA; however, the slew rate limit due to the need to charge the difference-mode capacitor does not harm the VCO's digital output. By contrast, the slew rate limit can prevent high-frequency noise in the feedback loop to the VCO. In practice, adding some more difference-mode capacitance C dm to the dCCDA is preferable in order to improve the stability of the VFPWM. The corresponding SPICE analysis is shown in Figure 14. In the SPICE circuit model, a VCO with a center frequency of 5.5 MHz, a frequency range of 2.5 MHz, and a sensitivity of 1.0 MHz/V is used. Because the output of the VCO is 1 V, we amplify the output to 5 V before feeding it to the dCCDA. The result shows that the duty ratio is no more than 50%. The VFPWM has a slew rate limit on the voltage output of the dCCDA; however, the slew rate limit due to the need to charge the difference-mode capacitor does not harm the VCO's digital output. By contrast, the slew rate limit can prevent high-frequency noise in the feedback loop to the VCO. In practice, adding some more difference-mode capacitance to the dCCDA is preferable in order to improve the stability of the VFPWM. The corresponding SPICE analysis is shown in Figure 14. In the SPICE circuit model, a VCO with a center frequency of 5.5 MHz, a frequency range of 2.5 MHz, and a sensitivity of 1.0 MHz/V is used. Because the output of the VCO is 1 V, we amplify the output to 5 V before feeding it to the dCCDA. The result shows that the duty ratio is no more than 50%.

VCO to VFPWM by Using High-Resistance cCCDA
By having a VCO in series with a cCCDA that converts the 50% duty cycle square wave into PWM, the circuit achieves frequency control by simply adjusting , and the duty ratio is controlled by = . Compared with Equations (35) and (34), the frequency and duty cycle of the VFPWM using the low-resistance dCCDA are coupled, which increases the complexity of the WPT control, whereas VFPWM using the high-resistance cCCDA can control the frequency and duty cycle separately, resulting in less complex circuit calibration. The block diagram of a VCO to VFPWM using the high-resistance cCCDA is depicted in Figure 15. SPICE analysis demonstrates the VFPWM result, and the findings are shown in Figure 16. In the SPICE circuit model, a VCO is used with the same settings as for Figure 14.

VCO to VFPWM by Using High-Resistance cCCDA
By having a VCO in series with a cCCDA that converts the 50% duty cycle square wave into PWM, the circuit achieves frequency control by simply adjusting V F , and the duty ratio is controlled by V re f = V δ . Compared with Equations (22) and (23), the frequency and duty cycle of the VFPWM using the low-resistance dCCDA are coupled, which increases the complexity of the WPT control, whereas VFPWM using the high-resistance cCCDA can control the frequency and duty cycle separately, resulting in less complex circuit calibration. The block diagram of a VCO to VFPWM using the high-resistance cCCDA is depicted in Figure 15. SPICE analysis demonstrates the VFPWM result, and the findings are shown in Figure 16. In the SPICE circuit model, a VCO is used with the same settings as for Figure 14.
which increases the complexity of the WPT control, whereas VFPWM using the high-resistance cCCDA can control the frequency and duty cycle separately, resulting in less complex circuit calibration. The block diagram of a VCO to VFPWM using the high-resistance cCCDA is depicted in Figure 15. SPICE analysis demonstrates the VFPWM result, and the findings are shown in Figure 16. In the SPICE circuit model, a VCO is used with the same settings as for Figure 14.  which increases the complexity of the WPT control, whereas VFPWM using the high-resistance cCCDA can control the frequency and duty cycle separately, resulting in less complex circuit calibration. The block diagram of a VCO to VFPWM using the high-resistance cCCDA is depicted in Figure 15. SPICE analysis demonstrates the VFPWM result, and the findings are shown in Figure 16. In the SPICE circuit model, a VCO is used with the same settings as for Figure 14.

Experimental Results
A high gain bandwidth product operational amplifier is used, namely the MAX4265 400-MHz operational amplifier, which yields gain of nearly 100, that is = 100 with a nearly 60° phase lag, i.e., = 50 , at the operation frequency around 4 MHz. Examples of the VFPWM output from a VCO versus and the output in a dCCDA experiment are shown in Figure 17a. The circuit topology is presented in Figure 7. The circuit parameters are similar to those listed in Table 4. The operation voltage, , in this dCCDA configuration is 1.0 V, and the duty ratio, δ, is 22%. The phase lag of versus the output from the VCO is approximately 50°, which matches the phase lag of the opamp.
The experimental results of the VFPWM using a high-resistance cCCDA in series with a VCO, with circuit parameters as shown in Table 4, are illustrated in Figure 17b. The VCO generates nearly 50% duty ratio output when the output of the low-resistance cCCDA is of the duty ratio δ = 30%. The phase lag of versus the output from the VCO is also approximately 50°.

Experimental Results
A high gain bandwidth product operational amplifier is used, namely the MAX4265 400-MHz operational amplifier, which yields gain of nearly 100, that is A dm = 100 with a nearly 60 • phase lag, i.e., θ dm = 50 • , at the operation frequency around 4 MHz. Examples of the VFPWM output from a VCO versus v d and the output in a dCCDA experiment are shown in Figure 17a. The circuit topology is presented in Figure 7. The circuit parameters are similar to those listed in Table 4. The operation voltage, V re f , in this dCCDA configuration is 1.0 V, and the duty ratio, δ, is 22%. The phase lag of v d versus the output from the VCO is approximately 50 • , which matches the phase lag of the opamp. To understand the influence of capacitance in this cCCDA configuration, we measure the duty ratio δ and tuning results versus operation voltage and compare them with the theoretical result obtained using Equation (27). The parameters and α in Table 4 are set to 20 kΩ and 1, respectively. The parameter in Table 4 is set to two capacitances, and , respectively, according to the two ± terminals of the amplifier in Figure 9. The selection of and could be many combinations. Figure 18 shows the results for = 15 , and varies from 9 to 23 pF when R = 20 kΩ and α = 1. The experimental results of the VFPWM using a high-resistance cCCDA in series with a VCO, with circuit parameters as shown in Table 4, are illustrated in Figure 17b. The VCO generates nearly 50% duty ratio output when the output of the low-resistance cCCDA is of the duty ratio δ = 30%. The phase lag of v d versus the output from the VCO is also approximately 50 • . To understand the influence of capacitance in this cCCDA configuration, we measure the duty ratio δ and tuning results versus operation voltage V re f and compare them with the theoretical result obtained using Equation (19). The parameters R and α in Table 4 are set to 20 kΩ and 1, respectively. The parameter C cm in Table 4 is set to two capacitances, C + cm and C − cm , respectively, according to the two ± terminals of the amplifier in Figure 9. The selection of C + cm and C − cm could be many combinations. Figure 18 shows the results for C − cm = 15pF, and C + cm varies from 9 to 23 pF when R = 20 kΩ and α = 1.  Figure 19. The duty ratio responses of the three capacitance combinations match the theoretical response; however, the combination with identical capacitances, namely ( , ) = (15pF, 15pF), is closest to the theoretical response. Thus, the VFPWM design of the cCCDA configuration is well balanced in practice.   Then, only three combinations of (C + cm , C − cm ), that is, (15 pF, 15 pF), (15 pF, 10 pF), and (10 pF, 15 pF), are implemented in the experiments, and a comparison of the measurements with the experimental results of Equation (19) is presented in Figure 19. The duty ratio responses of the three capacitance combinations match the theoretical response; however, the combination with identical capacitances, namely (C + cm , C − cm ) = (15pF, 15pF), is closest to the theoretical response. Thus, the VFPWM design of the cCCDA configuration is well balanced in practice. Figure 20 illustrates the influence of resistance on the relationship between the duty ratio and operation voltage V re f in the cCCDA configuration. The δ max values are all close to 50% when V re f = 0, but they decrease slightly when the resistance in Table 4 increases from 8.2 to 20 kΩ. The limitation values of V re f , when the duty ratios are diminished, move away from the cutoff operation voltage at V re f = 2.5 V when the resistances are increased from 8.2 to 20 kΩ. The intersection of the duty ratio curves in Figure 20 is located at approximately V re f = 1.2 V, probably because we set a threshold of V = 1.2 V when analyzing the experimental results. is closest to the theoretical response. Thus, the VFPWM design of the cCCDA configuration is well balanced in practice. Figure 19. Influence of the capacitance on the duty ratio vs. control voltage ( ) in cCCDA letting α = 1 and = 20 kΩ in Table 2. Figure 20 illustrates the influence of resistance on the relationship between the duty ratio and operation voltage in the cCCDA configuration. The values are all close to 50% when = 0, but they decrease slightly when the resistance in Table 4 increases from 8.
8.2k 10k 12k 15k 20k Figure 19. Influence of the capacitance C cm on the duty ratio vs. control voltage (V δ ) in cCCDA letting α = 1 and R = 20 kΩ in Table 2. Figure 19. Influence of the capacitance on the duty ratio vs. control voltage ( ) in cCCDA letting α = 1 and = 20 kΩ in Table 2. Figure 20 illustrates the influence of resistance on the relationship between the duty ratio and operation voltage in the cCCDA configuration. The values are all close to 50% when = 0, but they decrease slightly when the resistance in Table 4 increases from 8.  The results in Figures 19 and 20 provide the transfer function between duty ratio δ (%) and the control voltage of V δ for the VFPWM circuit associated with the high-resistance cCCDA. The switching control depicted in Figure 1 consisting of the transfer matrix could be formulated into the following equation.
The gain G z1 from δ to V δ are piecewise linear functions interpolated from Figures 19 and 20 according to the selection of (C + cm , C − cm ) and R. The VFPWM driving circuit PCB was fabricated according to Figure 15, as shown in Figure 21. The VFPWM was integrated into a WPT device, as shown in Figure 22. It illustrates the validity of the cCCDA of the VFPWM in the WPT system application; the distance of the wireless transfer was more than 100 cm. In the photo in Figure 23, it can be seen that all output connectors of the function generator are disconnected. The cCCDA is used instead of the function generator to provide the switching signal to the gate driver of the PTU. In addition, there are multiple PTUs powering multiple PRUs. trix could be formulated into the following equation.
The gain from to are piecewise linear functions interpolated from Figures  19 and 20 according to the selection of ( , ) and . The VFPWM driving circuit PCB was fabricated according to Figure 15, as shown in Figure 21. The VFPWM was integrated into a WPT device, as shown in Figure 22. It illustrates the validity of the cCCDA of the VFPWM in the WPT system application; the distance of the wireless transfer was more than 100 cm. In the photo in Figure 23, it can be seen that all output connectors of the function generator are disconnected. The cCCDA is used instead of the function generator to provide the switching signal to the gate driver of the PTU. In addition, there are multiple PTUs powering multiple PRUs.  trix could be formulated into the following equation.
The gain from to are piecewise linear functions interpolated from Figures  19 and 20 according to the selection of ( , ) and . The VFPWM driving circuit PCB was fabricated according to Figure 15, as shown in Figure 21. The VFPWM was integrated into a WPT device, as shown in Figure 22. It illustrates the validity of the cCCDA of the VFPWM in the WPT system application; the distance of the wireless transfer was more than 100 cm. In the photo in Figure 23, it can be seen that all output connectors of the function generator are disconnected. The cCCDA is used instead of the function generator to provide the switching signal to the gate driver of the PTU. In addition, there are multiple PTUs powering multiple PRUs.  The power transfer efficiency was reported in [24]. The maximum distance for 1 W power delivery can be as far as 140 cm when v DS is ≥ 700 V and the corresponding input voltage V DD is around 300 V. We achieved the same result as before. In addition, we surpassed the previous achievement by enabling MIMO (multiple input and multiple output) applications, because the function generator can only control a maximum of two PTUs at a time. Nevertheless, the VFPWM is much less inexpensive than the function generator, and it is very handy and small. In [25], we derived a theory called the minimum power input control, which trades off PDL (Power Delivered to Load) for the switching loss of the GaN HEMT in order to yield the optimal PTE (Power Transfer Efficiency). However, the MIMO control was not shown in [25], because the function generator Tektronix AFG 31054, which is a dual channel output equipment, does not allow easy management of the phase difference required for the operation of different PTUs in different arrangements. On the other hand, we were able to easily adjust the individual VFPWM boards in this paper to obtain the required phase difference among the PTUs and achieve the best power output for multiple PRUs. The power transfer efficiency was reported in [24]. The maximum distance for 1 W power delivery can be as far as 140 cm when vDS is ≥ 700 V and the corresponding input voltage VDD is around 300 V. We achieved the same result as before. In addition, we surpassed the previous achievement by enabling MIMO (multiple input and multiple output) applications, because the function generator can only control a maximum of two PTUs at a time. Nevertheless, the VFPWM is much less inexpensive than the function generator, and it is very handy and small. In [25], we derived a theory called the minimum power input control, which trades off PDL (Power Delivered to Load) for the switching loss of the GaN HEMT in order to yield the optimal PTE (Power Transfer Efficiency). However, the MIMO control was not shown in [25], because the function generator Tektronix AFG 31054, which is a dual channel output equipment, does not allow easy management of the phase difference required for the operation of different PTUs in different arrangements. On the other hand, we were able to easily adjust the individual VFPWM boards in this paper to obtain the required phase difference among the PTUs and achieve the best power output for multiple PRUs.
The experiment of a MIMO WPT demo is depicted in Figure 23, which uses the VFPWM shown in Figure 21 to control class-E amplifier switching. In this experiment, we set = = 15pF , = 20 kΩ and = 1 for the cCCDA. One of the VCO inputs V ( ) is set to 5V. The measured results show a total power output from five PRUs of 9.26 W when the total power input from two PTUs is 45 W. The input signals to the charge pump gate drive and the drain-source voltage of the class-E amplifier are shown in Figure  24. The control voltages of the VFPWM are shown in Table 5. Compared to the theoretical results, the estimated value of the switching frequency closely matches the data read from Figure 12. There is some difference, within 20%, between the estimated duty ratio δ% from the measurement and the theoretical duty ratio δ% interpolated from Figure 20. The differences are a result of the input impedance of the charge pump gate drive and the input impedance of the GaN HEMT transistor, which can be eliminated by the closed loop control in the WPT system using the minimum power input control [25]. The experiment of a MIMO WPT demo is depicted in Figure 23, which uses the VFPWM shown in Figure 21 to control class-E amplifier switching. In this experiment, we set C + cm = C − cm = 15pF, R = 20 kΩ and α = 1 for the cCCDA. One of the VCO inputs V I(rng) is set to 5 V. The measured results show a total power output from five PRUs of 9.26 W when the total power input from two PTUs is 45 W. The input signals to the charge pump gate drive and the drain-source voltage of the class-E amplifier are shown in Figure 24. The control voltages of the VFPWM are shown in Table 5. Compared to the theoretical results, the estimated value of the switching frequency closely matches the data read from Figure 12. There is some difference, within 20%, between the estimated duty ratio δ% from the measurement and the theoretical duty ratio δ% interpolated from Figure 20. The differences are a result of the input impedance of the charge pump gate drive and the input impedance of the GaN HEMT transistor, which can be eliminated by the closed loop control in the WPT system using the minimum power input control [25]. voltage VDD is around 300 V. We achieved the same result as before. In addition, we surpassed the previous achievement by enabling MIMO (multiple input and multiple output) applications, because the function generator can only control a maximum of two PTUs at a time. Nevertheless, the VFPWM is much less inexpensive than the function generator, and it is very handy and small. In [25], we derived a theory called the minimum power input control, which trades off PDL (Power Delivered to Load) for the switching loss of the GaN HEMT in order to yield the optimal PTE (Power Transfer Efficiency). However, the MIMO control was not shown in [25], because the function generator Tektronix AFG 31054, which is a dual channel output equipment, does not allow easy management of the phase difference required for the operation of different PTUs in different arrangements.
On the other hand, we were able to easily adjust the individual VFPWM boards in this paper to obtain the required phase difference among the PTUs and achieve the best power output for multiple PRUs. The experiment of a MIMO WPT demo is depicted in Figure 23, which uses the VFPWM shown in Figure 21 to control class-E amplifier switching. In this experiment, we set = = 15pF , = 20 kΩ and = 1 for the cCCDA. One of the VCO inputs V ( ) is set to 5V. The measured results show a total power output from five PRUs of 9.26 W when the total power input from two PTUs is 45 W. The input signals to the charge pump gate drive and the drain-source voltage of the class-E amplifier are shown in Figure  24. The control voltages of the VFPWM are shown in Table 5. Compared to the theoretical results, the estimated value of the switching frequency closely matches the data read from Figure 12. There is some difference, within 20%, between the estimated duty ratio δ% from the measurement and the theoretical duty ratio δ% interpolated from Figure 20. The differences are a result of the input impedance of the charge pump gate drive and the input impedance of the GaN HEMT transistor, which can be eliminated by the closed loop control in the WPT system using the minimum power input control [25].     Figure 12 and ** corresponds to Figure 20.

Discussion
The existing, and widely popular, inductive power transfer (IPT) cannot achieve long-distance power delivery, in theory. Resonant wireless power transfer allows electrical power to be delivered over long distances with acceptable efficiency, which is usually higher than 80%. Inductive power transfer through a metal object is also a major obstacle due to the generation of eddy currents, leading to substantial device heating. The resonant WPT system with a frequency of 6.78 MHz is capable of transferring power into metalencapsulated mobile devices without considering the eddy current effect. However, many technologies and tests for resonant WPT systems are still under investigation. Namely, the class-E amplifier, the control of which still needs to be validated with respect to installation costs and radio regulations. The power efficiency for the WPT is also one of the major concerns in real-life scenarios; WPT will never be as efficient as wired power transfer, but how close could the efficiency be? In addition to low cost, low environmental contamination, and high efficiency, the maximum power that can be transferred in a desired distance between the power transfer unit (PTU) and the power receiving unit (PRU) is also a factor that affects the decision to use resonant WPT systems. In this paper, we focused on the critical aspect of the gate driving the physical control of the class-E amplifier. The control of class-E amplifiers takes the optimal tuning of switching frequency and duty cycle as the inputs and generates the corresponding pulse train to switch the transistor on or off. Considering the multiple-input-multiple-output (MIMO) applications of WPT, the control hardware should be small in size, such that the PTU can be placed easily. It is recommended that the size of the PTUs be made so small that they can be placed directly into the socket on the wall or into a power extension cord, just like chargers for mobile devices. In this paper, the VFPWM consists of only a VCO and an OP-amp, and can be miniaturized into a system in packaging (SiP), while the class-E amplifier can also be reduced to the size of a cigarette box. The antenna of the PTU can also be made into the stickers that go on different faces of the PTU box. The minimum power input control [25] can also be implemented in the microprocessor or FPGA. The VFPWM proposed in this paper is a low-cost and high-reliability solution for the control of class-E amplifiers. Nevertheless, the duty cycle control, which is independent from the frequency control, can be adjusted via the analog voltage input, as shown in Figures 19 and 20, with the circuit topology as shown in Figures 15 and 16. The live demo photo shown in Figure 22 displays the possibility of multiple PRUs being charged simultaneously since PRUs can be distanced from one another.

Conclusions
Two VFPWM circuitries derived from a VCO and CCDAs, classified as the dCCDA and cCCDA, are proposed in this paper. The dCCDA with low resistance reduces the noise in the feedback loop to the VCO. The cCCDA with high resistance can be used in series with the VCO to meet the VFPWM requirements. Compared with dCCDA, the cCCDA circuit enables independent control of the frequency, and the duty cycle is deemed to be better in 6.78-MHz resonant WPT applications. The circuit was fabricated and used in a field test, yielding power transfer to 100 cm away for multiple power receiving units. The output power of the corresponding single power transmission unit was more than 10 W. The corresponding control can be either digital or analog for different WPT applications and market segments. With the VFPWM design introduced in this paper, the challenge of electromagnetic interference (EMI) from the antenna to the power supplies remains to be addressed in future studies. Currently, we can integrate multiple power transmission units to form a multiple-input-multiple-output system for WPT applications. In the future, we will devote more attention to high-power delivery, providing that the environmental safety issues are simultaneously addressed. High power delivery to load (PDL) can be achieved by using either multiple PTUs to the load or multiple PRU antennas on the load, depending on the load characteristics. The use of this resonant WPT technology will be seen in the future in electrical vehicle (EV) charging applications.  inductance on the switching power supply side of the PTU C 1 resonant capacitance on the switching power supply side of the PTU L 2 equivalent inductance including the load inductance on the PTU side C 2 equivalent capacitance including the load capacitance on the PTU side R L equivalent resistance of PRU on the PTU side v s switching control signal of PTU V F control voltage corresponding to the frequency f o to the VFPWM; V δ control voltage corresponding to the duty ratio δ to the VFPWM V DD input voltage of the PTU Gz zero-order hold transfer function matrix G Z0 gain of the switching frequency to voltage transfer function G Z1 gain of the duty ratio to voltage transfer function A dm differential mode gain of the OPAMP θ dm differential mode phase lag of the OPAMP @ 4MHz v d Difference voltage of the OPAMP V PS power supply voltage of the OPAMP C dm differential mode capacitance added to the difference amplifier C cm common mode capacitance added to the difference amplifier voltage input to control the frequency range of the SN54LS628 VCO