Multivariable Unconstrained Pattern Search Method for Optimizing Digital PID Controllers Applied to Isolated Forward Converter

: Most of the traditional PID tuning methods are heuristic in nature. The heuristic approach-based tuned PID controllers show only nominal performance. In addition, in the case of a digital redesign approach, mapping of the heuristically-designed continuous-time PID controllers into discrete-time PID controllers and in case of the direct digital design approach, mapping of the continuous-time plant (forward converter) into the discrete-time plant, results in frequency distortion (or warping). Besides this, nonlinear elements such as ADC and DAC, and delay in the digital control loop deteriorate the control performance. There is a need to tune conventionally-designed digital controllers to enhance performance. This paper proposes optimized discrete-time PID controllers for a forward DC–DC converter operating in continuous conduction mode (CCM). The considered conventional digital PID controllers designed on the basis of the digital redesign and direct digital approaches are tuned by one of the multivariable unconstrained pattern search methods named Hooke–Jeeves (H–J) search method to ensure excellent output voltage regulation performance against the changes in input voltage and load current. Numerical results show that the H–J-based optimized PID compensated forward converter system shows tremendous improvement in performance compared to its unoptimized counterpart and simulated annealing (SA)-based compensated system, thus justifying the applicability of the H–J method for enhancing the performance.


Introduction
Forward converters, which are popular switched-mode power supplies (SMPSs), have a simple circuit configuration, as they employ a single power transistor referenced to the primary-side return. Forward converter topologies (especially single-ended), typically used in off-line applications in the 100 W−300 W region, are extensively used in applications such as telecom central office equipment, smartphones, systems that use distributed power Regarding the literature review, in [2], a dual-loop control strategy, where an analog PI controller was used for the synthesis of both the internal current control loop and the external voltage control loop, was proposed for a galvanically isolated forward converter to ensure better transient response and reduced ripples in the output voltage. For both the loops, the PI controller was designed based on crossover frequency and phase margin characteristics. In [3], an output current-differential (OCD) control scheme having a masterslave structure was proposed for a three forward converters-based input-series-outputparallel (ISOP) system. The output voltage regulator (OVR) loop designed for a master module (to provide current references to slave modules) and individual load-current sharing loops developed for slave modules (to regulate the current in each module equally) of the OCD control scheme were constructed using the frequency-response characteristics. In [4], the authors, however, proposed a digital PI controller implemented through Digital Signal Processor (DSP) for OVR and input voltage sharing (IVS) for a modular ISOP system. Various analog compensators, including PI, PID, and lead were designed heuristically and applied to forward converter to ensure better control performance [5]. In [6], regulation of the most effective DC output voltage of a multiple output high frequency (MOHF) isolated forward converter mainly designed for power factor correction (PFC) was achieved by the heuristic Ziegler Nichols method-based tuned PI controller. In [7], for a single-ended forward circuit, negative feedback for driving MOSFET was accomplished through an operational amplifier (from Texas Instruments) with high-bandwidth. The control loops (mostly analog in nature) suggested in all the references mentioned above for switching converters are designed based on classical control theory. There occurs usually a tradeoff between robustness and transient response in such types of controllers.
To overcome the limitations, recently other artificial intelligence and nonlinear control theory-based control techniques have also been reported in the literature. Authors in [8] suggested a fuzzy-neural sliding-mode controller (FNSMC) comprising a neural controller and a compensation controller for a PWM-based isolated forward converter to achieve excellent load and line regulations. Authors in [9] concluded through simulation results that the fuzzy PID controller displayed better transient and steady-state performance than did PID and fuzzy controllers when applied to push-pull forward (PPF) DC-DC converter. In [10], two controllers, called a self-regulating fuzzy logic control (SR-FLC) and a fuzzy sliding-mode control (SR-FSMC) were proposed for a forward DC-DC converter. To avoid a time-consuming trial-and-error tuning procedure, fuzzy rules were adjusted by a gradient-based rule modifier. A fuzzy logic controller (FLC) along with PI was successfully developed and applied to a modular forward converter-based input-paralleloutput-series (IPOS) system [11] and a forward converter with an active clamp circuit (ACFC) [12] used in the telecom power supply. In [13], the fuzzy logic-based PI controller was suggested for a bidirectional dual active bridge converter. In [14], a sliding mode controller was applied to a forward converter to achieve regulated output voltage even against load transients. An adaptive disturbance observer (ADO)-based practical terminal sliding mode control (TSMC) that required no exact feedback linearization about the plant dynamics was suggested in [15]. The ADO-TSMC guaranteed high control accuracy and rapid convergence by adopting a TSMC-type surface. In [16], the adaptive nonsingular TSMC was integrated with neural networks (NNs) to realize fault-tolerant control for the simultaneous compensation of model uncertainties and disturbances, as well as actuator faults. Authors in [17] proposed a robust PID controller with quantitative feedback theory (QFT) to ensure stability in the presence of model uncertainties and external disturbances. The control approaches, however, may require a time-consuming trial-and-error tuning procedure to ensure superior performance.
Owing to rapid advances in digital control technology, researchers have also suggested digital control loops for isolated DC-DC converters. In [18], for a central-tapped full-bridge converter to display superior line regulation, the two dedicated control loops were realized using a digital PID compensator. An FPGA-based on-line tuned PID controller was also suggested in [19] for a forward converter to attain better control performance without pin-pointing the procedure of calculating PID parameters. A conventionally designed analog PID controller for a specific bandwidth (crossover frequency), and phase margin was digitally implemented by DSP to regulate the output voltage of a full-bridge active-clamp forward-flyback (FBACFF) converter in [20]. Only a notion of the microcontroller-based implementation of digital control for a forward converter with a DC electromagnet as a load of an SMPS designed for electromagnet systems was given in [21] to keep output voltage regulated against the input voltage sag.
Limited research has been carried out on realizing digital controllers for isolated switching converters. Digital control loop nonlinearities, warping (or distortion) in digital frequency response during (approximate) mapping from s-plane into z-plane, and so on have detrimental effects on digital controller performance. Proper retuning of once traditionally designed digital PID controllers by optimization techniques may diminish nonlinear effects to obtain the required transient response. The gradient-free H-J method is employed here for retuning controller coefficients. The method uses flexible searching steps to ensure the near-optimal solution and offers characteristics such as simplicity, robustness, and versatility. This methodical pattern search technique yields an optimum solution for an effectively-distinct cost (objective) function and handles well, especially for small-and medium-sized optimization problems. This lays a good foundation for the construction of this paper.
Additionally, the H-J method is deterministic, as it does not involve randomness during its progression. It converges to the same end solution on every run for the same initial point. On the other hand, a metaheuristic optimization method converges to a different point every time it is executed. The process may sometimes become laborious for finding the best solution in the case of metaheuristics. Once compared to one of the metaheuristics, such as simulated annealing (in our case), the H-J method gives promising results and shows an optimal end solution. This justifies the applicability of the H-J method to the optimized digital control algorithms applied to the forward converter.
The paper is structured in the following way. Section 2 presents the literature review of the state-of-the-art. Section 3 describes the dynamics (i.e., the transfer function) of a forward DC-DC converter required for the design of discrete-time PID controllers. The design of four types of discrete-time PID controllers based on classical control theory is presented in Section 4. The H-J search algorithm employed for optimizing digital PID controllers is described in detail in Section 5. Simulation results are presented in Section 6. Hardware into the loop implementation is pinpointed in Section 7. Finally, conclusions are drawn in Section 8.

Description of Forward Converter Dynamics
For the sake of designing the required control loop, the transfer function (dynamics) of a forward DC-DC converter should be known. A simplified schematic of a forward DC-DC converter is shown in Figure 1. It consists of a controllable switch Q (MOSFET, BJT, IGBT, and so on), a three-winding isolation transformer with a demagnetizing (reset) winding, diodes D 1 , D 2 , and D 3 , an output filter inductor L with its direct current resistance (DCR) r L , an output filter capacitor C with its equivalent series resistance (ESR) r C , and a load resistance R. Bifilar transformer winding with ratio 1:1 for N p :N r is normally used. The auxiliary (reset) winding helps in resetting the transformer during the switching off period to avoid core saturation.

Description of Forward Converter Dynamics
For the sake of designing the required control loop, the transfer function (dynamics) of a forward DC-DC converter should be known. A simplified schematic of a forward DC-DC converter is shown in Figure 1. It consists of a controllable switch Q (MOSFET, BJT, IGBT, and so on), a three-winding isolation transformer with a demagnetizing (reset) winding, diodes D1, D2, and D3, an output filter inductor L with its direct current resistance (DCR) rL, an output filter capacitor C with its equivalent series resistance (ESR) rC, and a load resistance R. Bifilar transformer winding with ratio 1:1 for Np:Nr is normally used. The auxiliary (reset) winding helps in resetting the transformer during the switching off period to avoid core saturation. Consider the converter working in CCM in two modes, as shown in Figure 2. When transistor Q switches are on, primary current ip rises linearly from zero; diode D2 becomes reverse-biased; voltage Vin develops across primary winding Np; energy is transferred from the primary winding to the secondary and then through the forward-biased D1 to the L-C filter and load R. When transistor Q switches off, the transformer voltage gets reversed; diode D1 gets reverse-biased, whereas diodes D2 and D3 become forward-biased; the primary reset winding with D3 provides a path to the transformer magnetizing current to avoid core saturation; this forces the maximum duty cycle Dmax not to exceed 50% theoretically for resetting transformer fully.
Applying the inductor volt-second balance (IVSB) principle while neglecting all the losses, the DC transfer function of a forward converter can be expressed by represents the turn ratio of the transformer, and D is the duty ra-  Consider the converter working in CCM in two modes, as shown in Figure 2. When transistor Q switches are on, primary current i p rises linearly from zero; diode D 2 becomes reverse-biased; voltage V in develops across primary winding N p ; energy is transferred from the primary winding to the secondary and then through the forward-biased D 1 to the L-C filter and load R. When transistor Q switches off, the transformer voltage gets reversed; diode D 1 gets reverse-biased, whereas diodes D 2 and D 3 become forward-biased; the primary reset winding with D 3 provides a path to the transformer magnetizing current to avoid core saturation; this forces the maximum duty cycle D max not to exceed 50% theoretically for resetting transformer fully. Since the forward converter is a buck-derived isolated converter, its transfer function can be easily derived from the buck converter [22]. The well-established state-space averaging and linearization technique proposed by Middlebrook et al. [23]    The circuit element values taken for the forward converter design example, unless otherwise specified, are V in = 36 V, V out = 12 V, n = N s /N p = 32/48, L m = 10 mH, L = 400 µH, r L = 120 mΩ, C = 100 µF, r C = 33 mΩ, R = 10 Ω, and f s = 60 kHz (T s = 1.67 × 10 −5 s).
Applying the inductor volt-second balance (IVSB) principle while neglecting all the losses, the DC transfer function of a forward converter can be expressed by where n (= N s /N p ) represents the turn ratio of the transformer, and D is the duty ratio. The output-input voltage relationship of buck converter V out = DV in becomes translated into the forward converter's V out = DnV in if we replace V in by nV in . Since the forward converter is a buck-derived isolated converter, its transfer function can be easily derived from the buck converter [22]. The well-established state-space averaging and linearization technique proposed by Middlebrook et al. [23] was employed to derive the buck converter's transfer function. The buck converter's transfer function can be translated into the forward converter's just by replacing V in with nV in , as already remarked. As a result, the control-to-output (or duty ratio-to-output) small-signal transfer function in the s-domain of the forward converter is expressed as Here ω ESR , ω 0 = 1/τ, and Q = 1/2ζ signify the capacitor zero frequency, the filter resonance frequency, and the filter quality factor, respectively. From T p (s), it is observed that due to the presence of capacitor ESR, a zero frequency is introduced at 1/r C C [24].
A pair of complex conjugate poles at ω 0 causes phase reduction, thus resulting in a low phase margin. For the component values mentioned above, the open-loop forward converter offers only a phase margin of 8.01 • at 2.5 × 10 4 rad/s (see Figure 3). The low phase margin needs to be raised to achieve better transient and steady-state characteristics. This is accomplished by introducing a compensator into the loop, which introduces phase at the required crossover frequency to meet the required specifications. A pair of complex conjugate poles at  0 causes phase reduction, thus resulting in a low phase margin. For the component values mentioned above, the open-loop forward converter offers only a phase margin of 8.01° at 2.5 × 10 4 rad/s (see Figure 3). The low phase margin needs to be raised to achieve better transient and steady-state characteristics. This is accomplished by introducing a compensator into the loop, which introduces phase at the required crossover frequency to meet the required specifications. For the digital compensated system, the analog plant has to be discretized. The continuous-time forward DC-DC converter () p Ts (plant) is discretized using zero-orderhold (ZOH) with Ts = 1/(60 × 10 3 ) s. That is to say, Using the values of the components mentioned above, the discretized plant by ZOH, numerically, can be expressed by For the digital compensated system, the analog plant has to be discretized. The continuous-time forward DC-DC converter T p (s) (plant) is discretized using zero-orderhold (ZOH) with T s = 1/(60 × 10 3 ) s. That is to say, Using the values of the components mentioned above, the discretized plant by ZOH, numerically, can be expressed by with

Conventional Digital Controller Design
Both the digital redesign or emulation and direct digital approaches are adopted in the paper to construct digital PID controllers. The first three PID controllers considered in the paper are first designed in s-plane for a specific phase margin and crossover frequency (frequency-domain characteristics). The analog PID controllers are then mapped into the digital PID controllers using different transformation techniques. The fourth PID controller is directly constructed in the z-plane for the discretized plant. In the case of switching converters, usually a compensator designed for a phase margin (PM) of 60 • and 0-dB crossover frequency (ω x ) of one-tenth the converter switching frequency (f s ) guarantees acceptable rise and settling times, overshoots, and null steady-state error [14]. Unless otherwise specified, all considered PID compensators are designed for PM ≥ 60 • and ω x = ω s /10. It is worth mentioning that we employed four digital controllers to a forward converter. However, other approaches such as the PID-like coefficient diagram method (CDM) [25], one-degree-of-freedom (1DOF) [26] and 2DOF [27] PID, PID with derivative on output (DOO) [24], deadbeat control [28], and so on can also be utilized to realize controllers.
The digital closed-loop forward converter system is shown in Figure 4. The voltage error signal sampled by ADC is processed by a digital PID controller whose output (digital control signal), after its conversion into analog form, is fed to an analog forward converter. Conventionally-designed digital PID controllers are optimized by the H-J method. To facilitate the controller design, ADC, DAC, and delay gains are set to unity initially.
converters, usually a compensator designed for a phase margin (PM) of 60° and 0-dB crossover frequency (ωx) of one-tenth the converter switching frequency (fs) guarantees acceptable rise and settling times, overshoots, and null steady-state error [14]. Unless otherwise specified, all considered PID compensators are designed for PM ≥60° and ωx = ωs/10.
It is worth mentioning that we employed four digital controllers to a forward converter. However, other approaches such as the PID-like coefficient diagram method (CDM) [25], one-degree-of-freedom (1DOF) [26] and 2DOF [27] PID, PID with derivative on output (DOO) [24], deadbeat control [28], and so on can also be utilized to realize controllers.
The digital closed-loop forward converter system is shown in Figure 4. The voltage error signal sampled by ADC is processed by a digital PID controller whose output (digital control signal), after its conversion into analog form, is fed to an analog forward converter. Conventionally-designed digital PID controllers are optimized by the H-J method. To facilitate the controller design, ADC, DAC, and delay gains are set to unity initially.

PID Controller with Complex Zeros
Open-loop complex poles of the forward DC-DC converter emerging due to an output LC filter should be damped as they cause phase reduction. The two complex poles can be compensated by two complex zeros of the compensator. The transfer function of the compensator in s-plane having two complex zeros ω z at the LC resonant frequency ω 0 (i.e., ω z = ω 0 ) to provide the necessary phase lead and an integrator to reduce steady-state error is expressed by Using s = jω, the magnitude and phase of G c (s) can be written as For the complex conjugate zeros, the controller transfer function in (10) can also equivalently be written as where the pair of compensator complex zeros occurs at s = −α ± jβ. The parameters α and β in terms of ω z and Q C can be written as The compensator quality factor Q C is set almost equal to the forward converter Q at maximum output current. The required DC gain K c representing the PID integral gain is computed for the required ω x = ω s /10 by assuming that the control loop is compensated so the gain plot crosses 0 dB at a-1 slope, i.e., As all the parameters α, β, K c , Q C , etc. are known now, the transfer function of the analog controller numerically is calculated to be G c (s) = 6.2557 × 10 −5 s 2 + 1379s + 2.522 × 10 7 s The above compensator is essentially a single-pole, two-zero compensator. Various transformation techniques can be employed to map the analog PID compensator into its equivalent digital counterpart. We start with the simple mapping z = e sT s . The digital PID controller in its velocity form, one of the z-domain counterparts of the s-domain PID controllers, is generally given by Or equivalently, in discrete-time difference equation, the controller can be written as where K cz is the gain of the discrete compensator. The s-plane zeros s 1 and s 2 can be mapped to the corresponding z-plane locations z 1 and z 2 through z 1 = e s 1 T s and z 2 = e s 2 T s , respectively [29]. If the complex zeros z 1 = e −αT s +jβT s and z 2 = e −αT s −jβT s (assuming that both the zeros lie in the same position) are the roots of the polynomial, then The other unknown parameter, the gain K cz of the discrete-time PID compensator, can be computed by meeting the condition that G c (s) and G MAP (z) have the same magnitude at the desired loop crossover frequency f x . That is to say, Performing some algebraic manipulations gives the digital controller as From the step response and Bode plot shown in Figure 5, it can be noticed that the performance of the digital controller deteriorates slightly compared to its analog counterpart.  (21) From the step response and Bode plot shown in Figure 5, it can be noticed that the performance of the digital controller deteriorates slightly compared to its analog counterpart.

PID Controller with Real Zeros
The effect of converter complex poles causing phase reduction can also be nullified using compensator real zeros. For such a case, the analog PID controller with real zeros can be written as Here one of the real zeros is placed at  0 and the other slightly below  0 to provide the necessary phase lead. Keeping in view the converter power stage parameters, their position, however, can be adjusted differently in the vicinity of  0 .
The DC gain c K is computed to achieve the desired x f by meeting the following condition:

PID Controller with Real Zeros
The effect of converter complex poles causing phase reduction can also be nullified using compensator real zeros. For such a case, the analog PID controller with real zeros can be written as Here one of the real zeros is placed at ω 0 and the other slightly below ω 0 to provide the necessary phase lead. Keeping in view the converter power stage parameters, their position, however, can be adjusted differently in the vicinity of ω 0 .
The DC gain K c is computed to achieve the desired f x by meeting the following condition: This gives the following analog controller as G c (s) = 6.0608 × 10 −5 (s + 5022)(s + 4017) s Energies 2021, 14, 77 10 of 23 The compensator in (22) is of type interacting or series where the parameters K c , ω z1 , and ω z2 are independent of one another. Equivalently, the PID controller having a noninteracting or parallel form with independent gains is given by The parameters of the noninteracting form can be derived from that of the interacting form and are related by the following expression: The backward Euler transformation method with sampling time T s is employed to map the parallel form of analog PID into its digital counterpart. This is accomplished by The above expression leads to the following discrete-time PID compensator.
Knowing all the compensator gains and sampling time, the discrete-time PID compensator is given by Just like the case of complex zeros, the s-plane real zeros s 1 and s 2 of an analog PID controller can also be mapped into the corresponding z-domain zeros using z 1 = e −ω z1 T s and z 2 = e −ω z2 T s , respectively. This implies With The discrete-time PID compensator and its discrete-time difference equation can now be expressed as: For a crossover frequency f x , the only unknown parameter K cz of the digital PID is calculated from the following condition: As a result, the digital PID controller, numerically, is expressed by

PID Controller with Derivative Filter
The continuous-time PID controller with a (first-order) derivative filter in parallel form is given by where K p , K i , and K d are controller parameters; T f is a filter time constant. The low pass filter 1/(1 + T f s) appended with derivative term K d s filters out the high-frequency noise entering the differentiator. For computing the coefficients of the PID controller, a frequency response-based PID algorithm developed and patented by MathWorks [30] is used to achieve a good balance between performance (reference tracking and disturbance rejection, and so on) and robustness. The algorithm computes PID coefficients for a specific crossover frequency (loop bandwidth) based on the plant dynamics (usually one-tenth the switching frequency in case of switching converters), and a phase margin of 60 • .
A brief theoretical description of the algorithm is outlined here. Once user-specified crossover frequency ω x and phase margin θ m are specified, the controller in the analog domain is expressed by [30] where the angles ϕ z , α, and β lie in the range from 0 • and 90 • . The total phase shift ∆φ, a function of these angles, introduced by the PID at ω x is given by In the three-term product controller described in Equation (36), the first term refers to the integral action; the second term signifies the phase lead contributed by the K p and K i terms; the third term captures the phase lead introduced additionally by the K d and T f terms if 0 • < α < β < 90 • and phase lag if β < α. On the satisfaction of certain conditions or assumptions, the angles α and β that are the free parameters can be selected.
Using these parameter values in Equation (35) and performing some algebraic manipulations, we obtain the following PID controller in a continuous domain.
The discrete-time PID controller obtained through the discretization of the continuoustime PID controller using Tustin transformation with T s is then given by

PID Controller with Derivative Filter-Direct Digital Design Approach
A discrete-time PID compensator with a filter can also be designed using a direct digital design (DDD) approach. In the DDD approach, a discrete-time compensator is directly constructed in the z-plane for a discretized plant. Like other cases, the considered DDD compensator is designed for Φ m ≥ 60 and ω x = ω x /10.
Inspired by the work of [31], the DDD approach-based digital PIDF controller, in general form, is given by The two complex poles of the discretized forward converter (plant) are compensated by the two complex zeros of the digital compensator by placing them exactly at a position where the converter poles exist. In order to meet the requirement of steady-state error, a pole at z = 1 is placed. This gives G DDD (z) as The gain M g and the phase ϕ g (to satisfy Φ m ) the controller needs to introduce at ω x can be calculated from the complex value of G DDD (z) at z = e jω x T s from G DDD (e jω x T s ) = 0.2548e j1.4416 , M g = 1/0.2548 = 3.9246, and ϕ g = Φ m + 180 + 82.6.
The remaining unknown parameters K i and β d of G DDD (z) can be determined by the following equations [31]: Using ω x , ϕ g (in radians), and M g in the above equations gives β d = 24.5349 and K i = 3.7979. On knowing all the parameters, G DDD (z) takes the following form: This completes the digital controller design by the DDD approach. The traditionally determined s-plane poles and zeros (or coefficients) of all the conventionally designed analog PID controllers are mapped approximately into z-plane poles and zeros (or coefficients) of digital PID controllers. Direct digital design approach-based controllers also require a discretized plant. This mapping from s-plane to z-plane thereby causes further distortions in frequency. The digital controllers only show limited performance, which can be enhanced by retuning the coefficients using the H-J pattern search method.

Digital Controller Optimization by the Hooke-Jeeves Method
Optimization of the discrete-time controllers is a multivariable unconstrained optimization problem, as no bounds are imposed on the PID controller coefficients. The Hooke-Jeeves (H-J) pattern search algorithm is employed to tune the coefficients (six in number) of conventionally designed digital controllers. The idea is to minimize the voltage error signal e(t) = V out − V ref of the compensated forward converter system (in our case) as quickly as possible to ensure better reference tracking. This is accomplished by minimizing the cost (error signal) in the form of the integral of the squared error (ISE). The cost function, in an n-multidimensional space, to be minimized thus takes the following form: The gradient-free H-J pattern search method [32], which uses a combination of exploratory moves and heuristic pattern moves iteratively, is proposed here to minimize J over n without any constraints. The algorithm performs an exploratory move in the vicinity of the current point systematically to find the best point in the n-dimensional search space. Thereafter, n such points are used to make a pattern move. The steps involved in the H-J algorithm (in the form of Algorithm 1) are outlined below. Step 1: Set an initial guess (initial point or starting point) n ) ∈ n , initial variable stepsizes ∆ i > 0 (i = 1, 2, . . . , n), a step reduction parameter α > 1, permissible error (termination parameter) ε > 0, and the maximum iterations k max . Set an iteration counter k = 0 and x (k+1) p = x (0) .
Step 2: Execute an exploratory move with the base point x (0) . Let the outcome of the exploratory move be x. If the exploratory move is a success, set x (k+1) = x and carry out Step 4; otherwise, carry out Step 3.
Step 4: Set k = k + 1 and execute the pattern move: x Step 5: Execute another exploratory move using the base point x (k+1) p . Let the result be x (k+1) .
The algorithm takes the gains/coefficients (six in number for each case) of conventionally designed discrete-time controllers (initial guess) as the input. It comes with updated coefficients as the output, resulting in better performance and robustness. No constraint is imposed on the bounds of the design variables. The parameters of the H-J algorithm set for tuning all the controllers are summarized in Table 1. The H-J algorithm, at the end of its execution, gives optimized discrete-time controllers with much improved transient response and steady-state error characteristics (see simulation results in the next section). Optimally-tuned and traditionally-tuned digital PID controller coefficients are detailed in Table 2. The number of iterations taken, and the objective function value attained finally by the optimized digital controllers are detailed in Table 3. It can be observed that the H-J method takes a different number of iterations to converge for different optimized digital controllers to achieve the same value of the objective function.   Table 3. The number of iterations taken, and the objective function value attained by the optimized controllers.

Resultant Objective Function Value
Iterations Taken for Convergence

Simulation Results and Discussion
All the simulations were performed using the MATLAB/Simulink environment. The solver of type "fixed" was used to carry out all the simulations. As already mentioned, the forward converter system is designed to convert an input voltage V in of 36 V to an output voltage V out of 12 V. The H-J pattern search algorithm is used to optimize digital controllers. The performance of digital controllers, unoptimized and optimized, for a fixed load (10 Ω) is presented in Figure 6, for all three cases. Inspection of output voltage response reveals that the optimized digital controllers offered better transient response characteristics than their unoptimized counterparts. A detailed comparison of transient response characteristics extracted from voltage responses is given in Table 4. istics than their unoptimized counterparts. A detailed comparison of transient response characteristics extracted from voltage responses is given in Table 4.
To compare the results of the deterministic H-J method with other stochastic optimization methods, a simulated annealing (SA) algorithm that mimics the thermodynamic process of metal annealing was considered. Both H-J and SA are gradient-free algorithms and solve unconstrained optimization problems well. Both the algorithms take the traditionally-tuned discrete PID controllers' coefficients as the initial point or guess.  To compare the results of the deterministic H-J method with other stochastic optimization methods, a simulated annealing (SA) algorithm that mimics the thermodynamic process of metal annealing was considered. Both H-J and SA are gradient-free algorithms and solve unconstrained optimization problems well. Both the algorithms take the traditionally-tuned discrete PID controllers' coefficients as the initial point or guess.
For simulation purposes, the most commonly used (standard) values of SA parameters were considered, which are summarized in Table 5. Table 5. Simulated annealing (SA) parameters taken for simulations.

SA Parameter Value
Cost function f ISE Initial temperature T 0 100 Annealing function Fast annealing Initial acceptance probability 1 Acceptance probability function p p(∆, T) = 1 + exp Temperature update function T T = T 0 × 0.95 k where k signifies the annealing parameter.

Reannealing interval 100
Function tolerance (termination criteria) 1 × 10 −6 Maximum function evaluations 18,000 Considering case 2, the output voltage response offered by SA showed somewhat increased overshoot and steady-state error than that of the H-J method (see Figure 7). This justifies the applicability of the H-J method to digital controllers. It can be further deduced that an unconstrained optimization problem involving fewer decision variables can be handled well by a deterministic optimization algorithm compared to a stochastic optimization algorithm. and 18 V to 12 V more quickly compared to their unoptimized counterparts. This the claim of superiority of the performance of optimized controllers over unop ones.
For the real compensated forward converter system, nonlinear effects due and DAC, and delay in the digital control loop should be taken into consideration impose adverse effects on performance [33]. For the design example, ripples in voltage ΔV were considered 1% of Vout and Vref 80% of Vmax. The detail of the digita loop nonlinearities with numeric values is summarized in Table 6.   All additional simulations were carried out using the digital PID controllers, unoptimized and optimized (by the H-J method), of case 3 to save space. The error signal became minimized more quickly in the case of the optimized compensated system (see Figure 8). This ensured better reference tracking and transient response characteristics. To gain insight into the H-J optimization method further, the cost function representing the integral of the squared error (ISE) was plotted against the iteration, as shown in Figure 9. As can be observed, with the progression of iteration, the cost function decreased monotonically and finally converged to a value of 9.5637 × 10 −6 after meeting the stopping criteria. The algorithm took 513.252875 s for 92 iterations when run on a personal computer with a Core i7 (2.10 GHz) processor and 8 GB of RAM. This minimization of cost function resulted in better convergence of the output (voltage) to the set point. Figure 10 shows that optimized digital controllers follow the changes in reference voltage from 12 V to 18 V and 18 V to 12 V more quickly compared to their unoptimized counterparts. This justifies the claim of superiority of the performance of optimized controllers over unoptimized ones.      For the real compensated forward converter system, nonlinear effects due to ADC and DAC, and delay in the digital control loop should be taken into consideration as they impose adverse effects on performance [33]. For the design example, ripples in output voltage ∆V were considered 1% of V out and V ref 80% of V max . The detail of the digital control loop nonlinearities with numeric values is summarized in Table 6.

Term Formula Value
Furthermore, optimization of the above newly-designed digital PID controller through the H-J method gives optimized digital PID controller as To justify that the optimized PID controller offers excellent load regulation compared to the unoptimized one, a change in load resistance was made from 10 Ω to 5 Ω and 5 Ω to 10 Ω. From the transient load response shown in Figure 11, it is clear that the optimized PID controller offered a reduced voltage spike and recovery time at the instant of load transient compared to the unoptimized compensator. Similarly, despite the changes in the input voltage from 36 V (nominal) to 48 V and then from 48 V to 36 V, the controllers maintained a constant output voltage of 12 V (see Figure 12). However, in the instant of a change in the input voltage, the optimized controller showed less deviation in the output voltage value and settled the output voltage to its steady-state value more quickly compared to its unoptimized counterpart. The optimized controller, thus, exhibited excellent load and line regulation.
to 10 Ω. From the transient load response shown in Figure 11, it is clear that the optimized PID controller offered a reduced voltage spike and recovery time at the instant of load transient compared to the unoptimized compensator. Similarly, despite the changes in the input voltage from 36 V (nominal) to 48 V and then from 48 V to 36 V, the controllers maintained a constant output voltage of 12 V (see Figure 12). However, in the instant of a change in the input voltage, the optimized controller showed less deviation in the output voltage value and settled the output voltage to its steady-state value more quickly compared to its unoptimized counterpart. The optimized controller, thus, exhibited excellent load and line regulation.  The tuning of all considered digital PID controllers with and without nonlinearities by the H-J search method always resulted in better control performance. This justifies the applicability and workability of the once scorned but now respectable H-J pattern search method.

Hardware-into-the-Loop Implementation
For the sake of rapid prototyping, a Xilinx System Generator (XSG), a DSP design tool from Xilinx [34], is used for implementing the discrete-time PID controller on FPGA that can be easily interfaced with Simulink through the XSG environment. Once integrated with Simulink, XSG automatically produces low-level, executable, synthesizable, and vendor-neutral VHDL code (for the control algorithm) from the Simulink modelbased generated high-level abstractions. This way, sophisticated and complex digital control algorithms are realized rapidly on FPGA compared to conventional resistor-transis- The tuning of all considered digital PID controllers with and without nonlinearities by the H-J search method always resulted in better control performance. This justifies the applicability and workability of the once scorned but now respectable H-J pattern search method.

Hardware-into-the-Loop Implementation
For the sake of rapid prototyping, a Xilinx System Generator (XSG), a DSP design tool from Xilinx [34], is used for implementing the discrete-time PID controller on FPGA that can be easily interfaced with Simulink through the XSG environment. Once integrated with Simulink, XSG automatically produces low-level, executable, synthesizable, and vendorneutral VHDL code (for the control algorithm) from the Simulink model-based generated high-level abstractions. This way, sophisticated and complex digital control algorithms are realized rapidly on FPGA compared to conventional resistor-transistor logic (RTL) development times by control design engineers without having expertise in developing VHDL code. This reduces design and testing time.
The netlist and cores are generated automatically through the Core Generator and ChipScope generator invoked by XSG. Consequently, the generated bitstream-the cosimulation FPGA configuration file for the JTAG hardware co-simulation platform-is loaded into the target device (FPGA XC7A35T-1CPG236C on Basys 3 Artix-7 FPGA board, in our case), thus implementing the digital controller on FPGA.
The optimized controller in Equation (47) is considered for the hardware into the loop (HiL) implementation and is re-written as Furthermore, in the difference equation form, the above controller takes the form For realizing the above digital controller, hardware-realizable adders/subtractors, multipliers, and delay blocks from the XSG library are used (see Figure 13). The 32-bit floating-point arithmetic (FP) is employed to realize the controller coefficients. The relatively fast FP arithmetic ensures certain accuracy for realizing coefficients. Rather than using direct programming (DP), standard programming (SP) is employed here to realize the controller. SP uses only n delay elements, whereas DP uses m + n, where m and n denote the number of zeros and poles, respectively, such that m ≤ n [35].
A synthesizable VHDL block representing the hardware co-simulation library is then generated automatically and is loaded into the Artix-7 board (see Figure 13). For downloading the bitstream, JTAG communication between Simulink (on PC) and hardware platform (Artix-7 FPGA board) for a supported board is performed. This way, hardwaresoftware co-simulation through JTAG is accomplished to close the digital control loop.
After introducing hardware into the control loop, it has been observed that the XSGbased compensated system displays almost the same output voltage response as that of the Simulink-based compensated system, as shown in Figure 14, thus validating the HiL implementation. This is quite understandable, as the floating-point data format for digital controller coefficients has been used just like the "double" type data of Simulink. the controller. SP uses only n delay elements, whereas DP uses m + n, where m and n denote the number of zeros and poles, respectively, such that m ≤ n [35]. A synthesizable VHDL block representing the hardware co-simulation library is then generated automatically and is loaded into the Artix-7 board (see Figure 13). For downloading the bitstream, JTAG communication between Simulink (on PC) and hardware platform (Artix-7 FPGA board) for a supported board is performed. This way, hardwaresoftware co-simulation through JTAG is accomplished to close the digital control loop.
After introducing hardware into the control loop, it has been observed that the XSGbased compensated system displays almost the same output voltage response as that of the Simulink-based compensated system, as shown in Figure 14, thus validating the HiL implementation. This is quite understandable, as the floating-point data format for digital controller coefficients has been used just like the "double" type data of Simulink.

Conclusions
In this paper, the Hooke Jeeves search algorithm was successfully applied to tune the coefficients of discrete-time PID controllers to enhance the performance of the compensated forward DC-DC converter. Three types of PID controllers were designed on the basis of frequency response characteristics (crossover frequency and phase margin) in the

Conclusions
In this paper, the Hooke Jeeves search algorithm was successfully applied to tune the coefficients of discrete-time PID controllers to enhance the performance of the compensated forward DC-DC converter. Three types of PID controllers were designed on the basis of frequency response characteristics (crossover frequency and phase margin) in the s-plane, which were then mapped into the z-plane using transformation techniques such as Tustin, backward Euler, and (simple) mapping. The digital redesign approach based designed digital PID controllers show only nominal performance, which further gets deteriorated due to frequency distortions during mapping and nonlinearities such as ADC and DAC, sampling and hold effects, loop delay, and so on. Based on our findings, we observe that when the H-J pattern search method is applied to these conventionally-designed digital controllers (with and without nonlinear elements) exhibiting limited performance, it finetunes the controller coefficients intelligently by minimizing the cost function rapidly, thus ensuring the near-optimal solution. For all the considered cases, better control performance is achieved. This clearly indicates that the H-J method employs pattern search efficiently to make the iterative process fast-convergent. Hardware-into-the-loop implementation is also carried out for rapid prototyping.