A Frequency Estimation Method Based on a Revised 3-Level Discrete Fourier Transform with an Estimation Delay Reduction Technique

: In this paper, a frequency estimation method based on a revised three-level discrete Fourier transform (DFT) with an estimation delay reduction technique is proposed. First, the input signal passes through a sine ﬁlter twice to improve the ability to decrease the level of harmonics and inter-harmonics. Secondly, the second sine-ﬁltered signal is decomposed into two orthogonal components by DFT with a hamming window to enhance the ability to suppress inter-harmonics. The frequency of the signal is derived using orthogonal components without a zero-crossing problem, which can cause numerical estimation error. This process causes the estimation delay of three cycles and three samples in total. Therefore, the estimation delay reduction technique compensating for the phase delay of the phasor is proposed. To evaluate the performance of the proposed method, several frequency changes were considered when the test signals were generated according to the IEEE PMU Standards C37.118.1a-2014. The performance of the proposed method was also evaluated under dynamic and fault conditions in a ﬁve-bus transmission system modeled with PSCAD / EMTDC. The simulation results show that the proposed method accurately estimated the frequency of the signal. investigation,


Introduction
In electric power grids, frequency is one of the most important quantities, because frequency deviation is a good indicator of abnormal system operating conditions, so any deviation in power system frequency should be closely observed. For load shedding, islanding detection of distributed generators, and control of energy storage systems in the power grid, many real-time applications require accurate and fast estimation of power system frequency because an erroneous estimation may eventually result in a catastrophic grid failure due to inadequate or delayed load shedding [1].
Many techniques for more accurate frequency estimation have been proposed. The use of zero-crossing detection and calculation of the number of cycles that occur during a predetermined time interval is a simple and well-known methodology [2,3]. However, an actual signal that is measured in a real power system might contain harmonics. Since a huge error can be caused by distortion of a signal due to harmonics, modified zero-crossing methods have also been studied [4,5]. Phase-locked loop (PLL) techniques have been considered state-of-the-art methodology and widely used for synchronization [6][7][8][9]. PLL-based methods show good performance, but the implementation of these algorithms is complex, and the dynamic response is not fast. Besides, many approaches have been studied to estimate frequency in the scientific literature, such as recursive [10,11], Kalman filters [12,13], least-squares [1,[14][15][16], artificial neural networks (ANN) [17,18], Prony [19,20], the

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The revised 3LDFT can improve harmonic and inter-harmonic suppression performance.

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The proposed frequency estimation method by adding four orthogonal components helps to suppress harmonics and inter-harmonics, which increases the frequency estimation accuracy. However, a potential weakness of the proposed method is the estimation delay error caused by three cycles and three samples. • Therefore, as a final step, the estimation delay error would be decreased tremendously using the estimation delay reduction technique, compensating for the phase delay of the phasor.
Several simulation results obtained using computer and PSCAD/EMTDC-generated signals have demonstrated the performance and effectiveness of the proposed method. The remainder of this paper is organized as follows. Section 2 contains details on the methodology for frequency estimation. Section 3 provides simulation results to demonstrate the performance of the proposed method. The result of the proposed method was compared with those of the 3LDFT and dual second-order generalized integrator(DSOGI)-PLL using computer-generated signals created according to IEEE PMU Standards C37.118.1a-2014 [28] and generated by PSCAD/EMTDC, which were used to verify the accuracy of the proposed method as well. Finally, the conclusions of the study are summarized in Section 4.

Sine-Filtered Signals
where f is the reference frequency, v m is the amplitude, θ is the initial phase, f 0 is the nominal frequency, N is the number of samples per cycle, and f s = f 0 N. First of all, the input signal passes through a sine filter instead of a cosine filter to suppress harmonics and inter-harmonics that might be included in the input signal of a power system. Theoretically, this filtering process brings about a delay of one cycle. The respective coefficients of the cosine and sine filters are as follows: where Z c [k] and Z s [k] are the coefficients of the cosine and sine filter respectively. The input signal may be decomposed into two components, each orthogonal in phase, by the use of two finite impulse response (FIR) filters based upon sine and cosine impulse responses. This technique is actually identical to the discrete Fourier transform evaluated for the fundamental component [21]. The magnitude and phase response of the cosine and sine filters can be respectively expressed as where Z c ( f ) and ∠Z c ( f ) is the magnitude and phase response of the cosine filter, and Z s ( f ) and ∠Z s ( f ) is the magnitude and phase response of the sine filter. The magnitude response for each filter is illustrated in Figure 1. The sine filter can decrease the level of the harmonics and inter-harmonics more effectively than the cosine filter, as shown in Figure 1, which is the reason why it is used in place of the cosine filter in this paper. The first sine-filtered signal can be obtained as To reduce the negative influence of harmonics and inter-harmonics on the accuracy of the proposed method, the sine filter is applied to the first sine-filtered signal again, which should give rise to an additional delay of one cycle. The second sine-filtered signal can be expressed as where K ss = −K s Z s ( f ) , θ cc = θ c + ∠Z c ( f ) and v ss [n] is the second sine-filtered signal. After that, the second sine-filtered signal is decomposed into two orthogonal components through DFT, which, in other words, means it passes through the cosine and sine filters once more. The entire filtering procedure is described in Figure 2. and ∠ ( ) is the magnitude and phase response of the sine filter. The magnitude response for each filter is illustrated in Figure 1. The sine filter can decrease the level of the harmonics and interharmonics more effectively than the cosine filter, as shown in Figure 1, which is the reason why it is used in place of the cosine filter in this paper. The first sine-filtered signal can be obtained as where K = | ( )|, = + ∠ ( ) and [ ] is the first sine filtered-signal.
To reduce the negative influence of harmonics and inter-harmonics on the accuracy of the proposed method, the sine filter is applied to the first sine-filtered signal again, which should give rise to an additional delay of one cycle. The second sine-filtered signal can be expressed as where K = −K | ( )|, [ ] is the second sine-filtered signal.
After that, the second sine-filtered signal is decomposed into two orthogonal components through DFT, which, in other words, means it passes through the cosine and sine filters once more. The entire filtering procedure is described in Figure 2. As previously mentioned, the second sine-filtered signal is divided into real and imaginary parts.
where [ ] and [ ] are the real and imaginary parts of the input signal, K = K | ( )|, This filtering procedure can be considered as the DFT applied three times, which is similar to the 3LDFT method presented in [26]. As a result, the three-cycle delay comes about, which becomes a part of the estimation delay. A diagram of the revised 3LDFT is shown in Figure 3. As previously mentioned, the second sine-filtered signal is divided into real and imaginary parts.
where v ssc [n] and v sss [n] are the real and imaginary parts of the input signal, This filtering procedure can be considered as the DFT applied three times, which is similar to the 3LDFT method presented in [26]. As a result, the three-cycle delay comes about, which becomes a part of the estimation delay. A diagram of the revised 3LDFT is shown in Figure 3.  Each imaginary part from the first and second levels is used as the input signal in each next step, and it should be noted that the real part is only calculated at the third level. Therefore, in the DFT process, the revised 3LDFT method has half the computational burden of the 3LDFT. At the third level of the DFT, a hamming window works as a smoothing technology to improve the accuracy of  Each imaginary part from the first and second levels is used as the input signal in each next step, and it should be noted that the real part is only calculated at the third level. Therefore, in the DFT process, the revised 3LDFT method has half the computational burden of the 3LDFT. At the third level of the DFT, a hamming window works as a smoothing technology to improve the accuracy of the frequency estimation. The coefficient of the hamming window is given by

The Novel Frequency Estimation Method
Now that there are only a few harmonics left in the orthogonal components thanks to the revised 3LDFT, most of the signal distortion will disappear, which means that the frequency estimation error is considerably decreased. In [25], a frequency estimation method by magnifying the harmonics and inter-harmonics using the difference between the neighboring input data was suggested. However, the difference might cause errors because the difference can be regarded as a high-pass filter. Hence, another frequency estimation method based on addition using four orthogonal components is proposed in this paper. Using the trigonometric identity cos(A) + cos(B) = 2cos((A + B)/2)cos((A − B)/2) yields the following equation: The following expression can also be derived by using the same trigonometric identity: The following expression can be derived in a similar manner: Energies 2020, 13, 2256 6 of 16 Next, the frequency estimation equation can be obtained by dividing (14) by (13) as follows: Similarly, another frequency estimation equation can also be obtained as Both Equations (17) and (18) introduce the zero-crossing problem since v ssc [n] and v sss [n] are instantaneous values. To solve this zero-crossing problem, the following equation is proposed: As a result, the frequency of the input signal f cal [n] is calculated using Equation (20), but it may lead to a delay of three cycles and three samples.

The Estimation Delay Reduction Technique
As previously stated, Equation (20) results in the estimation delay of three cycles and three samples. The estimation delay can be anticipated using Equation (5) which means phase response of the phasor. The Equation (5) represents how the phase of the phasor is delayed. Since Equation (5) is a frequency-dependent function, the phase delay of the phasor can be obtainable by using the previously calculated frequency. In the proposed method, a moving average filter with the length of one cycle is applied to achieve a stable response as shown in Equation (21).
The phase delay of the phasor can be calculated by substituting f avg [n] for f in Equation (5). Therefore, the phase delay of three cycles and three samples can be also determined from Equation (22) as follows: where θ delay [n] is the phase delay of three cycles and three samples. The phase delay is the phase difference between the ideal phasor of the discrete-time input signal and the delayed phasor. Figure 4 illustrates what the phase delay means.
The phase delay of the phasor can be calculated by substituting [ ] for in Equation (5). Therefore, the phase delay of three cycles and three samples can be also determined from Equation (22) as follows: where [ ] is the phase delay of three cycles and three samples.
The phase delay is the phase difference between the ideal phasor of the discrete-time input signal and the delayed phasor. Figure 4 illustrates what the phase delay means. where ( ) is the ideal phasor of the discrete-time input signal whose phase delay is not included at all, [ ] is the delayed phasor, and is the sampling interval, which is the same as 1 ⁄ .
Since the phase delay is related to the estimation delay, the estimation delay can be got rid of by compensating for the phase delay of three cycles and three samples as follows: This methodology can be easily implemented by using Euler's formula as  Where v m e j(2π f nT s +θ) is the ideal phasor of the discrete-time input signal whose phase delay is not included at all, v m e j(2π f nT s +θ+θ delay [n]) is the delayed phasor, and T s is the sampling interval, which is the same as 1/ f s .
Since the phase delay is related to the estimation delay, the estimation delay can be got rid of by compensating for the phase delay of three cycles and three samples as follows: where V ssc [n] and V sss [n] are the revised orthogonal components. Then, the frequency, f est [n], whose estimation delay is almost eliminated, can be estimated by Figure 5 shows the flowchart of the proposed method. The proposed method starts with collecting the input voltage signal with the sampling frequency of 3840 Hz (i.e., 64 samples per cycle in a 60 Hz system). The sampled signal is decomposed into the two orthogonal components through the revised 3LDFT described in Section 2.1. Equation (20) is used to calculate the frequency f cal [n], in which the estimation delay of the three cycles and three samples is included.

A Flowchart of the Proposed Method
Afterwards, f avg [n] is obtained using Equation (21) to calculate the phase delay of the phasor. Then, the phase delay is decreased through Equations (22) and (24). Finally, the frequency with the reduced estimation delay is estimated by using, V ssc [n] and V sss [n], as in Equation (25).  Figure 5 shows the flowchart of the proposed method. The proposed method starts with collecting the input voltage signal with the sampling frequency of 3840 Hz (i.e. 64 samples per cycle in a 60 Hz system). The sampled signal is decomposed into the two orthogonal components through the revised 3LDFT described in Section 2.1. Equation (20) is used to calculate the frequency [ ], in which the estimation delay of the three cycles and three samples is included. Afterwards, [ ] is obtained using Equation (21) to calculate the phase delay of the phasor.

A Flowchart of the Proposed Method
Then, the phase delay is decreased through Equations (22) and (24). Finally, the frequency with the reduced estimation delay is estimated by using, [ ] and [ ], as in Equation (25).

Performance Evaluation
To verify the performance of the proposed method, computer-generated signals were used, and these signals were made according to IEEE PMU Standards C37.118.1a-2014. The PSCAD/EMTDC signal obtained in the modified IEEE five-bus 345 kV transmission system [26] was also used to test the accuracy of the proposed method under the dynamics and fault condition. The results of the proposed method were compared with those of the 3LDFT [26] and the DSOGI-PLL method [8].

Using Computer Generated Signals
With reference to [26] and IEEE C37.118.1a-2014, the three types of computer-generated frequency variation signals were created using where is positive ramp frequency variation, is negative ramp frequency variation, and is sinusoidal frequency variation.

Performance Evaluation
To verify the performance of the proposed method, computer-generated signals were used, and these signals were made according to IEEE PMU Standards C37.118.1a-2014. The PSCAD/EMTDC signal obtained in the modified IEEE five-bus 345 kV transmission system [26] was also used to test the accuracy of the proposed method under the dynamics and fault condition. The results of the proposed method were compared with those of the 3LDFT [26] and the DSOGI-PLL method [8].

Using Computer Generated Signals
With reference to [26] and IEEE C37.118.1a-2014, the three types of computer-generated frequency variation signals were created using where f 1 is positive ramp frequency variation, f 2 is negative ramp frequency variation, and f 3 is sinusoidal frequency variation.
In accordance with IEEE C37.118.1a-2014, the positive ramp test starts at 58 Hz and ramps up to 62 Hz, whereas the negative ramp test starts at 62 Hz and ramps down to 58 Hz [28]. To evaluate the accuracy of the proposed method, the frequency estimation error is calculated as where Error is the frequency estimation error and expressed as both [Hz] and [%].

Tests for Basic Signals
The input signal was generated using Equation (1) with Equations (26)- (28). Figure 6 shows that the proposed method was able to estimate the frequency much more accurately than the 3LDFT and DSOGI-PLL under the positive ramp variation condition. Since the estimation delay of the proposed method was considerably eliminated, the frequency estimation error was close to zero. On the other hand, the 3LDFT had a frequency estimation error of 0.041 Hz due to the five cycles and DSOGI-PLL also had a frequency estimation error of 0.032 Hz. The proposed method had a slightly slow time response at the beginning of the frequency variation but was faster enough than Energies 2020, 13, 2256 9 of 16 3LDFT and DSOGI-PLL as seen in Figure 6c. The proposed method had a small overshoot at the end of the frequency variation, as shown in Figure 6b.
In accordance with IEEE C37.118.1a-2014, the positive ramp test starts at 58 Hz and ramps up to 62 Hz, whereas the negative ramp test starts at 62 Hz and ramps down to 58 Hz [28]. To evaluate the accuracy of the proposed method, the frequency estimation error is calculated as where Error is the frequency estimation error and expressed as both [Hz] and [%].

Tests for Basic Signals
The input signal was generated using Equation (1) Figure 6 shows that the proposed method was able to estimate the frequency much more accurately than the 3LDFT and DSOGI-PLL under the positive ramp variation condition. Since the estimation delay of the proposed method was considerably eliminated, the frequency estimation error was close to zero. On the other hand, the 3LDFT had a frequency estimation error of 0.041 Hz due to the five cycles and DSOGI-PLL also had a frequency estimation error of 0.032 Hz. The proposed method had a slightly slow time response at the beginning of the frequency variation but was faster enough than 3LDFT and DSOGI-PLL as seen in Figure 6c. The proposed method had a small overshoot at the end of the frequency variation, as shown in Figure 6b. The test results under the negative ramp frequency variation condition are shown in Figure 7. Unlike 3LDFT and DSOGI-PLL, the proposed method estimated the frequency very accurately with reduced estimation delay, so the frequency estimation error was close to zero as seen in Figure 7b. The test results under the negative ramp frequency variation condition are shown in Figure 7. Unlike 3LDFT and DSOGI-PLL, the proposed method estimated the frequency very accurately with reduced estimation delay, so the frequency estimation error was close to zero as seen in Figure 7b.

Tests for Harmonics and Inter-Harmonics
To investigate the performance of the proposed method under harmonic distortion condition, the following input signal, whose THD is 31.6%, was considered. The percentage of the harmonics are listed in Table 1. Percentage 100 20 20 10 10 Figures 9 and 10 show the frequency estimation results in the presence of the harmonics. The proposed method and 3LDFT are seen to efficiently remove the adverse influence of the harmonics because of the triple use of the DFT. Besides, the estimation delay of the proposed method was successfully eliminated under the harmonic conditions. The proposed method resulted in slight errors when the reference frequency was either at steady state or had deviated from the nominal frequency. However, the proposed method showed much better results than the others. The DSOGI-PLL demonstrated the worst performance under the harmonic conditions among the methods compared.

Tests for Harmonics and Inter-Harmonics
To investigate the performance of the proposed method under harmonic distortion condition, the following input signal, whose THD is 31.6%, was considered. The percentage of the harmonics are listed in Table 1.  Figures 9 and 10 show the frequency estimation results in the presence of the harmonics. The proposed method and 3LDFT are seen to efficiently remove the adverse influence of the harmonics because of the triple use of the DFT. Besides, the estimation delay of the proposed method was successfully eliminated under the harmonic conditions. The proposed method resulted in slight errors when the reference frequency was either at steady state or had deviated from the nominal frequency. However, the proposed method showed much better results than the others. The DSOGI-PLL demonstrated the worst performance under the harmonic conditions among the methods compared. To investigate the performance of the proposed method under harmonics and inter-harmonics condition, the following input signal was considered. The percentage of the harmonics and interharmonics are listed in Table 2.  The estimated frequency in the presence of the harmonics and inter-harmonics is shown in Figure 11 and 12. Compared with the previous simulation results in Figures 9 and 10, inter-harmonics certainly resulted in the adverse effect on all three of method. Even though the effect of interharmonics on the frequency estimation created some error, the proposed method successfully eliminated the estimation delay even under the inter-harmonic conditions. Therefore, the proposed method demonstrated the improved frequency estimation results as shown in Figure 11   To investigate the performance of the proposed method under harmonics and inter-harmonics condition, the following input signal was considered. The percentage of the harmonics and interharmonics are listed in Table 2.  The estimated frequency in the presence of the harmonics and inter-harmonics is shown in Figure 11 and 12. Compared with the previous simulation results in Figures 9 and 10, inter-harmonics certainly resulted in the adverse effect on all three of method. Even though the effect of interharmonics on the frequency estimation created some error, the proposed method successfully eliminated the estimation delay even under the inter-harmonic conditions. Therefore, the proposed method demonstrated the improved frequency estimation results as shown in Figure 11   To investigate the performance of the proposed method under harmonics and inter-harmonics condition, the following input signal was considered. The percentage of the harmonics and inter-harmonics are listed in Table 2. The estimated frequency in the presence of the harmonics and inter-harmonics is shown in Figures 11 and 12. Compared with the previous simulation results in Figures 9 and 10, inter-harmonics certainly resulted in the adverse effect on all three of method. Even though the effect of inter-harmonics on the frequency estimation created some error, the proposed method successfully eliminated the estimation delay even under the inter-harmonic conditions. Therefore, the proposed method demonstrated the improved frequency estimation results as shown in Figures 11 and 12. The DSOGI-PLL demonstrated the worst performance under the harmonic conditions.

Using the PSCAD/EMTDC-Generated Signals
The performance of the proposed algorithm was also evaluated under several sets of conditions in a modified IEEE five-bus transmission system modeled by PSCAD/EMTDC as shown in Figure 13. The modified five-bus system modeled according to [26] was composed of two synchronous generators, and total electrical loads with a capacity and power factor of around 167.7 MVA and 0.984, respectively, were connected to the transmission system. As mentioned previously, increasing the total load of the power system, which causes the dynamic condition, and a single line-to-ground fault were applied to create frequency deviation situations. In all cases, signals were acquired at 640 samples per cycle in a 60 Hz system and

Using the PSCAD/EMTDC-Generated Signals
The performance of the proposed algorithm was also evaluated under several sets of conditions in a modified IEEE five-bus transmission system modeled by PSCAD/EMTDC as shown in Figure 13. The modified five-bus system modeled according to [26] was composed of two synchronous generators, and total electrical loads with a capacity and power factor of around 167.7 MVA and 0.984, respectively, were connected to the transmission system. As mentioned previously, increasing the total load of the power system, which causes the dynamic condition, and a single line-to-ground fault were applied to create frequency deviation situations. In all cases, signals were acquired at 640 samples per cycle in a 60 Hz system and

Using the PSCAD/EMTDC-Generated Signals
The performance of the proposed algorithm was also evaluated under several sets of conditions in a modified IEEE five-bus transmission system modeled by PSCAD/EMTDC as shown in Figure 13. The modified five-bus system modeled according to [26] was composed of two synchronous generators, and total electrical loads with a capacity and power factor of around 167.7 MVA and 0.984, respectively, were connected to the transmission system.

Using the PSCAD/EMTDC-Generated Signals
The performance of the proposed algorithm was also evaluated under several sets of conditions in a modified IEEE five-bus transmission system modeled by PSCAD/EMTDC as shown in Figure 13. The modified five-bus system modeled according to [26] was composed of two synchronous generators, and total electrical loads with a capacity and power factor of around 167.7 MVA and 0.984, respectively, were connected to the transmission system. As mentioned previously, increasing the total load of the power system, which causes the dynamic condition, and a single line-to-ground fault were applied to create frequency deviation As mentioned previously, increasing the total load of the power system, which causes the dynamic condition, and a single line-to-ground fault were applied to create frequency deviation situations. In all cases, signals were acquired at 640 samples per cycle in a 60 Hz system and preprocessed by a second-order Butterworth low-pass filter with a gain of 0.1 at the stop-band cut-off frequency of 1920 Hz in order to get rid of aliasing errors. Afterwards, the filtered signals were used as the input signal of each algorithm after downsampling to 64 samples per cycle. Figure 14 shows the schematic diagram of down-sampling processing.
Energies 2020, 13, x FOR PEER REVIEW 14 of 16 preprocessed by a second-order Butterworth low-pass filter with a gain of 0.1 at the stop-band cutoff frequency of 1920 Hz in order to get rid of aliasing errors. Afterwards, the filtered signals were used as the input signal of each algorithm after downsampling to 64 samples per cycle. Figure 14 shows the schematic diagram of down-sampling processing.

Dynamic Condition
First, approximately 20% of the total load around 34 MVA was connected to the #2 bus to simulate dynamic conditions. As soon as the additional load was connected, the magnitude and frequency of the signal were changed concurrently, as shown in Figure 15. The envelope of the terminal voltage of #1 synchronous machine and the reference frequency of the input signal are shown in Figure 15a and 16b, respectively. The reference frequency corresponded to the rotor speed obtained from the PSCAD/EMTDC simulation [26]. Simulation results depicted in Figures 15c and 15d indicate that the proposed method was able to track the reference frequency much more accurately than the 3LDFT and DSOGI-PLL, although a spike up to 0.413 Hz occurred after the additional load was connected at 0 sec.

Dynamic Condition
First, approximately 20% of the total load around 34 MVA was connected to the #2 bus to simulate dynamic conditions. As soon as the additional load was connected, the magnitude and frequency of the signal were changed concurrently, as shown in Figure 15. The envelope of the terminal voltage of #1 synchronous machine and the reference frequency of the input signal are shown in Figures 15a and  16b situations. In all cases, signals were acquired at 640 samples per cycle in a 60 Hz system and preprocessed by a second-order Butterworth low-pass filter with a gain of 0.1 at the stop-band cutoff frequency of 1920 Hz in order to get rid of aliasing errors. Afterwards, the filtered signals were used as the input signal of each algorithm after downsampling to 64 samples per cycle. Figure 14 shows the schematic diagram of down-sampling processing.

Dynamic Condition
First, approximately 20% of the total load around 34 MVA was connected to the #2 bus to simulate dynamic conditions. As soon as the additional load was connected, the magnitude and frequency of the signal were changed concurrently, as shown in Figure 15. The envelope of the terminal voltage of #1 synchronous machine and the reference frequency of the input signal are shown in Figure 15a and 16b, respectively. The reference frequency corresponded to the rotor speed obtained from the PSCAD/EMTDC simulation [26]. Simulation results depicted in Figures 15c and 15d indicate that the proposed method was able to track the reference frequency much more accurately than the 3LDFT and DSOGI-PLL, although a spike up to 0.413 Hz occurred after the additional load was connected at 0 sec. Secondly, the single line-to-ground fault was simulated at 0 sec and cleared at 0.1 s, which means the fault lasted for 0.1 s. A fault inception angle of 90° was considered to create the maximum amount of noise. Figure 16a and 16b show the magnitude of the terminal voltage of the #1 synchronous machine and reference frequency, respectively, while Figure 16c and 16d show the respective results of each method using the PSCAD/EMTDC-generated signal. There was a large spike up after clearing the fault, as shown in Figure 16c. Apart from a period of transient errors, the proposed method estimated the frequency of the signal more closely than the 3LDFT and DSOGI-PLL, as shown in Figure 16d.

Conclusions
In this paper, a frequency estimation method based on revised 3LDFT with an estimation delay reduction technique was suggested. The revised 3LDFT, which uses hamming window as a smoothing technology, shows an outstanding ability to suppress the adverse influence of the harmonics and inter-harmonics. The frequency estimation method uses two orthogonal components obtained by the revised 3LDFT to estimate the frequency without the zero-crossing problem but induces an estimation delay caused by three cycles and three samples. To overcome this drawback, an estimation delay reduction technique was proposed. The estimation delay can be considerably eliminated by compensating the phase delay of the phasor, which is calculated by the phase response function of the phasor.
To evaluate the performance of the proposed method, computer-generated signals with harmonics and inter-harmonics were used. The results were compared to those of the previously reported DFT-based and PLL-based method. The results show that the proposed method was able to estimate the frequency accurately, even under harmonics and inter-harmonics polluted conditions. The reference frequency corresponded to the rotor speed obtained from the PSCAD/EMTDC simulation [26]. Simulation results depicted in Figure 15c,d indicate that the proposed method was able to track the reference frequency much more accurately than the 3LDFT and DSOGI-PLL, although a spike up to 0.413 Hz occurred after the additional load was connected at 0 sec.

The Single Line-to-Ground Fault
Secondly, the single line-to-ground fault was simulated at 0 sec and cleared at 0.1 s, which means the fault lasted for 0.1 s. A fault inception angle of 90 • was considered to create the maximum amount of noise. Figure 16a,b show the magnitude of the terminal voltage of the #1 synchronous machine and reference frequency, respectively, while Figure 16c,d show the respective results of each method using the PSCAD/EMTDC-generated signal. There was a large spike up after clearing the fault, as shown in Figure 16c. Apart from a period of transient errors, the proposed method estimated the frequency of the signal more closely than the 3LDFT and DSOGI-PLL, as shown in Figure 16d.

Conclusions
In this paper, a frequency estimation method based on revised 3LDFT with an estimation delay reduction technique was suggested. The revised 3LDFT, which uses hamming window as a smoothing technology, shows an outstanding ability to suppress the adverse influence of the harmonics and inter-harmonics. The frequency estimation method uses two orthogonal components obtained by the revised 3LDFT to estimate the frequency without the zero-crossing problem but induces an estimation delay caused by three cycles and three samples. To overcome this drawback, an estimation delay reduction technique was proposed. The estimation delay can be considerably eliminated by compensating the phase delay of the phasor, which is calculated by the phase response function of the phasor.
To evaluate the performance of the proposed method, computer-generated signals with harmonics and inter-harmonics were used. The results were compared to those of the previously reported DFT-based and PLL-based method. The results show that the proposed method was able to estimate the frequency accurately, even under harmonics and inter-harmonics polluted conditions. The PSCAD/EMTDC-generated signals were also used to test the performance under the disturbance, including the load increasing and the single line-to-ground fault. As for the results of comparing the proposed method with the previously reported DFT-based and PLL-based method, it can be seen that the proposed method is much more effective for estimating the frequency accurately.