A Generic Multi-Level SVM Scheme Based on Two-Level SVM for n -Level Converters

: Multi-level converters are widely used in various industrial applications. Among various space vector modulation (SVM) schemes, the multi-level SVM scheme based on two-level space vector pulse width modulation (SVPWM) is recognised as a simpliﬁed multi-level SVM scheme, which can reduce the computation complexity. However, this scheme is still complicated when the number of the voltage levels is large. This paper proposes a modiﬁed SVM scheme that can further simplify the multi-level SVM scheme based on two-level SVPWM. The proposed SVM scheme can directly determine the two-level hexagon where the reference voltage vector is located by calculating a simple formula. The whole modulation process can be completed by only three steps. Meanwhile, the proposed method is generic for any n -level converter without adding much calculation, which greatly simpliﬁes the modulation process. Experimental results have been provided, which verify the e ﬀ ectiveness and generality of the proposed SVM scheme for two types of multi-level converters.


Introduction
Compared to the two-level converter, multi-level converters demonstrate clear advantages such as higher voltage operation capability, lower voltage stress (dv/dt), output harmonics and switching loss, higher efficiency, etc. [1][2][3]. However, there are also challenges associated with multi-level converters such as increased control and modulation complexity, the need for capacitor voltage balancing, reliability challenges, etc. [4], and this paper will focus on the modulation aspect.
Common multi-level space vector modulation (SVM) schemes can be classified into two typical categories: (1) carrier-based sinusoidal pulse width modulation (SPWM), including phase disposition PWM (PD-PWM) [5][6][7] and phase shifted PWM (PS-PWM) [8][9][10]; and (2) space vector PWM (SVPWM) [11]. With the appropriate zero-sequence signal injection, carrier based PWM is equivalent to SVPWM [12][13][14]. Both the two methods can achieve a high DC-link voltage utilization ratio, and the relationship between control objectives-such as neutral point voltage balancing and common mode voltage, and the space vectors and zero-sequence-can be well defined. Therefore, SPWM and SVPWM can have the same performance for multi-level converters. This paper mainly focuses on multi-level SVM.
For multi-level SVM, the research is mainly focused on two aspects: application and implementation. It is well known that multi-level SVM has redundant voltage space vectors, which have different effects on the multi-level converters. The converters can be controlled to output the required performance through selecting the appropriate voltage space vectors. Therefore, multi-level SVM has various applications, such as common-mode voltage reduction [15,16], harmonic suppression [17,18], balancing capacitor voltage [19], reducing switching losses [20], conferring fault tolerance [21], etc.
However, when this algorithm is applied in converters with higher number of levels, the multiple comparisons still require significant computation resources.
For the multi-level SVM scheme based on two-level SVPWM, the problem is that the process of decomposing V ref is too complex and difficult to implement as the number of levels increases. In order to solve this issue, this paper proposes a new, generic, simplified multi-level SVM. This scheme can easily and effectively decompose V ref into the two-level hexagon, and the whole modulation process can be achieved by three simple steps. The proposed scheme has the following salient advantages compared with existing the methods mentioned above: (1) The center of the two-level hexagon where V ref is located can be directly expressed through a simple calculation. The decomposition does not require the layer calculations. (2) No lookup table or coordinate transformation are required.
(3) For any n-level converter, the whole modulation process can be implemented within three-step calculations without adding much calculation, regardless of the number of levels.
The rest of this paper is organized as follows: Section 2 introduces the space vector diagram of the five-level converter and the coordinate normalization; Section 3 presents the proposed multi-level SVM scheme; Section 4 shows experimental results for two kinds of multi-level inverter, which validate the effectiveness of the proposed method; and Section 5 concludes the paper.

Space Voltage Vector Distribution
A five-level cascaded H-bridge inverter (CHB) as shown in Figure 1 is employed as an example for evaluation. Figure 2 shows the space vector diagram of the five-level converter.

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Vref is located. However, when this algorithm is applied in converters with higher number of levels, the multiple comparisons still require significant computation resources.
For the multi-level SVM scheme based on two-level SVPWM, the problem is that the process of decomposing Vref is too complex and difficult to implement as the number of levels increases. In order to solve this issue, this paper proposes a new, generic, simplified multi-level SVM. This scheme can easily and effectively decompose Vref into the two-level hexagon, and the whole modulation process can be achieved by three simple steps. The proposed scheme has the following salient advantages compared with existing the methods mentioned above: (1) The center of the two-level hexagon where Vref is located can be directly expressed through a simple calculation. The decomposition does not require the layer calculations. (2) No lookup table or coordinate transformation are required.
(3) For any n-level converter, the whole modulation process can be implemented within three-step calculations without adding much calculation, regardless of the number of levels.
The rest of this paper is organized as follows: Section 2 introduces the space vector diagram of the five-level converter and the coordinate normalization; Section 3 presents the proposed multi-level SVM scheme; Section 4 shows experimental results for two kinds of multi-level inverter, which validate the effectiveness of the proposed method; and Section 5 concludes the paper.

Space Voltage Vector Distribution
A five-level cascaded H-bridge inverter (CHB) as shown in Figure 1 is employed as an example for evaluation. Figure 2 shows the space vector diagram of the five-level converter.      Figure 3 shows the coordinate components of the voltage space vectors in the a-b-c coordinate system. The coordinate components V a , V b , V c are per unit values after division by V dc , and V dc is the DC-link voltage of each cell. Then, the whole hexagon can be divided into six sectors (I-VI), as shown in Figure 3.  Figure 3 shows the coordinate components of the voltage space vectors in the a-b-c coordinate system. The coordinate components Va, Vb, Vc are per unit values after division by Vdc, and Vdc is the DC-link voltage of each cell. Then, the whole hexagon can be divided into six sectors (I-VI), as shown in Figure 3. From Figure 3, it can be seen that the coordinate components of the voltage space vectors are symmetrically distributed in the six sectors. Therefore, in order to simplify the calculation process, the voltage space vectors in other sectors can be normalized to Sector I by interchanging the coordinate components [36]. Figure 4 shows the symmetry of the vector distributions (θ1 = θ2 = θ3 = θ4 = θ5 = θ6). The voltage space vectors in two adjacent sectors are symmetrically distributed with respect to the axis on which the two adjacent sectors coincide. For example, the voltage space vectors in Sectors I and II are symmetrically distributed with respect to the c-axis. Therefore, it is only From Figure 3, it can be seen that the coordinate components of the voltage space vectors are symmetrically distributed in the six sectors. Therefore, in order to simplify the calculation process, the voltage space vectors in other sectors can be normalized to Sector I by interchanging the coordinate components [36]. Figure 4 shows the symmetry of the vector distributions (θ 1 = θ 2 = θ 3 = θ 4 = θ 5 = θ 6 ). The voltage space vectors in two adjacent sectors are symmetrically distributed with respect to the axis on which the two adjacent sectors coincide. For example, the voltage space vectors in Sectors I and II are symmetrically distributed with respect to the c-axis. Therefore, it is only necessary to interchange the coordinate components of the a-axis and b-axis to normalize the voltage space vectors of Sector II to Sector I, such as if the coordinate is (1/3, 4/3, −5/3) in Sector II, then the equivalent coordinate is (4/3, 1/3, −5/3) after normalizing it to Sector I. Similarly, the voltage space vectors in other sectors can also be normalized to Sector I according to this method. The equivalent coordinate components (V a1 , V b1 , V c1 ) of the voltage space vectors in Sector I are shown in Table 1. This coordinate normalization only needs to interchange the coordinate components and is easy to implement.
Energies 2020, 13, 2143 5 of 18 necessary to interchange the coordinate components of the a-axis and b-axis to normalize the voltage space vectors of Sector II to Sector I, such as if the coordinate is (1/3, 4/3, −5/3) in Sector II, then the equivalent coordinate is (4/3, 1/3, −5/3) after normalizing it to Sector I. Similarly, the voltage space vectors in other sectors can also be normalized to Sector I according to this method. The equivalent coordinate components (Va1, Vb1, Vc1) of the voltage space vectors in Sector I are shown in Table 1. This coordinate normalization only needs to interchange the coordinate components and is easy to implement.

Principle of the Proposed SVM Scheme
The proposed simplified multi-level SVM scheme only needs three steps to be completed. The whole modulation process is as follows.

Step 1: Determining the Generalized Zero Vector
For the multi-level SVM scheme based on two-level SVPWM, the two-level hexagon where the reference voltage vector is located should be determined firstly, and this process is also the most important part. In this paper, the centers of the two-level hexagon are defined as the generalized zero vectors (GZV), as the red dots show in Figure 5.

Principle of the Proposed SVM Scheme
The proposed simplified multi-level SVM scheme only needs three steps to be completed. The whole modulation process is as follows.
Step 1: Determining the Generalized Zero Vector For the multi-level SVM scheme based on two-level SVPWM, the two-level hexagon where the reference voltage vector is located should be determined firstly, and this process is also the most important part. In this paper, the centers of the two-level hexagon are defined as the generalized zero vectors (GZV), as the red dots show in Figure 5. necessary to interchange the coordinate components of the a-axis and b-axis to normalize the voltage space vectors of Sector II to Sector I, such as if the coordinate is (1/3, 4/3, −5/3) in Sector II, then the equivalent coordinate is (4/3, 1/3, −5/3) after normalizing it to Sector I. Similarly, the voltage space vectors in other sectors can also be normalized to Sector I according to this method. The equivalent coordinate components (Va1, Vb1, Vc1) of the voltage space vectors in Sector I are shown in Table 1. This coordinate normalization only needs to interchange the coordinate components and is easy to implement.

Principle of the Proposed SVM Scheme
The proposed simplified multi-level SVM scheme only needs three steps to be completed. The whole modulation process is as follows.

Step 1: Determining the Generalized Zero Vector
For the multi-level SVM scheme based on two-level SVPWM, the two-level hexagon where the reference voltage vector is located should be determined firstly, and this process is also the most important part. In this paper, the centers of the two-level hexagon are defined as the generalized zero vectors (GZV), as the red dots show in Figure 5.  Sector I is analyzed as an example to show how to locate the GVZ, and there are six GVZs in total, as shown in Figure 6 (Point 1 ~6 ). In order to clearly locate the positions of GVZs, Sector I can be divided into six regions as shown by the dashed lines in Figure 6, denoted by different colors. The benefit of the idea of dividing into regions is that each region only has one GVZ, and the regions are not overlapping. Sector I is analyzed as an example to show how to locate the GVZ, and there are six GVZs in total, as shown in Figure 6 (Point ①~⑥). In order to clearly locate the positions of GVZs, Sector I can be divided into six regions as shown by the dashed lines in Figure 6, denoted by different colors. The benefit of the idea of dividing into regions is that each region only has one GVZ, and the regions are not overlapping.  Figure 3 that are on the lines. The expressions are as follows: Here, Vref in Region ④ is analyzed as an example, and the Point P is the GVZ in Region ④. In order to determine the location of the Point P, the intersection of the region borders should be firstly obtained. As shown in Figure 6, the Point C2 is the intersection of the borders of Region ④ (A2B2 and OC2). Therefore, the process of locating the GVZ (Point P) is shown in Figure 7, and the GVZ can be expressed as: As shown in Equation (2), the coordinates of the GVZ can be determined by subtracting the coordinates of the vector 2  PC from the coordinates of the intersection (Point C2) of the region borders. In Figure 3, it can be seen that the voltage space vector has constant values (2/3, −1/3, −1/3), which is the shortest voltage space vector in the five-level converter. Hence, the only unknown in Equation (2) is the coordinates of 2 OC  , which should be obtained as follows. The expressions of the dashed lines can be obtained based on the coordinate components of the voltage space vectors shown in Figure 3 that are on the lines. The expressions are as follows: Here, V ref in Region 4 is analyzed as an example, and the Point P is the GVZ in Region 4 . In order to determine the location of the Point P, the intersection of the region borders should be firstly obtained. As shown in Figure 6, the Point C 2 is the intersection of the borders of Region 4 (A 2 B 2 and OC 2 ). Therefore, the process of locating the GVZ (Point P) is shown in Figure 7, and the GVZ can be expressed as: Sector I is analyzed as an example to show how to locate the GVZ, and there are six GVZs in total, as shown in Figure 6 (Point ①~⑥). In order to clearly locate the positions of GVZs, Sector I can be divided into six regions as shown by the dashed lines in Figure 6, denoted by different colors. The benefit of the idea of dividing into regions is that each region only has one GVZ, and the regions are not overlapping.  Figure 3 that are on the lines. The expressions are as follows: Here, Vref in Region ④ is analyzed as an example, and the Point P is the GVZ in Region ④. In order to determine the location of the Point P, the intersection of the region borders should be firstly obtained. As shown in Figure 6, the Point C2 is the intersection of the borders of Region ④ (A2B2 and OC2). Therefore, the process of locating the GVZ (Point P) is shown in Figure 7, and the GVZ can be expressed as: As shown in Equation (2), the coordinates of the GVZ can be determined by subtracting the coordinates of the vector 2  PC from the coordinates of the intersection (Point C2) of the region borders. In Figure 3, it can be seen that the voltage space vector  As shown in Equation (2), the coordinates of the GVZ can be determined by subtracting the coordinates of the vector → PC 2 from the coordinates of the intersection (Point C 2 ) of the region borders.
In Figure 3, it can be seen that the voltage space vector which is the shortest voltage space vector in the five-level converter. Hence, the only unknown in Equation (2) is the coordinates of → OC 2 , which should be obtained as follows. Based on the characteristics of Equation (1), the common terms of all dashed lines are (3V a1 + 3V c1 , V a1 − V c1 ), and all the constants are integers. Therefore, two variables x, y can be defined as in Equation (3) by using the coordinate components of V ref . where (V a1_ref , V b1_ref , V c1_ref ) are the equivalent coordinate components of V ref in Sector I, and the ceil (·) function means rounding up to the next larger integer. Based on the coordinate components of the voltage space vectors in Figure 3, the values of x, y corresponding to each region (where each GVZ 1 -6 locates) can be summarized in Table 2. Table 2. The values of x and y corresponding to each region.
As shown in Table 2, x = 2 and y = 0 when V ref is in Region 4 . Therefore, the coordinates (V a_C2 , V b_C2 , V c_C2 ) of the intersection (Point C 2 ) of the region borders (A 2 B 2 and OC 2 ) can be expressed as In Equation (4) are the expressions of A 2 B 2 and OC 2 by using the variables x and y, which are the same as in Equation (1). Then, based on (4) and V a_C2 + V b_C2 + V c_C2 = 0 (i.e., there is no zero-sequence component in a three-phase three-wire system), the coordinate components of Point C 2 can be expressed by using x and y, as shown in Equation (5).
Finally, based on the Equation (2), the coordinate components (V a0 , V b0 , V c0 ) of the GVZ (Point P) can be expressed as It can be seen that the coordinate components of all GVZs can be easily obtained by calculating Equation (6). According to the relationship of the multi-level space vector distribution, this SVM scheme can be extended to any n-level converter. Additionally, the variables x, y can be redefined as in Equation (7) to account for any n-level converter.
where the function rem (·) means the remainder of n/2, and n is the number of voltage levels. If n is odd, z = 1, and if n is even, z = 0. By adding the variable z, this simplified multi-level SVM scheme can be extended to any n-level converter without much increase in calculation. According to the above analysis, Step 1, which is the most important part of the multi-level SVM scheme for determining the GVZs, can be easily achieved by calculating Equation (6). The process proposed here is much simpler than other SVM schemes based on two-level SVM in references [33,35] and does not require the layer calculations. Step 2: Space Vector State (Redundant Vector) Selection For the SVM scheme, V ref is synthesized by the voltage space vectors around it. Therefore, it is necessary to select the most appropriate voltage space vectors.
For the multi-level converters, there are a large number of voltage space vectors, including redundant vectors. For a five-level converter, there are 125 voltage space vectors in total. The redundant voltage space vectors have different effects on the performance of the multi-level converters, such as reducing common-mode voltage [15,16], harmonic suppression [17,18], balancing capacitor voltage [19], reducing switching losses [20], conferring fault tolerance [21], etc. Therefore, the redundant voltage space vectors can be selected to achieve a certain objective. In this paper, common-mode voltage reduction is selected as the primary objective and is used as an example. The common-mode voltage can cause issues in motor drive systems, such as motor bearing damage, insulation breakdown and electromagnetic interface (EMI).
The common-mode voltage is different when different voltage space vectors are used. For a five-level converter, when all voltage space vectors are used, the common-mode voltages are ± 2V dc , ±5V dc /3, ±4V dc /3, ±V dc , ±2V dc /3, ±V dc /3, and 0, and the maximum common-mode voltage is ±2V dc . Therefore, the common-mode voltage can be reduced by selecting the appropriate voltage space vectors. For example, the zero space vector at the origin in the space vector diagram in Figure 2 has five available vector states: (2 2 2), (1 1 1), (0 0 0), (−1 −1 −1) and (−2 −2 −2), and the corresponding common-mode voltages are 2V dc , V dc , 0, −V dc and −2V dc . Here, −2, −1, 0, 1 and 2 represent the five voltage levels in a five-level converter. The common-mode voltage is minimized when the middle voltage space vector state (0 0 0) is selected. Therefore, some voltage space vectors generating a larger common-mode voltage should not be used to reduce the common-mode voltage [15].
As shown in Figure 2, different points have different numbers of redundant voltage space vectors. When the point has an odd number of voltage space vectors, only the middle voltage space vector should be used. When the point has an even number of voltage space vectors, the middle two voltage space vectors should be used, as shown in Figure 8. At this point, the common-mode voltages are ±V dc , ±2V dc /3, ±V dc /3 and 0, and the maximum common-mode voltage is ±V dc , which is half of all voltage space vectors used.  Based on Figure 5 or Figure 8, it can be seen that each GVZ has two voltage space vectors. Therefore, the initial space vector state should be determined at the beginning of the modulation cycle. The voltage space vectors within brackets are defined as the initial space vector states in Figure 8. For instance, when Vref is in Region ④ as shown in Figure 6, the initial space vector state is (1 0 -2), and the switching sequence is The two voltage space vectors of each GVZ can be defined as Sup and Sdown. Sup is the starting vector state for the current cycle, Sdown is the ending vector state for the current cycle and also the starting space vector state of the next modulation cycle, and Sdown is defined as the initial space vector state. By analyzing the relationship between the values of x, y in Table 2 and the two voltage Based on Figure 5 or Figure 8, it can be seen that each GVZ has two voltage space vectors. Therefore, the initial space vector state should be determined at the beginning of the modulation cycle. The voltage space vectors within brackets are defined as the initial space vector states in Figure 8. For  Figure 6, the initial space vector state is (1 0 -2), and the switching sequence is [ The two voltage space vectors of each GVZ can be defined as S up and S down . S up is the starting vector state for the current cycle, S down is the ending vector state for the current cycle and also the starting space vector state of the next modulation cycle, and S down is defined as the initial space vector state. By analyzing the relationship between the values of x, y in Table 2 and the two voltage space vectors of the GVZs in Sector I in Figure 8, S up and S down can be directly expressed by using the variables x and y as Based on the above analysis, the initial space vector state can be directly expressed by using the variables x and y in Equation (8) when common-mode voltage reduction is the control objective. The main contribution of Step 2 is to reveal the relationship between the common-mode voltage reduction and the defined variables x and y, and it provides a theoretical approach to linking the common-mode reduction to the variables x and y.
When other control objectives need to be considered, such as harmonic (THD, WTHD) suppression, reducing switching losses, etc., in theory, the relationship between these control objectives and the variables x and y can also be determined based on the above-presented approach, and these control objectives have been implemented for many other SVPWM methods through selecting the redundant voltage space vectors [17][18][19][20][21]. The identification of these relationships needs to be further researched.
where (V a , V b , V c ) are the coordinate components of the two-level equivalent reference voltage vector V ref , and (V a0 , V b0 , V c0 ) are the coordinate components of the GVZ.
Then, the ON-times of each phase can be calculated. Compared to conventional two-level SVM, two-level simplified SVM can directly calculate the ON-times through the three-phase reference voltage without judging the sector, calculating the ON-times of the basic space vectors and determining the switching sequence. The calculation can be greatly simplified [37]. Therefore, based on two-level simplified SVM, the ON-times of each phase can be directly expressed as where V avg = [max(V a ,V b ,V c ) + min(V a ,V b ,V c )]/4, T s is the switching cycle, and j = a, b, c. Therefore, Step 3 can be directly completed only through calculating the Equations (9) and (10). After calculating the three steps (Equations (6), (8)-(10)), the proposed SVM scheme is complete when V ref is located in Sector I. Based on the coordinate normalization in Table 1, the coordinate components of the GVZs and the initial space vector S down (S a0 , S b0 , S c0 ) in other sectors can be directly obtained through anti-normalization by interchanging the coordinate components. For example, the coordinate components of the GVZ and the initial space vector in Sector I are (V a0 , V b0 , V c0 ) and (x−1, −y, −x), respectively. If they are anti-normalized from Sector I to Sector II, it is only necessary to interchange the coordinate components of a-axis and b-axis, i.e., the coordinate components of the GVZ and the initial space vector are (V b0 , V a0 , V c0 ) and (−y, x−1, −x) in Sector II, respectively. The anti-normalization for the other sectors is the same, as shown in Table 3. Table 3. The anti-normalization of coordinate components of GVZs and initial voltage space vector states.

Sector
V 0 (S a0 , S b0 , S c0 ) A flowchart of the proposed SVM scheme is shown in Figure 9. It shows the whole process of the proposed SVM schemes. By summarizing the above analysis, the normalization and anti-normalization only need to interchange the coordinate components without adding calculations. Therefore, the proposed SVM scheme only needs to calculate Steps 1, 2, and 3, and each step is only a simple mathematical calculation, which greatly simplifies the process of decomposing V ref . The whole modulation process does not require the layer calculations. Therefore, this SVM scheme can be extended to the higher level converters without adding much calculation.

Experimental Results
The proposed SVM scheme is validated on a three-phase five-level CHB inverter prototype. The experimental setup is shown in Figure 10. The power switches are insulated gate bipolar transistors (IGBT) (BSM50GB120DLC, 1200 V/50 A). The phase currents and voltages are measured by LEM voltage and current sensors (LA55-P and LV 25-P). The master controller board contains one DSP TMS320F28335 and one Xilinx Spartan3E FPGA XC3S500E. The whole SVM process is executed on the DSP, and the FPGA is only responsible for extending pulse signals. The experimental parameters are shown in Table 4.

Experimental Results
The proposed SVM scheme is validated on a three-phase five-level CHB inverter prototype. The experimental setup is shown in Figure 10. The power switches are insulated gate bipolar transistors (IGBT) (BSM50GB120DLC, 1200 V/50 A). The phase currents and voltages are measured by LEM voltage and current sensors (LA55-P and LV 25-P). The master controller board contains one DSP TMS320F28335 and one Xilinx Spartan3E FPGA XC3S500E. The whole SVM process is executed on the DSP, and the FPGA is only responsible for extending pulse signals. The experimental parameters are shown in Table 4.  Figure 13 shows the common-mode voltage waveform. Figure 11 shows the experimental results when m = 0.6. The line voltage vab has seven levels as expected, the total harmonic distortion (THD) is 23.46%, and the weight THD (WTHD) is 0.39%. Meanwhile, the harmonics of vab are mainly distributed around the integer multiples of the switching frequency of 2 kHz (nfs, n = 1, 2, 3, …). The three phase currents are highly sinusoidal, and the THD is 1.13%. Figure 12 shows the experimental results when m = 0.9. vab has nine levels as expected, the THD is 16.91%, and the WTHD is 0.27%. The three phase currents are also highly sinusoidal, and the THD is 0.8%. The line voltage in Figures 11 and 12 contains a slight DC offset due to the DC bias of the voltage probe, which was not calibrated to zero. The main waveforms are correct as expected that the line voltage is seven levels when the modulation index is 0.6 and the line voltage is nine levels when the modulation index is 0.9. Meanwhile, the THD and WTHD of the proposed SVM scheme are very low, and the main components of the harmonics are switching frequency harmonics (around nfs). Therefore, the waveforms and THD results show that the proposed SVM scheme can ensure the converter can work properly with low harmonics. It should be noted that from the harmonics (THD) point of view, the proposed method has similar performance to other SVPWM methods. The focus of the proposed multi-level SVM scheme is not to reduce the THD but to reduce the computation time.
As shown in Figure 13, the common-mode voltage has seven values of ±Vdc, ±2Vdc/3, ±Vdc/3 and 0 in total, and the maximum common-mode voltage is Vdc = 50 V. It is consistent with the analysis in Step 2. Therefore, the selected voltage space vectors can effectively reduce the common-mode voltage, where the common-mode voltages ± 2Vdc, ±5Vdc/3 and ±4Vdc/3 have been removed.
The experimental results prove that the proposed SVM scheme can work well with low harmonics under different modulation indexes.  Here, the modulation index m is defined as Figures 11 and 12 show the performance of the proposed SVM scheme under different modulation indexes. Figure 13 shows the common-mode voltage waveform. Figure 11 shows the experimental results when m = 0.6. The line voltage v ab has seven levels as expected, the total harmonic distortion (THD) is 23.46%, and the weight THD (WTHD) is 0.39%. Meanwhile, the harmonics of v ab are mainly distributed around the integer multiples of the switching frequency of 2 kHz (nf s , n = 1, 2, 3, . . . ). The three phase currents are highly sinusoidal, and the THD is 1.13%. Figure 12 shows the experimental results when m = 0.9. v ab has nine levels as expected, the THD is 16.91%, and the WTHD is 0.27%. The three phase currents are also highly sinusoidal, and the THD is 0.8%. The line voltage in Figures 11 and 12 contains a slight DC offset due to the DC bias of the voltage probe, which was not calibrated to zero. The main waveforms are correct as expected that the line voltage is seven levels when the modulation index is 0.6 and the line voltage is nine levels when the modulation index is 0.9. Meanwhile, the THD and WTHD of the proposed SVM scheme are very low, and the main components of the harmonics are switching frequency harmonics (around nf s ). Therefore, the waveforms and THD results show that the proposed SVM scheme can ensure the converter can work properly with low harmonics. It should be noted that from the harmonics (THD) point of view, the proposed method has similar performance to other SVPWM methods. The focus of the proposed multi-level SVM scheme is not to reduce the THD but to reduce the computation time.   In order to verify the generality of the SVM scheme, another experimental validation is carried out on an existing four-level inverter [38] in the laboratory. The topology is shown in Figure 14. The four-level converter needs to control the flying capacitor (FC) voltages, and the control method has    In order to verify the generality of the SVM scheme, another experimental validation is carried out on an existing four-level inverter [38] in the laboratory. The topology is shown in Figure 14. The four-level converter needs to control the flying capacitor (FC) voltages, and the control method has   In order to verify the generality of the SVM scheme, another experimental validation is carried out on an existing four-level inverter [38] in the laboratory. The topology is shown in Figure 14. The four-level converter needs to control the flying capacitor (FC) voltages, and the control method has As shown in Figure 13, the common-mode voltage has seven values of ±V dc , ±2V dc /3, ±V dc /3 and 0 in total, and the maximum common-mode voltage is V dc = 50 V. It is consistent with the analysis in Step 2. Therefore, the selected voltage space vectors can effectively reduce the common-mode voltage, where the common-mode voltages ± 2V dc , ±5V dc /3 and ±4V dc /3 have been removed.
The experimental results prove that the proposed SVM scheme can work well with low harmonics under different modulation indexes.
In order to verify the generality of the SVM scheme, another experimental validation is carried out on an existing four-level inverter [38] in the laboratory. The topology is shown in Figure 14. The four-level converter needs to control the flying capacitor (FC) voltages, and the control method has been given in [38]. For the four-level inverter, each output voltage level may correspond to multiple switching states. Therefore, before outputting the pulse signals, the converter needs to select the appropriate switching states according to the FC voltages. In other words, the FC voltage is controlled through choosing the appropriate (redundant) switching states within each phase leg, not through choosing the redundant space vectors in the three-phase SVPWM. Therefore, the modulation strategy only needs to be modified when the pulse signals are generated, to select the appropriate switching states for FC voltage control, as shown in Figure 15 (FC voltage control), and the three calculation steps of the proposed SVM scheme in the paper do not need to be changed. In order to accurately and objectively evaluate the SVM scheme for different multi-level converters, the computational time of the FC voltage control method is not counted when calculating the time for the four-level converter.
14 of 19 been given in [38]. For the four-level inverter, each output voltage level may correspond to multiple switching states. Therefore, before outputting the pulse signals, the converter needs to select the appropriate switching states according to the FC voltages. In other words, the FC voltage is controlled through choosing the appropriate (redundant) switching states within each phase leg, not through choosing the redundant space vectors in the three-phase SVPWM. Therefore, the modulation strategy only needs to be modified when the pulse signals are generated, to select the appropriate switching states for FC voltage control, as shown in Figure 15 (FC voltage control), and the three calculation steps of the proposed SVM scheme in the paper do not need to be changed. In order to accurately and objectively evaluate the SVM scheme for different multi-level converters, the computational time of the FC voltage control method is not counted when calculating the time for the four-level converter.  In order to verify the feasibility of the proposed scheme for the four-level converter, a down-scaled prototype is built in the laboratory. The controller of the prototype is based on a TI 14 of 19 been given in [38]. For the four-level inverter, each output voltage level may correspond to multiple switching states. Therefore, before outputting the pulse signals, the converter needs to select the appropriate switching states according to the FC voltages. In other words, the FC voltage is controlled through choosing the appropriate (redundant) switching states within each phase leg, not through choosing the redundant space vectors in the three-phase SVPWM. Therefore, the modulation strategy only needs to be modified when the pulse signals are generated, to select the appropriate switching states for FC voltage control, as shown in Figure 15 (FC voltage control), and the three calculation steps of the proposed SVM scheme in the paper do not need to be changed. In order to accurately and objectively evaluate the SVM scheme for different multi-level converters, the computational time of the FC voltage control method is not counted when calculating the time for the four-level converter.  In order to verify the feasibility of the proposed scheme for the four-level converter, a down-scaled prototype is built in the laboratory. The controller of the prototype is based on a TI In order to verify the feasibility of the proposed scheme for the four-level converter, a down-scaled prototype is built in the laboratory. The controller of the prototype is based on a TI TMS320F28335 DSP and a Xilinx XC3S400 FPGA. The whole SVM scheme are also executed on the DSP, and the FPGA is responsible for extending pulse signals, as same as in the five-level CHB experimental validation. The phase currents and the FC voltages are measured by sensors from LEM (LA 55-P and LV 25-P). The power switches are IGBTs (IKW40N120T2 from Infineon, 1200 V/40 A). The experimental parameters are shown in Table 5. The experimental results are shown in Figure 16. Figure 16 shows the line voltage, the three phase currents and the FC voltages when the modulation index is dynamically changed from 0.9 to 0.6. The comparison of the experimental results and theoretical results is shown in Table 6.

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TMS320F28335 DSP and a Xilinx XC3S400 FPGA. The whole SVM scheme are also executed on the DSP, and the FPGA is responsible for extending pulse signals, as same as in the five-level CHB experimental validation. The phase currents and the FC voltages are measured by sensors from LEM (LA 55-P and LV 25-P). The power switches are IGBTs (IKW40N120T2 from Infineon, 1200V/40A). The experimental parameters are shown in Table 5. The experimental results are shown in Figure 16. Figure 16 shows the line voltage, the three phase currents and the FC voltages when the modulation index is dynamically changed from 0.9 to 0.6. The comparison of the experimental results and theoretical results is shown in Table 6.  As shown in Figure 16, when the modulation index is 0.9, the waveform of the line voltage is seven voltage levels, as expected for theoretical analysis, and when the modulation index is 0.6, the waveform of the line voltage is five voltage levels, as expected for theoretical analysis. The three phase currents are highly sinusoidal, and all FC voltages can always be regulated near the desired value of Vdc/3 = 80 V. Meanwhile, as shown in Table 6, the experimental results for the four-level inverter are almost the same as the theoretical results. This proves that the proposed SVM scheme can also be used for the four-level converter and the converter can work normally.
The proposed SVM scheme is a simplified multi-level SVM scheme based on the two-level SVPWM. The main contribution is that the scheme greatly simplifies the process of decomposing Vref, and the whole modulation process does not require the layer calculations. In order to evaluate the efficiency of the proposed SVM scheme, a comparison with an existing same type of SVM is necessary. The well-known and representative multi-level SVMs based on two-level SVPWM are  As shown in Figure 16, when the modulation index is 0.9, the waveform of the line voltage is seven voltage levels, as expected for theoretical analysis, and when the modulation index is 0.6, the waveform of the line voltage is five voltage levels, as expected for theoretical analysis. The three phase currents are highly sinusoidal, and all FC voltages can always be regulated near the desired value of V dc /3 = 80 V. Meanwhile, as shown in Table 6, the experimental results for the four-level inverter are almost the same as the theoretical results. This proves that the proposed SVM scheme can also be used for the four-level converter and the converter can work normally.
The proposed SVM scheme is a simplified multi-level SVM scheme based on the two-level SVPWM. The main contribution is that the scheme greatly simplifies the process of decomposing V ref , and the whole modulation process does not require the layer calculations. In order to evaluate the efficiency of the proposed SVM scheme, a comparison with an existing same type of SVM is necessary. The well-known and representative multi-level SVMs based on two-level SVPWM are described in [33,35]. Therefore, the computational times of three SVM schemes (the proposed SVM and the SVM schemes based on two-level SVM in [33,35]) were measured and compared in the DSP, as shown in Figure 17. 16 of 19 described in [33,35]. Therefore, the computational times of three SVM schemes (the proposed SVM and the SVM schemes based on two-level SVM in [33,35]) were measured and compared in the DSP, as shown in Figure 17. It can be seen that the computational time of the proposed SVM scheme is less than that of the two SVM schemes in [33,35]. Meanwhile, the computational times are slightly different for the four-level and five-level converters with the proposed SVM method. The reason is that the variables x and y are calculated differently in four-level and five-level SVM. Based on the Equation (7), when the voltage level is even, x and y are expressed as a1_ref c1_ref a1_ref c1_ref When the voltage level is odd, the variables x and y are expressed as Equation (3), which is slightly different to in Equation (12). Therefore, the computational time of the four-level SVM is slightly more than the computational time of the five-level SVM.
For a three-level converter, the computational time of the algorithm in [33] is 5.713 μs and the computational time of the algorithm in [35] is 5.207 μs. It is shown that the two methods are relatively simple for a three-level converter, but the computational time of the two methods in [33] and [35] increases as the number of voltage levels increases due to the layer calculations, as shown in Figure 17. However, no matter how many the voltage levels there are, the process of the proposed algorithm is the same as shown in the flowchart in Figure 9. The whole modulation only needs to calculate Equations (6), (8), (9) and (10). The only difference is that expressions of the variables x and y are different for the odd-and even-level converters. Therefore, for any odd-level converter, the computational time of the proposed SVM scheme is the same according to the Equation (3). For any even-level converter, the computational time is also the same according to the Equation (12). Both of them are almost the same, as shown in Figure 17 (the blue one and the green one). The comparison proves that the proposed SVM scheme greatly simplifies the modulation process of the multi-level SVM scheme based on two-level SVPWM and can be expanded to any n-level converter, and the computational times are almost the same.

Conclusions
In order to solve the issue that the multi-level SVM scheme is difficult to implement, this paper proposes a generic simplified multi-level SVM scheme based on the two-level SVM scheme. Compared to the existing multi-level SVM schemes based on the two-level SVM scheme, the It can be seen that the computational time of the proposed SVM scheme is less than that of the two SVM schemes in [33,35]. Meanwhile, the computational times are slightly different for the four-level and five-level converters with the proposed SVM method. The reason is that the variables x and y are calculated differently in four-level and five-level SVM. Based on the Equation (7), when the voltage level is even, x and y are expressed as When the voltage level is odd, the variables x and y are expressed as Equation (3), which is slightly different to in Equation (12). Therefore, the computational time of the four-level SVM is slightly more than the computational time of the five-level SVM.
For a three-level converter, the computational time of the algorithm in [33] is 5.713 µs and the computational time of the algorithm in [35] is 5.207 µs. It is shown that the two methods are relatively simple for a three-level converter, but the computational time of the two methods in [33,35] increases as the number of voltage levels increases due to the layer calculations, as shown in Figure 17. However, no matter how many the voltage levels there are, the process of the proposed algorithm is the same as shown in the flowchart in Figure 9. The whole modulation only needs to calculate Equations (6), (8)- (10). The only difference is that expressions of the variables x and y are different for the odd-and even-level converters. Therefore, for any odd-level converter, the computational time of the proposed SVM scheme is the same according to the Equation (3). For any even-level converter, the computational time is also the same according to the Equation (12). Both of them are almost the same, as shown in Figure 17 (the blue one and the green one). The comparison proves that the proposed SVM scheme greatly simplifies the modulation process of the multi-level SVM scheme based on two-level SVPWM and can be expanded to any n-level converter, and the computational times are almost the same.

Conclusions
In order to solve the issue that the multi-level SVM scheme is difficult to implement, this paper proposes a generic simplified multi-level SVM scheme based on the two-level SVM scheme. Compared to the existing multi-level SVM schemes based on the two-level SVM scheme, the proposed SVM scheme does not require a lookup table, coordinate transformation or layer calculations. The whole modulation process can be completed by only three steps, and each step only needs to calculate simple mathematical equations, which greatly simplifies the process of decomposing V ref . The whole modulation scheme is easy to implement. For any odd-level converter, the computational time of the proposed SVM scheme is the same, as is so for any even-level converter, and both of these times are almost the same. Therefore, the proposed SVM scheme can be used for any n-level converter without adding much calculation, regardless of the number of levels. Common-mode voltage reduction is selected as the primary objective and is used as an example, and the common-mode voltage can be reduced by half. Meanwhile, the proposed SVM scheme reveals the relationship between the common-mode voltage reduction and the switching sequence, and provides a theoretical approach to linking the common-mode reduction to the initial space vector states. When other control objectives are considered, the relationships between these control objectives and the switching sequence can also be determined based on the presented theoretical approach. In order to verify the feasibility and generality of the proposed SVM scheme, the experimental results for the four-level and five-level converters are provided. The experimental results prove that the proposed SVM scheme can ensure that the two types of converter work normally and that the computation effort does not increase with number of levels, so it can be readily applied to any n-level converter. Meanwhile, the proposed SVM scheme is more efficient than other multi-level SVM schemes based on two-level SVPWM, which greatly simplifies the modulation process.
Author Contributions: C.W. wrote the paper, analyzed the principle and designed the experiments; X.Y. shared his experience and knowledge in advanced multilevel converter; Y.Z. analyzed the simulation data; X.W. helped to perform the analysis with constructive discussions. All authors have read and agreed to the published version of the manuscript.
Funding: This research was funded by joint Ph.D. program of "double first rate" construction disciplines of CUMT.

Conflicts of Interest:
The authors declare no conflict of interest.