Control Design and Experimental Validation of a HB-NPC as a Shunt Active Power Filter

: This work presents the design of a control law based on the average model of a shunt active power ﬁlter considering an H-bridge neutral point clamped topology and its experimental validation. Therefore, the proposed controller is formed by three control loops, namely current (inner), regulation (outer), and balance control loops. The current loop aims to compensate both the displacement power factor and the harmonic distortion produced by nonlinear loads connected to the point of common coupling. To deal with harmonic current distortion, the current loop involves an adaptive mechanism based on a bank of resonant ﬁlters tuned at odd harmonics of the fundamental grid frequency. The regulation and balance loops are aimed to maintain the voltage of the capacitors forming the DC-link at a desired constant level. For this, proportional-integral controllers are designed. The design of all three loops considers the average model of the system. The performance of the proposed multi-loop control law is evaluated through numerical results and real-time experimental implementation, both considering a 2 kW academic benchmark with a constant switching frequency of 7 kHz. In order to provide harmonic distortion, a nonlinear load based on an uncontrolled diode bridge rectiﬁer is considered. Additionally, step-load changes from 0.5 kW to 1 kW are considered for the nonlinear load. As a result, a suitable current tracking, voltage regulation, and balance are observed despite parametric uncertainties, load variations, and harmonic distortion. As a consequence, in steady state, simulation results indicate that the compensated grid current THD is 1.75%; meanwhile, the nonlinear load current THD is 52.5%. Experimental results indicate that the compensated grid current THD is 2.32%; meanwhile, the nonlinear load current THD is 53.8%.


Introduction
The ever increasing connection of non-linear loads (NLL) to the grid has produced power quality problems in sensitive electrical distribution systems. In particular, these NLL enlarge the reactive power and harmonic components circulating in electrical grids, which, in turn, lead to several issues, such as voltage waveform distortions, overheating of distribution transformers, electromagnetic interference, and inefficient distribution of energy, among others. Currently, modern electrical systems are adopting the concept of smart grids, which allows dealing in a more appropriate way with the high penetration of renewable energy (solar, wind, biomass energy, etc.) and multiple electronic loads. However, the need for energy quality compensators is still imperative [1]. Shunt active power filters (SAPF) represent a viable alternative to attenuate the adverse effects caused by NLL [2,3]. SAPF can compensate both the harmonics generated by NLL and the reactive power produced by non-resistive linear loads to ensure a power factor (PF) close to unity according to international power quality standards, such as IEEE-519 [4]. Therefore, the use of SAPF entails a significant increase in the overall efficiency of the system and leads to reduced energy consumption costs.
The typical structure of an SAPF consists of a voltage source inverter (VSI), which converts the type of electrical energy and serves as a coupling between the grid and the DC-link. The DC-link in the SAPF is made of capacitors, large enough to store energy to compensate transient current peaks throughout the operation of the system. An output filter is generally used as the coupling impedance between the VSI and the grid at the point of common coupling (PCC) to reduce the current switching ripple. Many VSI topologies used in SAPF applications have been studied. In particular, multilevel converters have demonstrated better characteristics when compared to traditional two-level conventional topologies [2]. Mainly, multilevel inverters are able to produce higher quality voltage and current waveforms. Furthermore, in multilevel inverters, the voltage across the switching devices is lower, which implies low electric stress on power semiconductors and a reduction of switching losses, keeping high efficiency. For instance, the five level HB-NPC topology has shown efficiency greater than 96% for photovoltaic applications [5].
In particular, the neutral point clamped (NPC) [6][7][8], full H-bridge [9], and flying capacitor [10], which are three-level power converter topologies, have been used as the VSI in SAPF applications. Five-level inverters, namely five-level (one-leg) NPC [11,12], H-bridge NPC (HB-NPC) [13,14], and cascade full-bridge topologies [15], have also been used as SAPF. Five-level inverters are able to generate an AC output voltage waveform with smaller switching ripple as compared to three-level inverters. They also provide lower common-mode voltage, lower harmonic distortion, and lower electromagnetic interference [6,16,17]. For instance, in [18], a cascade H-bridge (CHB) based multilevel converter was used as a static VAR compensator (STATCOM) in a wind farm. Additionally, a CHB-based SAPF using single-phase toroidal core transformers in cascaded configuration was presented in [19], which allowed the system to operate with a single DC-link capacitor. Furthermore, a detailed comparison of multilevel topologies' characteristics and their applications were presented in [20,21].
In the last few years, research related to the control design for different topologies used in SAPF applications has been carried out extensively as well. For instance, the work in [8] presented a control design for a three-level NPC as an SAPF. Here, the control method aimed to solve the current tracking problem and provided damping to the three order output filter. In [11,12], fuzzy logic control solutions were presented to solve the current tracking problem in a five-level NPC converter. In [22], a three-phase VSI connected to the PCC was used as an SAPF. In this case, the NLL was represented by an electric vehicle supplied by a photovoltaic system, which was controlled by a neuro-fuzzy inference system in combination with an MPPT scheme. In [23], a combination of a neural network control strategy plus a bandless hysteresis controller was proposed for a switched capacitor used as an SAPF. However, due to the nonlinear nature of the system, this control technique produced variable switching frequency, leading to undesirable resonance effects in grid-tied power electronics converters [24]. In [25], a proportional-integral (PI) iterative controller was proposed for a shunt hybrid power filter. In [26], a modified multifrequency passivity-based control (PBC) strategy was proposed for an SAPF based on a T-Type inverter topology. The modification consisted of the introduction of a PI regulator into the coupling loop of the conventional PBC. In [3], a model-based sliding-mode control (SMC) was proposed for a three-phase full-bridge shunt active power filter. The solution consisted of a Kalman filter structure to estimate the variables used to generate the switching surfaces. Nevertheless, a major drawback of SMC is the oscillations, also referred to as chattering, which are produced due to the switching time delay and the unknown dynamics of the system. As a consequence, SMC presents low control precision and unstable switching frequency in power electronics applications interacting with the electrical grid [27].
However, multilevel inverters exhibit also certain drawbacks. For instance, the control design becomes more challenging than in conventional three-level topologies. In fact, most multilevel power converters require an extra control strategy to guarantee that each capacitor in the topology maintains a specific voltage level. This is referred to as the voltage balancing loop, which gets more involved for higher levels and may represent a considerable additional computational cost. For instance, the work in [28] described in detail the modeling and control design for a three-level half-bridge NPC converter used as an SAPF, whereas, in [29], a control scheme for the cascaded H-bridge topology was proposed. In [30], a predictive current control scheme for an SAPF was presented. In [13,14], also predictive current control schemes were proposed for single-phase NPC power converters as an SAPF. In [14], a single-objective predictive control method was proposed for a single-phase SAPF based on a three-level NPC converter. Here, the control scheme aimed to compensate the reactive power and harmonic distortion without using weighting factors as the cost function. In [10], a novel finite control state set model predictive control was proposed for a flying capacitor topology operating as an SAPF. However, an issue for the implementation of predictive control techniques is the tuning for a reliable weighting factor, which is a complex optimization challenge in active power filtering applications [14]. Moreover, the absence of a modulating signal produces a varying switching frequency due to the limited number of valid switching states generating large current and voltage ripples [31].
This paper presents the modeling process and control design of an SAPF based on a five-level HB-NPC topology. This topology is composed of the bridge connection of two NPC branches, which provides five output voltage levels. The controller includes a control law capable of compensating reactive and harmonic currents. As the DC-link is split and composed of two capacitors, the controller also includes two additional voltage loops, namely voltage balance and regulation control loops to control the DC-link.
The contributions of this work towards shunt active power filtering are as follows: • The design of a multi-loop controller for SAPF based on a five-level HB-NPC topology, which considers a time scale separation between current and voltage dynamics. The last yields three independent control loops, i.e., current tracking loop, voltage regulation loop, and voltage balance loop for PF correction and harmonic mitigation.

•
The proposed control scheme does not depend on system parameters' knowledge; therefore, a robust behavior against grid uncertain parameters, output filter uncertain parameters, current harmonic distortion, and load variations is exhibited.

•
According to the best of the authors knowledge, there is no similar work in the literature regarding the experimental validation of the proposed control scheme applied to a five-level HB-NPC topology for an SAPF of 2 kW academic prototype with a constant switching frequency of 7 kHz.
The rest of the paper is organized as follows: In Section 2, the model of the system is obtained, and the control objectives together with the main assumptions are presented. Section 3 details the design of the three control loops, and numerical results are presented as well. Section 4.2 shows experimental results to evaluate the performance of the closed-loop system. Finally, Section 5 provides some concluding remarks about the present work. Figure 1 depicts the five-level HB-NPC (5L-HB-NPC) topology used as an SAPF, which is connected in parallel to the NLL. The grid voltage is represented by v G , which supplies both the NLL and the SAPF, and has a fundamental frequency given by ω. The grid impedance is represented by the series connection of L G and R G . Hence, the voltage at the PCC is given by:

System Description
The SAPF is coupled to the PCC through an L F filter (R F represents the filter parasitic resistance). Notice that, to generate a multilevel output voltage, it is necessary to store enough energy in both DC-link capacitors C 1 and C 2 . In other words, it is necessary to maintain a DC-link voltage level high enough to allow the reconstruction of a required VSI output voltage, also referred to as the injected voltage. The VSI output voltage must dominate the grid voltage amplitude to allow the appropriate injection of current towards the grid. Moreover, it is mandatory to guarantee that all capacitors in the DC-bus have a balanced voltage to avoid asymmetries on the reconstructed injected voltage. This fact will be detailed later in the control objectives' definition.
As shown in Figure 1, the 5L-HB-NPC consists of two branches of conventional three-level NPC converters connected in an H-bridge configuration. Every switch of the topology is represented by S n (n ∈ {1, 2, 3, 4, 5, 6, 7, 8}). The topology involves four diodes to gain access from the mid-point of the DC-link to the VSI output voltage to produce the null states. The permissible outputs for the converter are summarized in Table 1, where the value o one represents the ON state, whilst the value of zero represents the OFF state at the corresponding switch. The inverter output voltage is represented by e AF , which takes values from a discrete set of possible voltage levels, i.e.,

5L-HB-NPC
To simplify the modeling process, an equivalent circuit that represents a simplification of the power converter operation is obtained following the guidelines presented in [32] and is shown in Figure 2, where the switches are replaced by two equivalent single pole triple throw switches. Notice that δ 1 and δ 2 represent switching functions taking values in the discrete set {−1, 0, 1}. Table 1 relates the switch positions combinations to the equivalent switching functions δ 1 and δ 2 . Out of this equivalence, the following expression of the control signal e AF in terms of the switching functions δ 1 and δ 2 and the DC capacitor voltage levels can be obtained: As stated in the power electronics literature [33], the model SAPF based on the 5L-HB-NPC can be obtained by direct application of Kirchhoff's current and voltage laws, on the equivalent circuit of Figure 2, which yields: ). The nonlinear current generated by the NLL is represented by i NLL . Notice that the state x R provides a measure of the capacitor voltage regulation, while the state x B represents the capacitor voltage difference at the DC-link, i.e., the voltage balance. The output inductive filter is represented by L F . The DC-link is formed by two bulky capacitors C 1 and C 2 with the same capacitance value, i.e., C 1 = C 2 = C. Notice that the resistive term R is considered a system parameter and represents the typical resistance used for safety reasons to discharge the DC-link capacitors in maintenance works [34]. Notice also that this resistor is commonly of a high value above tens of kilo ohms and may provide a small damping effect on the system. On the other hand, the voltage at the PCC v PCC is an available signal to be measured. For control design purposes, an average model of the system is considered instead. For this, the switching signals δ 1 and δ 2 are replaced by the corresponding duty ratios d 1 and d 2 , which abide by the continuous range [−1, 1]. That is, in the above model, only the definitions of u a and u b are modified as follows: which, in principle, makes e AF a continuous signal and smooths the dynamics of all three states x G , x R , and x B . Notice that the duty cycles can be recovered from (9) as follows: The usage of averaged models for control design is a widely-accepted practice and is supported by the fact that the switching frequency of the power converter is at least 10 times higher than the bandwidth of the closed-loop system dynamics. Based on the system model (3)-(8), the following three control objectives can be stated, namely current tracking, voltage balance, and voltage regulation objectives:

O1.
Current tracking objective: An inner (current) control loop is designed to guarantee tracking of the state x G towards a desired reference x * G , i.e., (Without loss of generality, time dependency is only explicitly used in (11) and (13)- (15). Throughout the paper, time dependency is omitted for simplicity.): where the current reference is calculated as: where v PCC,1 is the fundamental component of v PCC and v PCC,RMS its RMS value. In practice, v PCC may be polluted by harmonic distortion, and thus, it is preferred to construct the current reference x G (t) in terms of the fundamental component. Signal v PCC,1 can be obtained from an external filter or with a phase-locked loop (PLL) scheme [35]. The term p represents the active power reference of the system, which modulates the amplitude of the grid current. The scalar term p is obtained from the outer (regulation voltage) control loop, as will be explained later.
O2. Voltage regulation objective: An outer (regulation voltage) loop is designed to maintain (on average) the DC-link voltage regulated to a desired constant value V DC . In particular, this control objective is expressed as: where x R 0 represents the DC component of x R and is used to address the average of x R , which is extracted using the following averaging function: where T represents the fundamental period of the disturbance signal; in this case, a second order harmonic of the fundamental is expected, and thus, T = π/ω can be proposed.
As an outcome of this control loop, the power reference p is obtained. The regulation objective must guarantee that the DC-Link stores enough energy to allow the appropriate injection of the compensating (reactive and harmonic) current to the PCC.
O3. Voltage balance objective: A balance loop is designed to guarantee that capacitors C 1 and C 2 , in the DC-bus, achieve the same voltage level. This avoids asymmetries on the reconstructed injected voltage and guarantees a safe operation of the capacitors. Equivalently, the balance objective is reached if the difference of the capacitor voltages x B goes to zero, that is, Additional to the control objectives above defined, the following assumptions are formulated based on the physical construction of the system. These assumption allow, in principle, decoupling the model of the system into three separated dynamics, which permits a simplified analysis and design of the control scheme and establishing the parameter tuning rules.

A1.
The inductor current dynamics is faster than the voltage dynamics (in the closed loop). Furthermore, the voltage balance dynamics is considered faster than the voltage regulation dynamics (in the closed loop). Hence, the controller design procedure can be divided into three independent loops' design (one loop for each dynamics). This is commonly referred to as the decoupling assumption and is based on the singular perturbation theory and analysis [36], i.e., a time scale separation. A2.
The fundamental frequency of the grid voltage ω = 2π f G is a known constant. A3.
The i NLL , as well as the v PCC are periodic signals (may be perturbed by harmonic disturbances) with a fundamental frequency ω, and thus, they can be described by Fourier series as follows: where V P,h and I NL,h are the vectors of unknown harmonic coefficients. Normally, for single-phase systems, such a harmonic distortion is only comprised of odd harmonics, i.e., harmonics in the set H G = {1, 3, 5, . . .}.

A4.
The system parameters L F , C, and R are considered positive unknown constants or may vary slowly due to the aging effect.

Controller Design
Based on Assumption A1, the system can be split into three dynamics, each accompanied by its corresponding controller design. The design is thus performed in three separated loops referred to as the current tracking loop, voltage balance loop, and voltage regulation loop, which are explained in detail next.

Current Tracking Loop
The system current dynamics is described by Subsystem (3), where signal e AF has become a continuous signal after the averaging argumentation, i.e., after replacing the switching signals δ 1 and δ 2 by the corresponding duty ratios d 1 and d 2 , as above explained The new e AF can be seen as a filtered version of the generated VSI output voltage. However, e AF represents the actual control input of Subsystem (3), and thus, it becomes the reference voltage to be reconstructed by the VSI.
Notice that e AF in (6) is comprised of two terms. First is the term ε AF = x R u a /2, which is designed to solve the current tracking issue, i.e., to produce the appropriate injected current. Second is the term x B u a u b /2, which is a vanishing term, i.e., it equals zero in the steady state after the voltage balance is reached.
Rewriting the current dynamics (3) in terms of the increments yields the following system referred to as the error model: is the error (or increment) of the grid current, i.e., the feedback state; ε AF is the non-vanishing part of e AF ; the term x B u a u b 2 is considered as a vanishing perturbation; R P = ∆ R F + R G is an unknown positive lumping the parasitic resistances of the system; and φ H is a term where periodic signals are collected as follows: Subsequently, based on Assumption A3, the term φ H contains similar harmonic contents as the NLL.
Based on the error model (16) and the periodic properties of term φ H above described, the following control law is proposed: The proposed control law in (18) is comprised of three terms. First, a feedforward term v PCC is added to alleviate the exogenous perturbation produced by the effect of the grid impedance. Second, a proportional term, associated with proportional gain k C > 0, is included to add damping to the system. Third, a harmonic compensation termφ H is included to cope with the harmonic term φ H considered as a perturbation. The design of this latter follows the ideas in [34], which appealed to the internal model principle [37].
Subsystem (16) in the closed loop with the proposed control law (18) yields the following error model: whereφ H is designed as described in [34], which consists of a bank of second-order harmonic oscillators, i.e., a bank of resonant filters tuned at odd harmonics of the fundamental frequency. The control law (18) can be written as: where λ h > 0 is the gain of the h-th oscillator tuned at the hω-th harmonic.
Notice that the design of the current tracking loop neglects the vanishing perturbation x B u a u b /2 appearing in (16). This is based on the fact that the balance loop, to be described next, guarantees x B → 0, while u a and u b are bounded by construction and relatively small, and thus, the product yields a relatively small amount.
Based on the structure of (17), it is proposed to calculate the auxiliary control variable u a , which is necessary to recuperate the duty cycles d 1 and d 2 according to (10), as follows:

Regulation and Balance Control Loops
The design of the voltage balance and regulation loops appeals to the decoupling Assumption A1. This is guaranteed if a suitable design of the physical system and selection of the adequate control parameters is performed. As a consequence, the current dynamics reach the steady state faster than the rest of the system. Therefore, it is assumed that x G = x * G in a relatively short time, which means thatx G = 0 and ε AF = v PCC .

Voltage Balance Control Loop
The design of the voltage balance loop considers Subsystem (5) evaluated at the steady state value of the control input (21) above described and subject to the restriction x G = x * G . The dynamics of the voltage balance can thus be rewritten as follows: This is a first-order system (22) with control input u b affected by a constant term. The term p = ∆ x * G v PCC 0 is calculated at the regulation loop to be explained later, while the term i NLL v PCC = ∆ P L represents the load consumed power. Hence, the power term (p − P L ) coincides with the power losses of the system collected in the term R, i.e., p − P L ∼ = 2V 2 DC /R. In fact, a more convenient representation for (22) is the following: Based on the structure of (23), the following control law is proposed to guarantee voltage balance. It consists of a proportional plus an integral controller: where k pB is a proportional gain and k iB is an integral gain of the proposed PI controller; χ B is an auxiliary variable to realize the integral part. The auxiliary control signal u b together with u a above calculated in the current tracking loop are necessary to recuperate the duty cycles d 1 and d 2 according to (10).

Voltage Regulation Control Loop
The voltage regulation loop aims to guarantee that the DC-link is charged to a desired V DC voltage level well above the grid voltage peak value. This is a necessary condition to allow proper compensation of harmonic distortion and reactive power, as above explained. The design of the voltage regulation control loop considers Subsystem (4). The decoupling assumption A1 is also considered, out of which the control signal ε AF in (18) has reached its steady state value. Therefore, the voltage regulation dynamics are simplified as follows: where the following transformation to the new state variable z R has been used: After this variable transformation, the voltage regulation objective (O2) changes to guarantee regulation of the new variable z R towards a desired reference V 2 DC 2 . Expressing Subsystem (26) in terms of increments of the new variable z R yields the following system: where the errorz R is defined as:z and the term p is used only to consider the DC component of the product x * G v PCC , that is p = ∆ x * G v PCC 0 . Notice that p acts as the control input in the system (28).
Based on the structure of the system (28), the following modified PI control law is proposed to guarantee voltage regulation (on average): where k pR > 0 is the proportional gain and k iR > 0 is the integral gain. Notice that, in the proposed modified PI controller (29), the proportional term includes a first-order low-pass filter with a time constant given by τ R . This modification of the PI controller avoids the reinjection of the ripple present in z R towards p . The block diagram of the overall proposed scheme is presented in Figure 3. Notice that the resulting control scheme makes use of two PI controller at voltage loops in combination with a proportional plus a bank of resonant filters at the current loop. The overall scheme can be easily implemented in a digital signal processor.

Tuning Guidelines
In what follows, tuning rules for the parameters of the proposed controller are presented to guarantee a desired closed-loop performance. These guidelines are based on the average model of the system, the control objectives, and the assumptions for the controller design.

Tuning Guidelines: Current Tracking Loop
As mentioned above, to guarantee the stability of the current tracking loop and the convergence of the tracking error x G to zero, it suffices to select k C > 0. However, to guarantee certain performance, it is still necessary to find certain boundaries as described next.
Consider the closed-loop dynamics of the current subsystem (19), which can also be expressed as: whereφ H = ∆φ H − φ H represents the harmonic disturbance estimation error. Note that the bandwidth of (30) is given by ω BWx G = k C /L F . Thereby, if ω BWx G is limited to be at most 1/10 of the sampling frequency 2π f s , then k C must fulfill:

Tuning Guidelines: Voltage Balance Loop
The tuning of parameters k pB and k iB of the voltage balance loop is based on Subsystem (22), which can be rewritten as follows: Its characteristic polynomial is given by: For this second-order system, the natural oscillation frequency and the damping factor are given by: By assuming that ωRC 10 and considering a critically damped response, then parameters k pB and k iB can be tuned according to:

Tuning Guidelines: Voltage Regulation Loop
The tuning of k pR , k iR , and τ R considers the closed-loop subsystem (29), which can be rewritten as: where ζ R is a state variable associated with the integral action and χ R is the state associated with the LPFmodification. It is a common practice to select τ R 1/(2ω), where ω is the fundamental frequency. Hence, the effect of the pole located at −1/τ R can be neglected from Subsystem (37), which is then reduced to a second order system. The characteristic polynomial of this reduced system is given by: where the damping factor and the natural oscillation frequency can be obtained as: If the damping factor is restricted to ς ≥ 1/ √ 2, then the bandwidth dynamics of the voltage regulation must comply with ω BWx R ≤ ω nR . Furthermore, in agreement with the time-scale separation assumption, the condition ω BWx R ω BWx G must hold. Moreover, to avoid the effect of the second harmonic fluctuation, ω x R can be further restricted to ω/5. Thus, the parameters can be selected according to: where it has been assumed that ωRC 20.

Numerical and Experimental Results
In this section, numerical and experimental results are given in order to assess the performance of the proposed control law. For the experimental results, R F , L G , and R G were unknown parameters. However, the controller was capable of dealing with these uncertainties.

Numerical Results
Numerical simulation results considering the system of Figure 4 are displayed in this part. For this purpose, PSCAD software was employed. The system parameters of the SAPF are shown in Table 2, and the controller parameters are depicted in Table 3.

Tracking Loop Regulation Loop Balance Loop
k C = 20 k iR = 0.016 k iB = 0.0008 λ 1 = 300 k pR = 0.035 k pB = 0.01 λ 3 = 700 τ R = 60 λ 5 = 1450 V DC = 220 λ 7 = 800 λ 9 = 80 λ 11 = 60 λ 13 = 60 The steady state responses of the voltage at the PCC v PCC , the grid current i G , the current demanded by the NLL i NLL , and the current injected by the SAPF i AF are shown in Figure 5. Notice that, despite the load current i NLL being highly distorted, the proposed control law was able to compensate the grid current i G to the desired sinusoidal waveform and in phase with the voltage at PCC v PCC ; where i AF is the quadrature current provided by the SAPF to compensate the nonlinear current i NLL . Note also that the THD of i G had a value of 1.75%, while the current consumed by the NLL i NLL presented a THD of 52.5%. Figure 6 shows the steady state responses of the voltage v PCC , the fundamental component of the voltage at the PCC v PCC,1 , the compensated current i G , and the VSI output voltage e AF . At this point, it is worth mentioning that the grid current i G was constructed using the fundamental component of the grid voltage v PCC,1 to avoid the harmonics re-injection through the current reference of the current control loop. The computation of the current reference using v PCC,1 guaranteed that the proposed control law was able to compensate the grid current i G to a sinusoidal signal and in phase with the grid voltage v PCC . Notice that v PCC,1 was obtained by using a band-pass filter as in [28] or by using an extra phase-locked loop algorithm [35]. The five-level output voltage of the multilevel converter e AF is also shown in this figure.  The transient responses of the voltage across each capacitor of the DC-Link v C1 , v C2 , the sum of the capacitors voltage x R , and the power reference calculated in the regulation loop p * during a step change in the NLL are presented in Figure 7. It can be noted that during the change in the power demand, the voltage regulation loop was capable of maintaining the voltage on each capacitor of the DC-Link v C1 , v C2 at the desired value of 110 V each, after a smooth transient. Moreover, in Figure 8, it is possible to observe that the difference between v C1 and v C2 was zero on average, which demonstrated the effectiveness of the voltage balance loop facing the changes in the power demand. Furthermore, the current tracking loop exhibited a smooth waveform transition during the power demand, increasing or decreasing the amplitude of i G as required. Figure 9 shows the transient responses of the grid current i G , the current consumed by the NLL i NLL , and the current injected from the SAPF i AF during a change of power at the NLL. Note that the waveforms of i G and i AF did not present any undesirable overshoot during the load changes. In order to further evaluate the performance of the proposed control law, an RLload connected to the output of the uncontrolled bridge rectifier was considered for evaluation. In this case and only for this numerical evaluation case, the electrical NLL consisted of a single-phase uncontrolled rectifier (NLL-H in Figure 4) with R L2 = 100 Ω, R NL2 = 15 Ω and L L2 = 12 mH, considering two different sizes of inductive output filters L F = 2 mH in Figure 10a and was reduced to L F = 1 mH in Figure 10b. Therefore, in Figure 10a, the steady state responses of the voltage at the point of common coupling v PCC , the grid current i G , the current demanded by the NLL i NLL , and the current injected by the SAPF i AF are presented. Despite the connection of a different NLL, the controller was capable of achieving an almost sinusoidal current i G . Nevertheless, a slight deviation appeared as small peaks during the load current zero-crossing on the compensated grid current i G . This fact occurred given that the slope of NLL was close to 90 o , which was produced by the bulky inductance of NLL, and the size of the output filter helped to eliminate the switching frequency, conversely limiting the current compensation capacity in pronounced slopes. Note that the current deformation was able to be alleviated if a small output inductance was placed as in Figure 10b, but the switching ripple increased. Notice also that the total compensation of this spike was not possible given the well-known limitations imposed by the output filter (∆i AF /∆t). On the other hand, the grid current i G was in phase with the voltage at the PCC v PCC in both cases, which proved the benefits of the controller for power quality improvement despite the NLL loads connected at the PCC. For Figure 10a, the THD of the compensated grid current i G was 1.49%; meanwhile, for NLL current i NLL , the THD was 17.1%. On the other hand, for the compensated grid current i G of Figure 10b, the THD was 1.1%; meanwhile, the THD of the NLL i NLL stayed at the same value of 17.1%. Notice that the THD of the compensated grid current i G in both cases reached values less than 5%.

Experimental Results
The performance of the SAPF based on the 5L-HB-NPC inverter under the proposed controller was experimentally tested in a 2 kW prototype with a constant switching frequency of 7 kHz. The 5L-HB-NPC as an SAPF was implemented as shown in Figure 4. The system parameters for the academic prototype are summarized in Table 2. As depicted in Figure 4, the SAPF was connected to the PCC to compensate the nonlinear currents produced by the NLL. The i NLL was produced by a pair of NLLs, which were implemented as uncontrolled diode bridge rectifiers feeding an RCload composed of a resistor R NLn , a capacitor C NLn , and an input inductance L L n. Furthermore, a linear resistor R L n was connected at the input of each NLL to increment the power demand. The combination of these load produced a distorted current referred as i NLL to be compensated by the SAPF. Notice that n = 1, 2 was used to refer to the fixed low nonlinear load (NLL-L) or the switched high nonlinear load (NLL-H). The system parameters of the SAPF are summarized in Table 2. The SAPF was implemented using the discrete semiconductors IRG4PC40FD as IGBT switching elements and the semiconductor MUR3060WT as a clamped diode. The control law was implemented in a dSPACE 1104 control board. The parameters of the controller were tuned according to the above guidelines and are listed in Table 3. The current sensor was CLN-50, and the voltage sensors were LV25P. Figure 11 shows the steady state responses (measured at the PCC) of the voltage v PCC , the grid current i G , the current consumed by the NLL i NLL , and the injected current i AF from the SAPF. Notice that the voltage at the PCC presented harmonic distortion. Nevertheless, the grid current i G showed an almost pure sinusoidal waveform in phase with the voltage waveform despite the NLL connected to the PCC. This came from the fact that the fundamental component of v PCC was used as a basis to construct the current reference. This corroborated the tracking of the grid current i G towards its sinusoidal reference. Figure 11. Steady state responses at the PCC after the current compensation process of: (CH1) the voltage v PCC (y-axis 250 V/div); (CH2) the grid current i G (y-axis 15 A/div); (CH3) the current consumed by the NLL i NLL (y-axis 15 A/div); and the injected current i AF (y-axis 15 A/div, x-axis 4 ms/div).
The steady state responses at the PCC of the voltage v PCC and the estimation of its fundamental component v PCC,1 together with their corresponding frequency spectra are depicted in Figure 12. Notice that the signal v PCC contained harmonic distortion, that is some odd harmonics components were present. Nevertheless, the fundamental component estimate v PCC,1 did not show any harmonic distortion. This was crucial in the proposed controller as v PCC,1 was used in the construction of the current reference according to (12).  Figure 13 shows the steady state responses of the grid voltage v PCC , the fundamental component estimate of the grid voltage v PCC,1 , the grid current i G , and the multilevel output voltage generated by the VSI e AF . It can be observed that all signals were in phase, in particular the grid current i G and the voltage v PCC . Furthermore, it can be observed that the injected voltage e AF exhibited five levels, as expected.   To evaluate the current and voltage dynamical response of the system variables, Figure 15 shows transient responses under the proposed controller during stepwise changes on the power demand p . Notice that the sum of the capacitor voltages x R was regulated to the desired value despite the changes in the power demand. Moreover, it was observed that the capacitor voltage difference, represented by x B , was maintained at zero (in average) and exhibited almost imperceptible transients. This corroborated that the controller guaranteed the voltage balance while keeping the capacitor voltages at a reference of 220 V DC . Note also that the grid current i G increased proportional to the power demanded by the system, and the envelope did not exhibit any overshoot during the transients. Figure 15. Transient responses during NLL stepwise changes of: (CH1) the sum of the capacitor voltage x 2 (y-axis 50 V/div); (CH2) the difference of the capacitors voltages x 3 (y-axis 50 V/div); (CH3) the power reference p * calculated in the regulation loop (y-axis 50 V/div); and (CH4) the grid current i G . Figure 16 shows the transient responses, during a change of the power demanded by the NLL, of the grid current i G , the current consumed by the NLL i NLL , and the current injected by the SAPF i AF .
Notice that, during the stepwise changes on the power demand, the current i G exhibited a fast and smooth response without any overshoot.  Figure 17 depicts the steady-state responses of the grid current i G and the current consumed by the NLL i NLL , together with their corresponding frequency spectra. Notice that the grid current i G had a quasi-sinusoidal waveform with a THD of 2.32%, while the demanded current by the NLL i NLL had a THD of 53.8%. This represented a noticeable power quality improvement. This was also corroborated by comparing the frequency spectra. Notice that, despite the harmonic pollution observed in the frequency spectra of i NLL , the grid current i G did not exhibit a perceivable harmonic distortion. Figure 17. Steady state responses of: (CH1) the grid current i G (y-axis 15 A/div, x-axis 4 ms/div); (R2) the frequency spectra of i G (y-axis 40 dB/div, x-axis 125 Hz/div); (CH2) the current consumed by the NLL i NLL (y-axis 15 A/div, x-axis 4 ms/div); and (R3) the frequency spectra of i NLL (y-axis 40 dB/div, x-axis 125 Hz/div).

Concluding Remarks
In this work, a control law for a shunt active power filter based on the five-level full-bridge NPC multilevel topology was presented. The control law comprised three control loops aimed to guarantee the control objectives of grid current tracking, DC-link voltage balance, and DC-link voltage regulation. The resulting control law was designed appealing to a dynamics decoupling assumption.
This assumption simplified enormously the control design as it was split into three independent control loops referred to as current, balance, and regulation loops. The current control loop resulted in a combination of a proportional controller aimed to provide damping to the system and a bank of resonant filters aimed to compensate reactive power and harmonic distortion. Regarding the balance and regulation control loops, PI controllers were obtained in each case. In particular, the PI controller of the regulation control loop involved a slight modification, which consisted of the introduction of a low pass filter in the proportional gain to limit the bandwidth of the overall loop. This consideration alleviated the effects and propagation of the unavoidable second harmonics fluctuation in the DC-link voltage produced by the rectification process. Finally, the control law was evaluated in an experimental 2 kW setup of the shunt active power filter based on the five-level full-bridge NPC multilevel topology. The experimental results showed that the active power filter under the proposed controller was able to guarantee an operation with a power factor close to unity and a grid current with less than 5% THD.
Author Contributions: All authors contributed to the development of the overall document, control design, and experimental results. All authors read and agreed to the published version of the manuscript.

Conflicts of Interest:
The authors declare no conflict of interest.

Abbreviations
The following abbreviations and symbols are used in this manuscript: