Circuit Structure and Control Method to Reduce Size and Harmonic Distortion of Interleaved Dual Buck Inverter

: A new circuit structure and control method for a high power interleaved dual-buck inverter are proposed. The proposed inverter consists of six switches, four diodes and two inductors, uses a dual-buck structure to eliminate zero-cross distortion, and operates in an interleaved mode to reduce the current stress of switch. To reduce the total harmonic distortion at low output power, the inverter is controlled using discontinuous-current-mode control combined with continuous-current-mode control. The experimental inverter had a power-conversion e ﬃ ciency of 98.5% at output power = 1300 W and 98.3% at output power = 2 kW, when the inverter was operated at an input voltage of 400 V DC , output voltage of 220 V AC / 60 Hz, and switching frequency of 20 kHz. The total harmonic distortion was < 0.66%, which demonstrates that the inverter is suitable for high-power dc-ac power conversion.


Introduction
The full-bridge inverter (FBI, Figure 1a) is widely used for dc-ac power conversion because of its simple structure and easy control [1]. An FBI uses sinusoidal modulation of the switching duty to produce an alternating output voltage. The FBI has a shoot-through problem [2], which occurs when the high side and low side switches (S 1 and S 4 , or S 3 and S 2 ) are turned on at the same time; this problem can cause serious circuit damage. The shoot-through problem can be solved by inserting a dead-time between the gate pulses of the high and low side switches, but inserting a dead-time changes the effective switching duty ratio and increases zero-cross distortion (ZCD) [3]. The FBI has the other disadvantage of requiring high-rated switches and large output filters [4,5].
Various dual-buck inverters [6][7][8][9][10][11][12][13][14][15] have been proposed to remedy the disadvantages of the FBI. The dual-buck inverters use freewheeling diodes to solve the shoot-through problem but have high output current ripple. The interleaved dual-buck inverter (IDBI) in [9], as shown in Figure 1b, is basically a parallel connection of four buck converters. In this inverter, S U1 and S U2 operate to generate positive sinusoidal voltage, S D1 and S D2 operate to generate negative sinusoidal voltage, and the switching-phase differences between S U1 and S U2 and between S D1 and S D2 are set to 180 • . Thus, the current of S U1 is interleaved with that of S U2 , and the current of S D1 is interleaved with that of S D2 . Using an interleaved mode reduces conduction losses, output current ripple, and current stress in switches and diodes. IDBI requires four inductors, so it is expensive and bulky. When IDBI uses typical sinusoidal pulse width control and operates at a low output power P o , IDBI has much higher total harmonic distortion (THD) of the output current than that of the FBI.  [9] (IDBI [9]).
The inverter proposed in this paper ( Figure 2) is a modified IDBI. This inverter inherits the IDBI's advantages but uses two reverse-current-protection diodes DD3 and DU3 to reduce the number of inductors and a new control method to reduce the THD of the output current. The proposed inverter operates in discontinuous conduction mode (DCM) [16] when the output current is below the threshold; otherwise, it operates in continuous conduction mode (CCM). The circuit structure and principle of operation are described in Section 2, experimental results and discussions are given in Section 3, and a conclusion is given in Section 4.

Circuit Structure and Principle of Operation
The proposed inverter ( Figure 2) uses two dual-buck legs (leg 1: SU1, DU1; leg 2: SU2, DU2) to generate Vgrid ≥ 0 V, two dual-buck legs (leg 3: SD1, DD1; leg 4: SD2, DD2) to generate Vgrid < 0 V, two blocking diodes (DU3, DD3) to prevent the current flowing through the body diode of switch during freewheeling mode, and two unfolding switches (SU3, SD3) to determine the polarity of the output current. Legs 1 and 4 are connected to L1, and legs 2 and 3 are connected to L2. Therefore, the proposed inverter requires two inductors, unlike interleaved dual-buck inverters, which have four legs and one inductor per leg. The proposed inverter works with the switching states and leg voltages VAN_on and VAN_off in Table I. Leg switches SU1, SU2, SD1, and SD2 operate at a fixed switching frequency fs = 1/Ts, where Ts is the switching period. The switching duty D is varied to produce a sinusoidal output voltage The simplified gate signals ( Figure 3) for the proposed inverter show that legs 1 and 2 operate for Vgrid > 0 V and legs 3 and 4 operate for Vgrid < 0 V. SU3 turns for Vgrid ≥ 0 V and SD3 turns on for Vgrid < 0 V. To obtain interleaved dual-buck operation, the switching phase differences between SU1 and SU2 and between SD1 and SD2 are set to Ts/2. The difference in switching phases reduces ZCD and prevents shoot-through without inserting dead time between switching pulses (Table 1).  [9] (IDBI [9]).
The inverter proposed in this paper ( Figure 2) is a modified IDBI. This inverter inherits the IDBI's advantages but uses two reverse-current-protection diodes D D3 and D U3 to reduce the number of inductors and a new control method to reduce the THD of the output current. The proposed inverter operates in discontinuous conduction mode (DCM) [16] when the output current is below the threshold; otherwise, it operates in continuous conduction mode (CCM). The circuit structure and principle of operation are described in Section 2, experimental results and discussions are given in Section 3, and a conclusion is given in Section 4.
The inverter proposed in this paper ( Figure 2) is a modified IDBI. This inverter inherits the IDBI's advantages but uses two reverse-current-protection diodes DD3 and DU3 to reduce the number of inductors and a new control method to reduce the THD of the output current. The proposed inverter operates in discontinuous conduction mode (DCM) [16] when the output current is below the threshold; otherwise, it operates in continuous conduction mode (CCM). The circuit structure and principle of operation are described in Section 2, experimental results and discussions are given in Section 3, and a conclusion is given in Section 4.

Circuit Structure and Principle of Operation
The proposed inverter ( Figure 2) uses two dual-buck legs (leg 1: SU1, DU1; leg 2: SU2, DU2) to generate Vgrid ≥ 0 V, two dual-buck legs (leg 3: SD1, DD1; leg 4: SD2, DD2) to generate Vgrid < 0 V, two blocking diodes (DU3, DD3) to prevent the current flowing through the body diode of switch during freewheeling mode, and two unfolding switches (SU3, SD3) to determine the polarity of the output current. Legs 1 and 4 are connected to L1, and legs 2 and 3 are connected to L2. Therefore, the proposed inverter requires two inductors, unlike interleaved dual-buck inverters, which have four legs and one inductor per leg. The proposed inverter works with the switching states and leg voltages VAN_on and VAN_off in Table I. Leg switches SU1, SU2, SD1, and SD2 operate at a fixed switching frequency fs = 1/Ts, where Ts is the switching period. The switching duty D is varied to produce a sinusoidal output voltage The simplified gate signals ( Figure 3) for the proposed inverter show that legs 1 and 2 operate for Vgrid > 0 V and legs 3 and 4 operate for Vgrid < 0 V. SU3 turns for Vgrid ≥ 0 V and SD3 turns on for Vgrid < 0 V. To obtain interleaved dual-buck operation, the switching phase differences between SU1 and SU2 and between SD1 and SD2 are set to Ts/2. The difference in switching phases reduces ZCD and prevents shoot-through without inserting dead time between switching pulses (Table 1).

Circuit Structure and Principle of Operation
The proposed inverter ( Figure 2) uses two dual-buck legs (leg 1: S U1 , D U1 ; leg 2: S U2 , D U2 ) to generate V grid ≥ 0 V, two dual-buck legs (leg 3: S D1 , D D1 ; leg 4: S D2 , D D2 ) to generate V grid < 0 V, two blocking diodes (D U3 , D D3 ) to prevent the current flowing through the body diode of switch during freewheeling mode, and two unfolding switches (S U3 , S D3 ) to determine the polarity of the output current. Legs 1 and 4 are connected to L 1 , and legs 2 and 3 are connected to L 2 . Therefore, the proposed inverter requires two inductors, unlike interleaved dual-buck inverters, which have four legs and one inductor per leg. The proposed inverter works with the switching states and leg voltages V AN_on and V AN_off in Table 1. Leg switches S U1 , S U2 , S D1 , and S D2 operate at a fixed switching frequency f s = 1/T s , where T s is the switching period. The switching duty D is varied to produce a sinusoidal output voltage V grid (t) = V g sin(ωt).
The simplified gate signals ( Figure 3) for the proposed inverter show that legs 1 and 2 operate for V grid > 0 V and legs 3 and 4 operate for V grid < 0 V. S U3 turns for V grid ≥ 0 V and S D3 turns on for V grid < 0 V. To obtain interleaved dual-buck operation, the switching phase differences between S U1 and S U2 and between S D1 and S D2 are set to T s /2. The difference in switching phases reduces ZCD and prevents shoot-through without inserting dead time between switching pulses (Table 1).   When Vgrid > 0 V, the current iL1 and voltage VL1 waveforms of the inductor L1 ( Figure 4a) consist of three operating modes: Mode 1 during which the input energy is delivered to L1 and the load; Mode 2 during which the stored energy in L1 is delivered to the load; and Mode 3 during which the stored energy in L1 = 0; Mode 3 occurs only when the inverter operates in DCM.
Mode 1 starts at by turning on SU1 (Figure 4b), where the integer n is a switching sequence number. During this mode, the output voltage Mode 2 starts at by turning off SU1 (Figure 4c). During this mode, Mode 3 starts at is duration of  When V grid > 0 V, the current i L1 and voltage V L1 waveforms of the inductor L 1 (Figure 4a) consist of three operating modes: Mode 1 during which the input energy is delivered to L 1 and the load; Mode 2 during which the stored energy in L 1 is delivered to the load; and Mode 3 during which the stored energy in L 1 = 0; Mode 3 occurs only when the inverter operates in DCM.
Mode 1 starts at t 0 = (n − 1)T s by turning on S U1 (Figure 4b), where the integer n is a switching sequence number. During this mode, the output voltage Mode 2 starts at t 1 = (n − 1 + D)T s by turning off S U1 (Figure 4c). During this mode, Mode 3 starts at t 2 = (n − 1 + ∆)T s where ∆T s is duration of i L1 (t) > 0, when D U1 is turned off (Figure 4d). This mode is skipped when ∆ = 1, i.e., when the inverter is operating in CCM. During this mode, V AN = V grid because i L1 (t) = 0 and the energy stored in L 1 is 0. The voltage V AN of node A with respect to node N equals to V grid + V L1 (t). The switching states (Table 1) produce V AN = V in in Mode 1, V AN = 0 V in Mode 2, and V AN = V grid in Mode 3. The average of V AN for one switching period is expressed as S U1 operates with a switching duty of D = D SU1 . V AN_avg can also be expressed as because V AN = V in in Mode 1, V AN = 0 V in Mode 2, and V AN = V grid in Mode 3. Solving for ∆ using (3) and (4) yields i L1_avg is calculated using Equations (1) and (2) as  The voltage AN V of node A with respect to node N equals to ) . The switching states ( SU1 operates with a switching duty of D = DSU1. avg AN V _ can also be expressed as To achieve a power factor of 1, the time average of output current i o_avg should be I o sin(ωt) for V grid (t) = V g sin(ωt). The inverter has L 1 = L 2 = L and operates in interleaved dual-buck mode, so i o_avg = 2i L1_avg . When the inverter operates in DCM, D SU1 at t = t 0 to produce sinusoidal i o_avg is obtained using Equations (5) and (6), 2π f s >> ω and i L1 (t 0 ) = 0 as When the inverter is operating in CCM, ∆ = 1 and D SU1 at t = t 0 is obtained using Equation (5) as The DCM interval during which the inverter operates in DCM is calculated using Equations (5), (7), and ∆ ≤ 1 as when V grid increases, and when V grid decreases. The condition for operating the inverter only in CCM is obtained by setting the argument of arcsine in Equations (9) and (10) less than 0, and is given as and the condition for operating the inverter only in DCM is obtained by setting the argument of arcsine in Equations (9) and (10) greater than 1, and is given as The waveforms i L2 and V L2 of the inductor L 2 for V grid > 0 V are the same as i L1 and V L1 except that they are delayed by T s /2.
The waveforms i L1 , V L1 , i L2 , and V L2 for V grid < 0 V are identical to the waveforms i L2 , V L2 , i L1 , and V L1 for V grid > 0 V, respectively, except that the polarity is reversed.

Design Constraint for L 1 and L 2
The inverter must operate at I o ≤ I o,max . The highest switching duty D SU1_max of S U1 is calculated using Equation (8) as which results in the upper bound of This condition gives L < 103.44 mH when P o = 2 kW and I o_max = 12.9 A.
Energies 2020, 13, 1531 6 of 19 The current and voltage waveforms for L 2 are same as those for L 1 , except the time delay by T s /2; hence, the output current ripple i o_ripple of the proposed inverter can be calculated using Equations (1), (2) and (8) as for 0 < D < 1/2 and for 1/2 < D < 1; the highest i o_ripple occurs at D = 1/4 or 3/4. After allowing the highest i o_ripple of 1 A at P o = 2 kW and f s = 20 kHz (this condition corresponds to THD < 3%), the lower bound of L is obtained using Equations (15) and (16) as L min = 2.5 mH was used in the experimental inverters to minimize the inductor size.

Controller Design
The controller ( Figure 5) was designed using Texas Instrument's TMS320F28335 digital signal processor (DSP). This controller inputs V grid , i o_avg , and V in and uses the D-Q axis control method [17] to produce gating signals S U1 − S U3 and S D1 − S D3 that can generate a sinusoidal i o_avg . The controller consists of a phase-locked loop (PLL), a D-Q axis controller, and a gate pulse generator. The DSP operates at a clock frequency f clk = 1/T clk = 150 MHz and the sampling frequency is the same as the switching frequency f s = 1/T s = 20 kHz. Thus, the sampling sequence number n is in the range of 0 ≤ n ≤ 332 when the grid frequency f = ω/2π = 60 Hz, and clock sequence number j is in the range of 0 ≤ j ≤ 7499.
for 0 < D < 1/2 and    for 1/2 < D < 1; the highest kHz (this condition corresponds to THD < 3%), the lower bound of L is obtained using Equations (15) and (16) as mH was used in the experimental inverters to minimize the inductor size.

Controller Design
The controller ( Figure 5) was designed using Texas Instrument's TMS320F28335 digital signal processor (DSP). This controller inputs Vgrid, io_avg, and Vin and uses the D-Q axis control method [17] to produce gating signals SU1 − SU3 and SD1 − SD3 that can generate a sinusoidal io_avg. The controller consists of a phase-locked loop (PLL), a D-Q axis controller, and a gate pulse generator. The DSP operates at a clock frequency fclk = 1/Tclk = 150 MHz and the sampling frequency is the same as the switching frequency fs = 1/Ts = 20 kHz. Thus, the sampling sequence number n is in the range of 0 ≤ n ≤ 332 when the grid frequency f = 2 = 60 Hz, and clock sequence number j is in the range of 0 ≤ j ≤ The PLL ( Figure 6) sets n = 0 and starts to operate when Vgrid = 0 and the enable signal EN = 1. This circuit inputs Vgrid and estimates the amplitude Vg and phase

A/D converter
, the PLL generates a virtual grid-voltage Vgrid_qs as The PLL ( Figure 6) sets n = 0 and starts to operate when V grid = 0 and the enable signal EN = 1. This circuit inputs V grid and estimates the amplitude V g and phaseθ =ωt of V grid . Using V grid [n] = V g sin(θ[n]), the PLL generates a virtual grid-voltage V grid_qs as has been set to 0 if V grid_ qs [0] ≥ 0 and to π otherwise. Thus, the initial estimation error e θ [0] = θ[0] −θ[0] is very small. V grid and V grid_qs are transformed into the voltages V grid_d and V grid_q in the synchronous reference frame as Energies 2020, 13, 1531 can be calculated using Equations (20) and (21). The PLL loop filter for a proportional-integral (PI) control produceŝ This equation is equivalent tô can be calculated using Equations (20) and (21). The PLL loop filter for a proportional-integral (PI) control produces The D-Q axis controller (Figure 7) consists of a CCM duty-calculator and a duty compensator. The CCM duty-calculator inputs i o_avg and V in from the inverter, andθ and V g from the PLL. In the CCM duty-calculator, i o_avg = i o_ds is delayed by π/2 to obtain the virtual current i o_qs of i o_avg . The D-Q transformation separates i o_avg into a D component I o_d parallel to the grid voltage and a Q component I o_q orthogonal to the grid voltage: For given I 0_d and I o_q , the circuit topology results in the D-Q components of V AN in the synchronous reference frame as and the D-Q components of the switching duty as because V AN_d = V in D d and V AN_q = V in D q . The D-Q axis controller inputs I o_d_ref and I o_q_ref as the reference values of I o_d and I o_q , respectively, and calculates the errors e d [n] = I o_d_re f − I o_d and e q [n] = I o_q_re f − I o_q . Then, the controller generates the D-Q components of the switching duty for CCM operation: For given I0_d and Io_q, the circuit topology results in the D-Q components of VAN in the synchronous reference frame as and the D-Q components of the switching duty as . Then, the controller generates the D-Q components of the switching duty for CCM operation: (28) that is given in Equation (8).
Energies 2020, 13, 1531 9 of 19 The duty compensator inputs V in from the inverter,θ and V g from the PLL, and I o_d_ref from CCM duty-calculator. Then, the compensator uses in Equations (7) and (8) to calculate the steady-state duty difference ∆D between the switching duties for CCM and DCM operations. ∆D is given by The time fraction ∆ in Equation (5) for which i L 0 is calculated using Equation (7) as which yields This equation shows that the switching duty in Equation (7) for DCM operation is always smaller than the one in Equation (8)   (33) At each clock edge, S c [j] increases by 1 for nT s ≤ t < (n+(1/2))T s during which U/D 1 is UP, and S c [j] decreases by 1 for (n+(1/2))T s ≤ t < (n+1)T s during which U/D 1 is DOWN. When S c [j] < 0, U/D 1 changes to UP and the next sequence begins. S cp [j] decreases by 1 for nT s ≤ t < (n+(1/2))T s during which U/D 2 is DOWN, and S cp [j] increases by 1 for (n+(1/2))T s ≤ t < (n+1)T s during which U/D 2 is UP. U/D 2 changes to DOWN when S cp [j] < 0, and the next sequence begins.  [j]. Finally, the logic gates produce gate control pulses S U1 = C 1 ·C 3 , S U2 = C 2 ·C 3 , S U3 = C 3 , S D1 = C 1 ·C 4 , S D2 = C 2 ·C 4 , and S D3 = C 4 . Table 2. Input and output relationship of comparator array.

Experimental Results and Discussions
The proposed inverter (Figure 9a, Table 3) was designed to operate at V in = 400 V DC , V grid = 220 V AC /60 Hz and 150 W ≤ P o ≤ 2 kW, and it was fabricated and tested using the calculated circuit parameters. An IDBI [9] (Figure 9b, Table 3) and an FBI [1] (Figure 9c, Table 3) were also fabricated and tested for comparison; the circuit elements for these inverters were the same as those for the proposed inverter. The control circuits for all experimental inverters were implemented using the TMS320F28335 digital signal processor (DSP) from Texas Instruments.   The proposed inverter uses two inductors, whereas the IDBI uses four inductors, and the proposed inverter uses a small inductor core (EER6062), whereas the FBI uses a large inductor core. The fabricated inverters had a circuit volume of 160mm × 250 mm × 43.9 mm for the proposed inverter, 450 mm × 550 mm × 43.9 mm for the IDBI, and 380mm × 550 mm × 78.0 mm for the FBI; the proposed inverter reduced 83.8% of the circuit volume compared with the IDBI, and 89.3% compared The proposed inverter uses two inductors, whereas the IDBI uses four inductors, and the proposed inverter uses a small inductor core (EER6062), whereas the FBI uses a large inductor core. The fabricated inverters had a circuit volume of 160mm × 250 mm × 43.9 mm for the proposed inverter, 450 mm × 550 mm × 43.9 mm for the IDBI, and 380mm × 550 mm × 78.0 mm for the FBI; the proposed inverter reduced 83.8% of the circuit volume compared with the IDBI, and 89.3% compared with the FBI. The circuit cost was $71.04 for the proposed inverter, $77.74 for the IDBI, and $73.9 for the FBI; the proposed inverter saved 8.62% of the circuit cost compared with the IDBI, and 3.87% compared with FBI.
To verify operation of the proposed inverter, the waveforms of switch-control pulses (Figure 10a) were measured at Vin = 400 VDC, V grid = 220 V AC /60 Hz, P o = 2 kW, and f s = 20 kHz. These waveforms show that the switches operated according to the switching states in Table 1; when V grid > 0 V, S U1 and S U2 operated in PWM mode, S U3 stayed ON and other switches stayed OFF; when V grid < 0 V, S D1 and S D2 operated in PWM mode, S D3 stayed ON and other switches stayed OFF. The inductor currents i L1 and i L2 , and the leg voltages V GS_SU1 and V GS_SU2 (Figure 10b) show that the inverter operated in an interleaved mode; the phase differences between i L1 and i L2 , and between V GS_SU1 and V GS_SU2 were T s /2. These switching states produced the sinusoidal leg voltage V AN (Figure 10c). η e vs. P o (Figure 11) was measured at V in = 400 V DC , V grid = 220 V AC /60 Hz, 150 W ≤ P o ≤ 2 kW, and f s = 20 kHz and 40 kHz, using a PW3336 (HIOKI E.E. Co.) power meter. At f s = 20 kHz, the proposed inverter had η e > 98% for P o ≥ 500 W, but η e for P o < 500 W decreased as P o decreased because the inverter operated in DCM. The highest power conversion efficiency η emax of the proposed inverter was 98.5% at P o = 1300 W when the power loss P DSP of the gate control/drive circuit was included. (η emax = 99.2% at P o = 500 W when P DSP was excluded.) The FBI does not use the interleaved buck inversion; hence, the switching and conduction losses in the current path were higher in the FBI than in the proposed inverter; as a result, the FBI had the lowest η e among the inverters tested. The IDBI has a circuit structure similar to the proposed inverter and operates in interleaved mode, so η e of the IDBI was very close to that of the proposed inverter. However, the proposed inverter requires two inductors to operate the inverter in interleaved mode, while the IDBI requires four inductors; hence, the proposed inverter can be implemented in a smaller size. compared with FBI.
To verify operation of the proposed inverter, the waveforms of switch-control pulses ( Figure  10a) were measured at Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, Po = 2 kW, and fs = 20 kHz. These waveforms show that the switches operated according to the switching states in Table I; when Vgrid > 0 V, SU1 and SU2 operated in PWM mode, SU3 stayed ON and other switches stayed OFF; when Vgrid < 0 V, SD1 and SD2 operated in PWM mode, SD3 stayed ON and other switches stayed OFF. The inductor currents iL1 and iL2, and the leg voltages VGS_SU1 and VGS_SU2 (Figure 10b) show that the inverter operated in an interleaved mode; the phase differences between iL1 and iL2, and between VGS_SU1 and VGS_SU2 were Ts/2. These switching states produced the sinusoidal leg voltage VAN (Figure 10c). interleaved buck inversion; hence, the switching and conduction losses in the current path were higher in the FBI than in the proposed inverter; as a result, the FBI had the lowest e  among the inverters tested. The IDBI has a circuit structure similar to the proposed inverter and operates in interleaved mode, so e  of the IDBI was very close to that of the proposed inverter. However, the proposed inverter requires two inductors to operate the inverter in interleaved mode, while the IDBI requires four inductors; hence, the proposed inverter can be implemented in a smaller size.   and 29.71 W for FBI at P o = 2kW, and P SW were 2.18 W for proposed, 2.48 W for IDBI, and 8.42 W for FBI at P o = 150 W. The inverters operated at V SW = V in and N SW = 666 for proposed and IDBI, and V SW = V in and N SW = 1333 for FBI, where N sw is the total switching number for one cycle of V grid . Thus, the proposed inverter and IDBI had the lowest P SW . The inductor loss P IND was 9.25 W for proposed, 10.33 W for IDBI, and 66.32 W for FBI at P o = 2kW and 0.155 W for proposed, 0.162 W for IDBI, and 0.66 W for FBI at P o = 150 W. The proposed inverter uses interleaved inputs; hence, the inductor current i L is half of the i L of FBI. Moreover, the proposed inverter uses small inductors with fewer turns than that of the FBI. Thus, FBI had the highest P IND . The diode loss P D was 7.04 W for proposed, 6.45 W for IDBI, and 0 for FBI at P o = 2 kW, and P D was 0.907 W for proposed, 0.885 W for IDBI, and 0 for FBI at P o = 150 W. The power loss P DSP of the gate control/drive circuit was 6.02 W for proposed, 6.19 W for IDBI, and 6.48 W for FBI at both P o = 150 W and P o = 2 kW. The total power loss P loss at P o = 2 kW was 35.53 W for proposed, 36.87 W for IDBI, and 102.51 W for FBI, and the power conversion efficiency η e at P o = 2 kW was 98.2% for proposed, 98.1% for IDBI, and 94.9 % for FBI. P loss at P o = 150W was 9.279 W for proposed, 9.717 W for IDBI, and 15.5 W for FBI, and η e at P o = 150 W was 93.8% for proposed, 93.5% for IDBI, and 89.6 % for FBI. Figure 11. ηe vs. Po for the experimental inverters operating at (a) fs = 20 kHz and (b) fs = 40 kHz: measured at Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, and Qo = 0 VAR. The power loss PDSP in the control circuit was included in ηe measurement. Losses (Figure 12) of the experimental inverters were analyzed at Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, fs = 20 kHz, Po = 2 kW and 150 W, and reactive output power Qo = 0 volt-ampere-reactive (VAR). The switching losses PSW were 13.2 W for proposed, 13.89 W for IDBI, and 29.71 W for FBI at Po = 2kW, and PSW were 2.18 W for proposed, 2.48 W for IDBI, and 8.42 W for FBI at Po = 150 W. The inverters operated at VSW = Vin and NSW = 666 for proposed and IDBI, and VSW = Vin and NSW = 1333 for FBI, where Nsw is the total switching number for one cycle of Vgrid. Thus, the proposed inverter and IDBI had the lowest PSW. The inductor loss PIND was 9.25 W for proposed, 10.33 W for IDBI, and 66.32 W for FBI at Po = 2kW and 0.155 W for proposed, 0.162 W for IDBI, and 0.66 W for FBI at Po = 150 W. The proposed inverter uses interleaved inputs; hence, the inductor current iL is half of the iL of FBI. Moreover, the proposed inverter uses small inductors with fewer turns than that of the FBI. Thus, FBI had the highest PIND. The diode loss PD was 7.04 W for proposed, 6.45 W for IDBI, and 0 for FBI at Po = 2 kW, and PD was 0.907 W for proposed, 0.885 W for IDBI, and 0 for FBI at Po = 150 W. The power loss PDSP of the gate control/drive circuit was 6.02 W for proposed, 6   The temperature T SW of switch vs. time of operation ( Figure 13) was measured while operating the experimental inverters at V in = 400 V DC , V grid = 220 V AC /60 Hz, P o = 2 kW, and f s = 20 kHz. T SW was stabilized at~52 • C (S U1 , S U2 , S D1 , S D2 ) and~55 • C (S U3 , S D3 ) in the proposed inverter,~54 • C (S U1 , S U2 , S D1 , S D2 ) and~58 • C (S U3 , S D3 ) in the IDBI, and at~110 • C in FBI. P SW at P o = 2 kW were 13.2 W for proposed, 13.89W for IDBI, and 29.71 W for FBI; therefore, T sw of the proposed inverter and IDBI was half that of FBI.
THD of i o vs. P o (Figure 14) was also measured at V in = 400 V DC , V grid = 220 V AC /60 Hz, P o = 150 W 2 kW, and f s = 20 kHz. THD at P o = 2 kW was 0.66% for proposed and IDBI and 3.25% for FBI; FBI had the highest THD because this inverter produced a ZCD during the dead-time period. THD at P o = 150 W was 16.6% for IDBI and the proposed inverter when the switching duties for the inverters were controlled using the CCM control (given in (8)). At a low P o , the proposed inverter operated in DCM for some time-interval of sinusoidal V grid , as discussed in Section 2.2. This operation produced a distortion in I o when the inverters were operated under CCM control only.
When the switching duties for IDBI and the inverters were controlled using the proposed DCM+CCM control (a combination of the CCM control and the DCM control given in Equation (7)), the THD at P o = 150 W was reduced to 4.1% because the combined DCM+CCM control reduced the distortion in I o significantly. W ~ 2 kW, and fs = 20 kHz. THD at Po = 2 kW was 0.66% for proposed and IDBI and 3.25% for FBI; FBI had the highest THD because this inverter produced a ZCD during the dead-time period. THD at Po = 150 W was 16.6% for IDBI and the proposed inverter when the switching duties for the inverters were controlled using the CCM control (given in (8)). At a low Po, the proposed inverter operated in DCM for some time-interval of sinusoidal Vgrid, as discussed in Section 2.2. This operation produced a distortion in Io when the inverters were operated under CCM control only. When the switching duties for IDBI and the inverters were controlled using the proposed DCM+CCM control (a combination of the CCM control and the DCM control given in Equation (7)), the THD at Po = 150 W was reduced to 4.1% because the combined DCM+CCM control reduced the distortion in Io significantly.
When fs was increased to 40 kHz, THD of io at Po = 2 kW was 0.63% for proposed and IDBI and 7.24% for FBI. The FBI nearly doubled the THD at fs = 40 kHz compared to the value at fs = 20 kHz, because the change increased the effect of dead-time on the switching duty. The THD at Po = 150 W W ~ 2 kW, and fs = 20 kHz. THD at Po = 2 kW was 0.66% for proposed and IDBI and 3.25% for FBI; FBI had the highest THD because this inverter produced a ZCD during the dead-time period. THD at Po = 150 W was 16.6% for IDBI and the proposed inverter when the switching duties for the inverters were controlled using the CCM control (given in (8)). At a low Po, the proposed inverter operated in DCM for some time-interval of sinusoidal Vgrid, as discussed in Section 2.2. This operation produced a distortion in Io when the inverters were operated under CCM control only. When the switching duties for IDBI and the inverters were controlled using the proposed DCM+CCM control (a combination of the CCM control and the DCM control given in Equation (7)), the THD at Po = 150 W was reduced to 4.1% because the combined DCM+CCM control reduced the distortion in Io significantly.
When fs was increased to 40 kHz, THD of io at Po = 2 kW was 0.63% for proposed and IDBI and 7.24% for FBI. The FBI nearly doubled the THD at fs = 40 kHz compared to the value at fs = 20 kHz, because the change increased the effect of dead-time on the switching duty. The THD at Po = 150 W When f s was increased to 40 kHz, THD of i o at P o = 2 kW was 0.63% for proposed and IDBI and 7.24% for FBI. The FBI nearly doubled the THD at f s = 40 kHz compared to the value at f s = 20 kHz, because the change increased the effect of dead-time on the switching duty. The THD at P o = 150 W was 7.41% for the proposed inverter using CCM control, 3.98% for the proposed inverter using DCM+CCM control, and 3.51% for FBI. The DCM operating time was reduced at higher f s (Equations (9) and (10)); hence, THD of the proposed inverter decreased as f s increased; a DCM control near the zero crossing point increased i L . In contrast, the THD for FBI increased as f s increased because the impact of dead-time on the switching duty increased.
The waveforms of i o and i o_avg for the experimental inverters ( Figure 15) were measured at V in = 400 V DC , V grid = 220 V AC /60 Hz, f s = 20 kHz, P o = 150 W, Q o = 0 VAR, and I o = 0.95 A. The cutoff frequency of the low-pass filter for i o_avg measurement was 2 kHz (=f s /10). The inverters were controlled using CCM or DCM+CCM control. The waveforms of i o show that the proposed inverter had the lowest switching ripple of i o , and the waveforms of i o_avg show that the DCM+CCM control of the proposed inverter achieved the best sinusoidal waveform. The harmonic components of i o (Figure 16) show that harmonics of i o of FBI were slightly higher than those of the proposed inverter because the proposed inverter operated as an interleaved dual buck inverter. was 7.41% for the proposed inverter using CCM control, 3.98% for the proposed inverter using DCM+CCM control, and 3.51% for FBI. The DCM operating time was reduced at higher fs (Equations (9) and (10)); hence, THD of the proposed inverter decreased as fs increased; a DCM control near the zero crossing point increased iL. In contrast, the THD for FBI increased as fs increased because the impact of dead-time on the switching duty increased.
The waveforms of io and io_avg for the experimental inverters ( Figure 15) were measured at Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, fs = 20 kHz, Po = 150 W, Qo = 0 VAR, and Io = 0.95 A. The cutoff frequency of the low-pass filter for io_avg measurement was 2 kHz (=fs/10). The inverters were controlled using  The dynamic responses of the proposed inverter ( Figure 17) were measured for a step change of P o from 2 kW to 1 kW and a step change of P o from 1 kW to 2 kW; the operating conditions for this measurement were V in = 400 V DC , V grid = 220 V AC /60 Hz, f s = 20 kHz, and Q o = 0 VAR. For both P o changes, the output current i o did not overshoot, and the transient time of i o was < 2 ms, which is~1/8 of the sinusoidal period at 60 Hz. PF, THD, and i o of the proposed inverter were measured for P o = 666.6 W, 1.333 kW, and 2 kW at V in = 400 V DC , V grid = 220 V AC /60 Hz, f s = 20 kHz, and line impedance Z = 0.4 + j0.25 Ω. The measured PF was 0.9973 at P o = 666.6 W (33% of the rated power), 0.9985 at P o = 1.333 kW (66% of the rated power), and 0.9992 at P o = 2 kW (100% of the rated power). The measured THD of i o was 4.20% at P o = 666.6 W, 3.68% at P o = 1.333 kW, and 3.43% at P o = 2 kW. These results fulfill most grid-connected inverter standards for renewable energy [19][20][21][22].
Comparisons (Table 4) of the circuit parameters and experimental results demonstrate the superiority of the proposed inverter. The proposed inverter has the following advantages: (1) proposed inverter requires two inductors, whereas IDBI requires four inductors; hence, the proposed inverter can be implemented with lower cost and smaller volume than IDBI; (2) it uses interleaved operation, which reduces the current stress of the switch by 1/2 of that in FBI; (3) the number of switching for one period of V grid in the proposed inverter is 1/2 of that in FBI; hence, the switching loss is reduced; and (4) η e at P o = 2 kW is as high as 98.3%, compared to 95.0% for FBI. These advantages indicate that the proposed inverter is useful for high-power dc-ac power conversion. harmonics of io of FBI were slightly higher than those of the proposed inverter because the proposed inverter operated as an interleaved dual buck inverter. The dynamic responses of the proposed inverter ( Figure 17) were measured for a step change of Po from 2 kW to 1 kW and a step change of Po from 1 kW to 2 kW; the operating conditions for this measurement were Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, fs = 20 kHz, and Qo = 0 VAR. For both Po changes, the output current io did not overshoot, and the transient time of io was < 2 ms, which is ~1/8 of the sinusoidal period at 60 Hz. PF, THD, and io of the proposed inverter were measured for Po = 666.6 W, 1.333 kW, and 2 kW at Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, fs = 20 kHz, and line impedance Z = 0.4 + j0.25 Ω. The measured PF was 0.9973 at Po = 666.6 W (33% of the rated power), 0.9985 at Po = 1.333 kW (66% of the rated power), and 0.9992 at Po = 2 kW (100% of the rated power). The measured THD of io was 4.20% at Po = 666.6 W, 3.68% at Po = 1.333 kW, and 3.43% at Po = 2 kW. These results fulfill most grid-connected inverter standards for renewable energy [19][20][21][22]. Comparisons (Table 4) of the circuit parameters and experimental results demonstrate the superiority of the proposed inverter. The proposed inverter has the following advantages: 1) proposed inverter requires two inductors, whereas IDBI requires four inductors; hence, the proposed inverter can be implemented with lower cost and smaller volume than IDBI; 2) it uses interleaved operation, which reduces the current stress of the switch by 1/2 of that in FBI; 3) the number of switching for one period of Vgrid in the proposed inverter is 1/2 of that in FBI; hence, the switching loss is reduced; and 4) e  at o P = 2 kW is as high as 98.3%, compared to 95.0% for FBI. These advantages indicate that the proposed inverter is useful for high-power dc-ac power conversion.  The dynamic responses of the proposed inverter ( Figure 17) were measured for a step change of Po from 2 kW to 1 kW and a step change of Po from 1 kW to 2 kW; the operating conditions for this measurement were Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, fs = 20 kHz, and Qo = 0 VAR. For both Po changes, the output current io did not overshoot, and the transient time of io was < 2 ms, which is ~1/8 of the sinusoidal period at 60 Hz. PF, THD, and io of the proposed inverter were measured for Po = 666.6 W, 1.333 kW, and 2 kW at Vin = 400 VDC, Vgrid = 220 VAC/60 Hz, fs = 20 kHz, and line impedance Z = 0.4 + j0.25 Ω. The measured PF was 0.9973 at Po = 666.6 W (33% of the rated power), 0.9985 at Po = 1.333 kW (66% of the rated power), and 0.9992 at Po = 2 kW (100% of the rated power). The measured THD of io was 4.20% at Po = 666.6 W, 3.68% at Po = 1.333 kW, and 3.43% at Po = 2 kW. These results fulfill most grid-connected inverter standards for renewable energy [19][20][21][22]. Comparisons (Table 4) of the circuit parameters and experimental results demonstrate the superiority of the proposed inverter. The proposed inverter has the following advantages: 1) proposed inverter requires two inductors, whereas IDBI requires four inductors; hence, the proposed inverter can be implemented with lower cost and smaller volume than IDBI; 2) it uses interleaved operation, which reduces the current stress of the switch by 1/2 of that in FBI; 3) the number of switching for one period of Vgrid in the proposed inverter is 1/2 of that in FBI; hence, the switching loss is reduced; and 4) e  at o P = 2 kW is as high as 98.3%, compared to 95.0% for FBI. These advantages indicate that the proposed inverter is useful for high-power dc-ac power conversion. Step responses of the proposed inverter at V in = 400 V DC , V grid = 220 VAC/60 Hz, f s = 20 kHz, and Q o = 0 VAR: (a) for a decrease of P o from 2 kW to 1 kW and (b) for an increase of P o from 1 kW to 2 kW. T sw Temperature of switches ( • C).

V AN
Leg voltage with respect to the ground (V).

V AN_avg
Time averaged value of V AN for one switching period (V).

V AN_d
Amplitude of V AN_avg parallel to V grid (V).

V AN_q
Amplitude of V AN_avg orthogonal to V grid (V). V g Amplitude of V grid (V). V grid AC output voltage (AC grid voltage) (V).
Voltages across the output filter inductors L 1 and L 2 (V). V L1_avg , V L2_avg Time averaged values of V L1 and V L2 for one switching period (V).

∆D
Difference of switching duties for CCM and DCM operations. ∆T s Duration of i L1 (t) 0 for one switching period (s). θ Phase angle of V grid (rad). θ Estimated θ by the phased locked loop (rad). η e Power conversion efficiency of inverters. ω Angular frequency of V grid (rad/s). ω set Nominal value of ω (rad/s).