A New Conﬁguration of Three-Level ZSI Using Transistor Clamped Topology

: In this paper, a three-level ZSI (impedance source inverter) based on transistor clamped theory is proposed. It uses the least number of switch counts and associated gate circuitry among all existing topologies of three-level ZSI without any performance degradation. The existing three-level ZSI topologies require three power switches to be turned ON for upper-lower shoot-through (ULST), and four power switches to be turned ON for full dc-link shoot-through (FST). However, with the proposed conﬁguration, upper–lower shoot-through (ULST) and full dc-link shoot-through (FST) is inserted by turning ON only two power semiconductors. A comparison between diode clamped, transistor clamped, and t-type is presented. The proposed topology can realize any of the existing sine-triangle- or space vector-based PWM (pulse width modulation) schemes, and all existing conﬁgurations of three-level ZSI can merge into the proposed inverter conﬁguration.


Introduction
The three most common multilevel configurations-diode clamped, capacitor clamped, and cascaded multilevel-are extensively studied in the literature. Since each of these three have their own merits and demerits, numerous branches of research areas emerged. Some of them found their applications in renewable energy, drives, and hybrid vehicles. Some other implementations are associated with control techniques like neutral point balance, reduced common-mode voltage, and topological developments, such as symmetrical/asymmetrical hybrid topologies and PWM technique developments like hybrid PWM techniques.
The main drawback of these three basic topologies is that only voltage buck operation is possible. So, to insert a voltage buck-boost feature in an existing voltage source inverter, a new class of inverters, namely Z-source inverters, is proposed in [1] with its two-level configurations. The other advantages offered by these (ZSI) inverters are: (i) no need for the time delay between the switches of the same leg, and (ii) better output voltage quality. Extensive research is present in the area of two-level ZSI, with the main focus on its topological improvements, PWM techniques, and its suitability for different applications.
However, the concept of ZSI in the area of multilevel inverters is less explored as compared to two-level ZSI-and VSI based multilevel inverters.
The first attempt to extend the ZSI concept in a three-level neutral point clamped (NPC) inverter was reported in [2], with a detailed explanation of the shoot-through addition procedure in the existing continuous and discontinuous PWM techniques. The presented circuit configuration in [2] requires two impedance networks for boosting output voltage, which increases the inverter complexity, control, and cost.
The configuration of the existing three-level ZSI is shown in Figure 1, where one impedance network is used for voltage boosting [12]. One impedance network indicates two inductors and two capacitors. In the FST scheme, full shoot-through states and non-shoot-through states are present, while in the ULST scheme, upper-lower shoot-through states and non-shoot-through states are present.
When upper and lower ST states use a single impedance network, the relation between M and ST duty ratio ( ℎ ) is written as: Where 0 is the shoot-through duration in a sample period T. The two primary types of shoot-through techniques used for shoot-through insertion are full dc-link shoot-through (FST) and upper-lower shoot-through (ULST). The switching combinations to implement FST and ULST scheme in diode clamped configurations are as follows: A.
Full dc-link shoot-through (FST): Upper shoot-through: Lower shoot-through: Non-shoot-through state: In the FST scheme, full shoot-through states and non-shoot-through states are present, while in the ULST scheme, upper-lower shoot-through states and non-shoot-through states are present.
When upper and lower ST states use a single impedance network, the relation between M and ST duty ratio (d sh ) is written as: where T 0 is the shoot-through duration in a sample period T. With a single impedance network, d sh offered by the ULST scheme is half in comparison to the FST scheme. This is written as: The relation between boost factor B and d sh is: For a particular value of modulation index 'M', the value of boost factor 'B' offered by the ULST scheme is lower than the FST scheme. The value offered by the ULST scheme is lower than the FST scheme of 3L-ZSI using a single impedance network. Figure 2 represents the relation between 'B' and 'M' for ULST and FST schemes. With a single impedance network, dsh offered by the ULST scheme is half in comparison to the FST scheme. This is written as: The relation between boost factor B and ℎ is: For a particular value of modulation index 'M', the value of boost factor 'B' offered by the ULST scheme is lower than the FST scheme. The value offered by the ULST scheme is lower than the FST scheme of 3L-ZSI using a single impedance network. Figure 2 represents the relation between 'B' and 'M' for ULST and FST schemes.

Operating Principal of the Three-Level Transistor Clamped Topology and Its Comparison with Other Existing Topologies
The diode clamped three-level voltage source inverter is shown in Figure 3. The main problems associated with these inverters are unequal device ratings of semiconductor switches, the need for diodes for dc voltage clamping, a high number of component counts at high levels, and neutral point potential unbalance. The above drawbacks limit their applications in real power conversion. Another alternative is presented in Figure 4, named as transistor clamped three-level inverter in this paper.

Operating Principal of the Three-Level Transistor Clamped Topology and Its Comparison with Other Existing Topologies
The diode clamped three-level voltage source inverter is shown in Figure 3. The main problems associated with these inverters are unequal device ratings of semiconductor switches, the need for diodes for dc voltage clamping, a high number of component counts at high levels, and neutral point potential unbalance. The above drawbacks limit their applications in real power conversion. Another alternative is presented in Figure 4, named as transistor clamped three-level inverter in this paper. With a single impedance network, dsh offered by the ULST scheme is half in comparison to the FST scheme. This is written as: The relation between boost factor B and ℎ is: For a particular value of modulation index 'M', the value of boost factor 'B' offered by the ULST scheme is lower than the FST scheme. The value offered by the ULST scheme is lower than the FST scheme of 3L-ZSI using a single impedance network. Figure 2 represents the relation between 'B' and 'M' for ULST and FST schemes.

Operating Principal of the Three-Level Transistor Clamped Topology and Its Comparison with Other Existing Topologies
The diode clamped three-level voltage source inverter is shown in Figure 3. The main problems associated with these inverters are unequal device ratings of semiconductor switches, the need for diodes for dc voltage clamping, a high number of component counts at high levels, and neutral point potential unbalance. The above drawbacks limit their applications in real power conversion. Another alternative is presented in Figure 4, named as transistor clamped three-level inverter in this paper.   This three-level topology has the two main power switches and one auxiliary switch in each leg. The auxiliary switch (a combination of one IGBT and four diodes to accomplish bidirectional power flow) clamps each phase leg voltage to the zero or neutral potential. Table 1 indicates the switch combination for each level of the output pole voltage. From Table 1, it can be seen that at each instant, only one switch from each leg is ON, and the other two (auxiliary and power switches) are off, to generate a three-level output voltage waveform.  Single-phase five-level configurations can be realized using only six power switches via appropriately modulating the two legs.
However, neutral point voltage unbalance and common-mode voltage elimination/reduction still require attention, and these issues are not discussed here.

Comparison of the Transistor Clamped, Diode Clamped and T-Type Inverter
The two other main three-level inverter configurations are diode clamped and T-type inverter. One phase leg of the diode clamped and T-type VSI is shown in Figure 5. The working principle of the diode clamped and T-type voltage source inverter can be understood from Table 2. This three-level topology has the two main power switches and one auxiliary switch in each leg. The auxiliary switch (a combination of one IGBT and four diodes to accomplish bidirectional power flow) clamps each phase leg voltage to the zero or neutral potential. Table 1 indicates the switch combination for each level of the output pole voltage. From Table 1, it can be seen that at each instant, only one switch from each leg is ON, and the other two (auxiliary and power switches) are off, to generate a three-level output voltage waveform.
Main features of this topology are listed below: • Total power switch count reduces to nine, as compared to twelve in the diode clamped, capacitor clamped, and cascaded for the same three-phase output voltage level.

•
No unequal device rating problem, as in the diode clamped configuration. No need for clamping diodes/capacitors. • Any conventional PWM techniques (sine-triangle/SVPWM) can be used with suitable modifications. • Single-phase five-level configurations can be realized using only six power switches via appropriately modulating the two legs.
However, neutral point voltage unbalance and common-mode voltage elimination/reduction still require attention, and these issues are not discussed here.

Comparison of the Transistor Clamped, Diode Clamped and T-Type Inverter
The two other main three-level inverter configurations are diode clamped and T-type inverter. One phase leg of the diode clamped and T-type VSI is shown in Figure 5. The working principle of the diode clamped and T-type voltage source inverter can be understood from Table 2. There are four power switches in each phase leg of the diode clamped and T-type VSI. Therefore, four gating pulses are required. Depending upon the direction of load current, various combinations of the ON switch and the ON diodes have been listed in Table 2. The comparison of the average switching frequency of each switch of the transistor clamped, diode clamped, and T-type VSI is presented in Table 3.  From Table 3, it is clear that the switching frequency of the bidirectional switch (SX2) of the transistor clamped VSI is twice that of the upper and lower switch of the same phase leg, and each switch of the diode clamped and T-type VSI. Considering the case of low voltage application (<= 1200V), the transistor clamped configuration offers the following advantages:  It provides reduced conduction and switching losses, as compared to the diode clamped VSI, since only one switch per phase leg is conducting at any instant in the transistor clamped VSI. On the other hand, in the diode clamped VSI, two switches per phase leg are in conduction during power flow to load (Table 2).  It reduces one IGBT per phase leg and its associated gate driver ICs/circuit elements, as compared to the diode clamped and T-type VSI.  There are four power switches in each phase leg of the diode clamped and T-type VSI. Therefore, four gating pulses are required. Depending upon the direction of load current, various combinations of the ON switch and the ON diodes have been listed in Table 2. The comparison of the average switching frequency of each switch of the transistor clamped, diode clamped, and T-type VSI is presented in Table 3.   Table 3, it is clear that the switching frequency of the bidirectional switch (SX2) of the transistor clamped VSI is twice that of the upper and lower switch of the same phase leg, and each switch of the diode clamped and T-type VSI. Considering the case of low voltage application (<= 1200 V), the transistor clamped configuration offers the following advantages: • It provides reduced conduction and switching losses, as compared to the diode clamped VSI, since only one switch per phase leg is conducting at any instant in the transistor clamped VSI. On the other hand, in the diode clamped VSI, two switches per phase leg are in conduction during power flow to load (Table 2).

•
It reduces one IGBT per phase leg and its associated gate driver ICs/circuit elements, as compared to the diode clamped and T-type VSI.
• Only one gating pulse is being generated and fed to the particular IGBT at a time to turn it ON in the transistor clamped VSI (Table 1). But there are always two gating pulses being generated in the diode clamped and T-type VSI (Table 2).
However, the following points can be considered as the drawbacks of the transistor clamped inverter configuration: During the inverter operation in state '0' shown in Table 1, there are two diodes and one IGBT in the conduction path of the transistor clamped VSI. On the other hand, the diode clamped and T-type VSI have one diode and one IGBT in the conduction during state 'O', which can be seen from Table 2. Therefore, the power loss due to one extra diode in state 'O' can be seen as the drawback of the transistor clamped VSI.
The schematic of the gating pulse for the three power switches in the TC-VSI and the conventional VSI is shown in Figure 6. The gating signal of SA2 and SA3 of the existing three-level VSI are logically transformed into one signal for switch SA0 of TC-VSI.
Energies 2020, 11, x FOR PEER REVIEW 7 of 16  Only one gating pulse is being generated and fed to the particular IGBT at a time to turn it ON in the transistor clamped VSI (Table 1). But there are always two gating pulses being generated in the diode clamped and T-type VSI (Table 2).
However, the following points can be considered as the drawbacks of the transistor clamped inverter configuration: During the inverter operation in state '0′ shown in Table 1, there are two diodes and one IGBT in the conduction path of the transistor clamped VSI. On the other hand, the diode clamped and Ttype VSI have one diode and one IGBT in the conduction during state 'O', which can be seen from Table 2. Therefore, the power loss due to one extra diode in state 'O' can be seen as the drawback of the transistor clamped VSI.
The schematic of the gating pulse for the three power switches in the TC-VSI and the conventional VSI is shown in Figure 6. The gating signal of SA2 and SA3 of the existing three-level VSI are logically transformed into one signal for switch SA0 of TC-VSI.

Proposed Configurations of Transistor Clamped Three-Level ZSI
The concept of ZSI is implemented in the above-discussed transistor clamped VSI. Different types of three-level ZSI configuration already presented in the literature [2][3][4][10][11][12] can extend to the transistor clamped configuration.
The attractive feature of the TC-ZSI is that it requires only two switches to be turned ON for shoot-through state insertion, whether it is upper, lower, or full dc-link shoot-through. Figures 7 and 8 show the schematics of the three-level TC-ZSI using two impedance networks and one impedance network, respectively. Here, one impedance network indicates two inductors and two capacitors.

Proposed Configurations of Transistor Clamped Three-Level ZSI
The concept of ZSI is implemented in the above-discussed transistor clamped VSI. Different types of three-level ZSI configuration already presented in the literature [2][3][4][10][11][12] can extend to the transistor clamped configuration.
The attractive feature of the TC-ZSI is that it requires only two switches to be turned ON for shoot-through state insertion, whether it is upper, lower, or full dc-link shoot-through. Figures 7 and 8 show the schematics of the three-level TC-ZSI using two impedance networks and one impedance network, respectively. Here, one impedance network indicates two inductors and two capacitors.
From Figure 8, it is clear that {'SX1', 'SX0'} is turned ON for the upper shoot-through, as shown in Figure 9a. {'SX2', 'SX0'} is turned ON for the lower shoot-through shown in Figure 9b, and {'SX1', 'SX2'} is turned ON for the full dc-link shoot-through presented in Figure 9c. However, the diode clamped NPC type ZSI requires three semiconductor switches and one diode for upper-lower shoot-through [2] and four switches for full dc-link shoot-through [3].   Figure 9c. However, the diode clamped NPC type ZSI requires three semiconductor switches and one diode for upper-lower shootthrough [2] and four switches for full dc-link shoot-through [3].   Figure 9c. However, the diode clamped NPC type ZSI requires three semiconductor switches and one diode for upper-lower shootthrough [2] and four switches for full dc-link shoot-through [3]. This paper considers the ULST scheme for the three-level transistor clamped ZSI proposed in Figure 7. The ULST scheme offers better output waveform quality because of the nearest three vector (NTV) switching. NTV switching is not possible using the FST scheme.
The expression for the capacitor voltage, input dc-link peak voltagev i and output peak phase voltagev x of inverter for both schemes can be written as [12]: Assuming L 1 = L 2 = L, C 1 = C 2 = C and Vdc_1 = Vdc_2 = V dc FST scheme: ULST scheme:  (5) where "T o /T" is the sum of upper and lower shoot-through. This paper considers the ULST scheme for the three-level transistor clamped ZSI proposed in Figure 7. The ULST scheme offers better output waveform quality because of the nearest three vector (NTV) switching. NTV switching is not possible using the FST scheme.
The expression for the capacitor voltage, input dc-link peak voltage ̂ and output peak phase voltage ̂ of inverter for both schemes can be written as [12]: Assuming L 1 = L 2 = L, C 1 = C 2 = C and Vdc_1 = Vdc_2 =V dc FST scheme: ULST scheme:

PWM Techniques
The most commonly used sine triangle-based PWM techniques for multilevel inverters are:
The above-mentioned techniques have been used in the literature for the insertion of shoot-through in the three-level ZSI. As per the shoot-through insertion process, these techniques are further classified into continuous edge insertion PWM and modified reference PWM, which differs only in the number of switching transitions. With the addition of an appropriate offset signal in the sinusoidal reference signal, the advantages offered by the central space vector PWM can be realized. The offset signal for three-level ZSI based SVPWM and other discontinuous PWM schemes is reported in [14].
The primary considerations required for insertion of shoot-through in the PWM control technique of three-level NPC-type ZSI or TC-ZSI are summarized below: • Minimum device commutation per half switching cycle.

•
Equal shoot-through time for both impedance network, if two impedance networks are used.
• Shoot-through should always be inserted in the state transition, i.e., null to active, active to active, and active to null with a single switch transition.
Continuous edge insertion using POD/APOD carrier with added offset to increase the modulation index range (<= 1.15) has been used in this paper, as shown in Figure 10. Continuous edge insertion offers a balanced and symmetrical voltage boost per switching cycle, thereby reducing the current ripple.
reported in [14]. The primary considerations required for insertion of shoot-through in the PWM control technique of three-level NPC-type ZSI or TC-ZSI are summarized below:  Minimum device commutation per half switching cycle.  Equal shoot-through time for both impedance network, if two impedance networks are used.  Shoot-through should always be inserted in the state transition, i.e., null to active, active to active, and active to null with a single switch transition.
Continuous edge insertion using POD/APOD carrier with added offset to increase the modulation index range (<= 1.15) has been used in this paper, as shown in Figure 10. Continuous edge insertion offers a balanced and symmetrical voltage boost per switching cycle, thereby reducing the current ripple.

Conduction and Switching Losses
The conduction and switching losses are the two main contributors to total power losses in the inverter. For a pulsed output voltage and current, the average conduction losses per sub-cycle in IGBT and diode can be calculated as: The switching losses are further classified into turn-on and turn-off energy losses. The total switching losses in the case of IGBT is defined as: Only turn-off losses (reverse recovery losses) have been considered in the case of diodes. These are written as: The parameters mentioned in the above equations have been taken from the datasheets to find the efficiency and switching losses of the converter.

Impedance Network Design
The impedance network inductor and capacitor are designed based on the high-frequency ripple components of the inductor current and capacitor voltage, respectively. The high-frequency component of the inductor ripple current is written as: where V C is the average voltage across the capacitors of impedance network. It is written as: The permissible value of inductor current ripple is defined as: where r L is the permissible percentage of the average inductor current ripple. I L is the average inductor current and is expressed as: where 'P' denotes the total output power of the inverter. Substituting (1), (10), and (11) into (9), the expression for 'L' is written as: Similarly, the high-frequency ripple component of the capacitor voltage is written as: The permissible value of capacitor voltage ripple is defined as: where r C is the permissible ripple percentage in the average capacitor voltage. Using (1), (9), (14), and (15), the expression for 'C' can be written as:

Simulation Results
The proposed topologies are simulated in a MATLAB/SIMULINK environment. A prototype is developed in the laboratory, and the results are presented. The input voltage for the simulation is set to 200 V (100 of each source), RL load (R = 10 ohm and L = 10 mH), and the switching frequency is set to 5.5 kHz. The impedance network inductor and capacitor values are calculated using Equations (13) and (14) as 2 mH and 330 uF. The output waveforms of transistor clamped three-level VSI are shown in Figure 11. It can be seen from Figure 11 that the PD carrier PWM follows the nearest three vectors for synthetization of the output voltage. Figure 12 shows the waveform of the proposed three-level ZSI, based on transistor clamped topology. The configuration shown in Figure 7 is used with the in-phase disposition carrier PWM technique (PD) with modulation index M = 1*1.15 and To/T = 0 (without shoot-through). Then, the upper and lower shoot-through states are inserted, and waveforms are shown in Figure 13 with M = 0.7*1.15 and To/T = 0.3. With upper and lower shoot-through added, the expressions for the gain of the inverter are given in Equation (5) [12]. Where T o/T; represents the sum of upper and lower shoot-through whose sum is equal to the 2To/T. By putting the values of M (=1.15*0.7) and To /T (=0.3) in the above equation, the output ac phase leg voltage of the inverter comes out to be 250 V, and peak line voltage is 500 V, which is clearly shown in Figure 13. Volt-sec error and minimum device commutation are kept in mind while adding shoot-through states. The same shoot-through time is used for both upper and lower shoot-through, in order to avoid unbalance in output voltage. Figure 14 shows the TC-ZSI configuration with a single impedance network, as shown in Figure 8. Similar results can be found with the same value of M and B as the above case. APOD PWM technique is used for this configuration to add full dc-link shoot-through, as APOD uses {0 0 0} state, even at a high modulation index. This technique does not follow the nearest three vectors to synthesize the output voltage waveform, which can be seen in the first waveform of Figure 14. The output power quality is poor, and contains higher harmonic distortion, as compared to the phase carrier PWM, if the APOD PWM technique is used; however, it saves one impedance network.
three-level ZSI, based on transistor clamped topology. The configuration shown in Figure 7 is used with the in-phase disposition carrier PWM technique (PD) with modulation index M=1*1.15 and To/T=0 (without shoot-through). Then, the upper and lower shoot-through states are inserted, and waveforms are shown in Figure 13 with M=0.7*1.15 and To/T=0.3. With upper and lower shootthrough added, the expressions for the gain of the inverter are given in Equation (5) [12]. Where ′ / represents the sum of upper and lower shoot-through whose sum is equal to the 2 / . By putting the values of M (=1.15*.7) and To`/T (=0.3) in the above equation, the output ac phase leg voltage of the inverter comes out to be 250 V, and peak line voltage is 500 V, which is clearly shown in Figure  13. Volt-sec error and minimum device commutation are kept in mind while adding shoot-through states. The same shoot-through time is used for both upper and lower shoot-through, in order to avoid unbalance in output voltage. Figure 14 shows the TC-ZSI configuration with a single impedance network, as shown in Figure  8. Similar results can be found with the same value of M and B as the above case. APOD PWM technique is used for this configuration to add full dc-link shoot-through, as APOD uses {0 0 0} state, even at a high modulation index. This technique does not follow the nearest three vectors to synthesize the output voltage waveform, which can be seen in the first waveform of Figure 14. The output power quality is poor, and contains higher harmonic distortion, as compared to the phase carrier PWM, if the APOD PWM technique is used; however, it saves one impedance network. Figure 11. Simulated output waveforms of the transistor clamped VSI, as shown in Figure 1, at a carrier frequency of 5.5 kHz, with a modulation index of 0.9.     Figure 15 shows a photograph of the prototype developed in the lab. Figure 16 shows the experimental waveforms of line voltage and pole voltage. Texas Instruments-based DSP TMS320F28335 was used for the generation of switching pulses. Figure 17 shows the waveform of the generated switching pulses. The experimental waveforms have a good agreement with the simulated waveforms. The explanation of the experimental results is same as that of the simulation results.  Figure 15 shows a photograph of the prototype developed in the lab. Figure 16 shows the experimental waveforms of line voltage and pole voltage. Texas Instruments-based DSP TMS320F28335 was used for the generation of switching pulses. Figure 17 shows the waveform of the generated switching pulses. The experimental waveforms have a good agreement with the simulated waveforms. The explanation of the experimental results is same as that of the simulation results. Figure 15 shows a photograph of the prototype developed in the lab. Figure 16 shows the experimental waveforms of line voltage and pole voltage. Texas Instruments-based DSP TMS320F28335 was used for the generation of switching pulses. Figure 17 shows the waveform of the generated switching pulses. The experimental waveforms have a good agreement with the simulated waveforms. The explanation of the experimental results is same as that of the simulation results.

Conclusions
This paper presented a new configuration of three-level ZSI derived from a neutral point clamped and conventional ZSI, which uses less component counts and associated gate circuitry as compared to the existing topologies. The proposed converter offers a low-cost alternative to applications that need to ride through frequent input voltage sags. A comparison between diode clamped, transistor clamped, and t-type is presented. It has been revealed that upper-lower shootthrough and full dc-link shoot-through can be easily incorporated by turning ON two power semiconductor switches. The proposed inverter topology can be modulated by any of the existing PWM techniques, and all current three-level ZSI configurations can be merged into this configuration by changing only the inverter switches. It is verified that the ULST scheme PD method offers better

Conclusions
This paper presented a new configuration of three-level ZSI derived from a neutral point clamped and conventional ZSI, which uses less component counts and associated gate circuitry as compared to the existing topologies. The proposed converter offers a low-cost alternative to applications that need to ride through frequent input voltage sags. A comparison between diode clamped, transistor clamped, and t-type is presented. It has been revealed that upper-lower shootthrough and full dc-link shoot-through can be easily incorporated by turning ON two power semiconductor switches. The proposed inverter topology can be modulated by any of the existing PWM techniques, and all current three-level ZSI configurations can be merged into this configuration by changing only the inverter switches. It is verified that the ULST scheme PD method offers better output voltage waveform, as it follows the nearest three vector approach, which is not possible in the FST scheme with the APOD carrier waveform.

Conclusions
This paper presented a new configuration of three-level ZSI derived from a neutral point clamped and conventional ZSI, which uses less component counts and associated gate circuitry as compared to the existing topologies. The proposed converter offers a low-cost alternative to applications that need to ride through frequent input voltage sags. A comparison between diode clamped, transistor clamped, and t-type is presented. It has been revealed that upper-lower shoot-through and full dc-link shoot-through can be easily incorporated by turning ON two power semiconductor switches.
The proposed inverter topology can be modulated by any of the existing PWM techniques, and all current three-level ZSI configurations can be merged into this configuration by changing only the inverter switches. It is verified that the ULST scheme PD method offers better output voltage waveform, as it follows the nearest three vector approach, which is not possible in the FST scheme with the APOD carrier waveform.