A Modified High Voltage Gain Quasi-Impedance Source Coupled Inductor Multilevel Inverter for Photovoltaic Application

The quasi-impedance source inverters/quasi-Z source inverters (Q-ZSIs) have shown improvement to overwhelmed shortcomings of regular voltage-source inverters (VSIs) and currentsource inverters (CSIs) in terms of efficiency and buck-boost type operations. The Q-ZSIs encapsulated several significant merits against conventional ZSIs, i.e., realized buck/boost, inversion and power conditioning in a single power stage with improved reliability. The conventional inverters have two major problems; voltage harmonics and boosting capability, which make it impossible to prefer for renewable generation and general-purpose applications such as drive acceleration. This work has proposed a Q-ZSI with five-level six switches coupled inverter. The proposed Q-ZSI has the merits of operation, reduced passive components, higher voltage boosting capability and high efficiency. The modified space vector pulse width modulation (PWM) developed to achieve the desired control on the impedance network and inverter switching states. The proposed PWM integrates the boosting and regular inverter switching state within one sampling period. The PWM has merits such as reduction of coupled inductor size, total harmonic reduction with enhancing of the fundamental voltage profile. In comparison with other multilevel inverters (MLI), it utilizes only half of the power switch and a lower modulation index to attain higher voltage gain. The proposed inverter dealt with photovoltaic (PV) system for the stand-alone load. The proposed boost inverter topology, operating performance and control algorithm is theoretically investigated and validated through MATLAB/Simulink software and experimental upshots. The proposed topology is an attractive solution for the stand-alone and grid-connected system.

operation, enhanced reliability, reduced component ratings, as well as single-stage regeneration capability. This topology provides consistency with the input current control and performs better than Q-ZSI.
In the current era, the interests of multilevel inverters (MLIs) have increased than the conventional VSIs, due to their merits [22]. Particularly the development of power semiconductor technology makes it easy to tradeoff the selection of power devices. New MLIs have been recommended in a hybrid approach by involving MOSFETs, IGCTs or GTOs and IGBTs [23][24][25][26][27]. Recently, the interleaved converter topology using coupled-inductors is proposed and extensively applied in low-power claims. These topologies are mostly used to increase the output current with lesser current ripple.
Additionally, the interleaved converter reduces the size of passive components (inductors and capacitors), and the output voltage harmonic profile is considerably increased [28][29][30][31][32][33][34][35][36][37][38][39]. Banaei et al. discussed the switching stress reduction in Z source-based MLI [36]. Alexandre Battiston et al. deliberated the withdrawal of the ripples in the input current with the suitable coupled inductors arrangement [37]. Li et al. proposed the use of the cascading magnetic cells to obtain a high voltage gain [38] and investigated the voltage gain achievement against smaller duty time. Followed by the authors, Lei et al. offered optimized pulse width modulation (PWM) technique with reduction of switching loss, current ripple, low total harmonic distortion (THD) and high boost gain [39]. The space vector PWM is extensively reviewed for impendence sourced VSIs and MLIs [40][41][42][43][44][45][46][47][48][49]. The creation of shoot-through (ST) and placing them in the active switching states, these PWM methods perform better than other carrier-based PWM methods. The ZSI space vector PWM is also studied with two-level MLIs for altering the active and ST switching vector in the space vector diagram for the enhancement of inverter output [44]. However, when connecting a coupled inverter with an impedance network, the PWM methods need to be modified.
Based on this technical background and coupled MLI and control scheme requirements of ZSI, this paper suggests a single-phase MLI coupled inverter topology with five-level output for PV application. This PV tied five-level coupled inverter topology is connecting the modified Q-ZSI with a six-switch coupled inverter, making a single stage DC to AC conversion topology. The proposed Q-ZSI has the merits of operation, namely reduced passive components, voltage boosting capability and high efficiency. The modified space vector PWM is proposed to realize the desired control in impedance network shoot-through and regular inverter switching state to make five-level output. The proposed PWM is integrating the boosting and regular inverter switching state within one sampling period. The PWM has the merits like a reduction of coupled inductor size and triplen harmonic reduction with the enhancement of the fundamental voltage profile.
In comparison with other MLIs, it utilizes only half of the power switch, lower modulation index to obtain high voltage gain. The proposed inverter is simulated and experimentally validated for single phase induction motor load with off-grid fashion. Nevertheless, the proposed inverter topology is a suitable version for both off-grid and on-grid applications.
The paper flow is organized in this way. Section 2 deals with the review of traditional Z-source inverter. The proposed modified Q-impedance converter fed coupled inductor multilevel inverter is explained in Section 3. The modified Space Vector PWM concept and control methods of the proposed inverter are shown in Sections 4-6 explain the simulation and experimentation, respectively. The conclusion is given in Section 7. Figure 1 illustrates the general impedance-source configuration with the impedance-source network for VSI. The basic Z-source network structure is generalized as a necessary X shaped twoport network using two L and C (linear energy storage elements) (Peng et al. 2003). Perhaps designing different Z-source network configurations to expand the converter performance, non-linear elements (switches, diodes, or/and combination of both) is added in the shape two-port network (Peng et al. 2003). According to Figure 2, the impedance-source network has two modes of work. During the mode-1, inverter switch is short-circuited to provide the charging loop for an inductor with input DC source. This state is called the 'shoot-through (ST) state'. The second mode is the active mode, where energy stored in the inductors is supplied the load via inverter active mode switching. To connect this ST state with regular inverter active switch, there are a variety of modulation methods available. The modulation methods are distributing the ST states equally based on the modulation index of the inverter (Ma). The upper limit of the modulation index is 1-DS. For the maximum boost modulation method, the modulation index is operated in extensive range (Ma ≥ 1); however, the state involves larger (high rating), passive (L and C) elements [8], and correspondingly distributing the active states, the Ma has its maximum Ma ≤ 1-DS [14]. Therefore, VC1 = VC2 = VPL. During this time, high-frequency generation in the active states causes higher frequency ripples, as shown in Figure 2a. According to the characteristics of Z-source inverter boost mode operation, the performance of inductor and capacitor components and DC-link voltage estimation related to input voltage function are shown in Figure 2b. From the characteristics curve, it is understood that the inverter matches the maximum DC-link voltage with the least input voltage. The inductor curve has a challenging dependency with ST time, and the quick capacitance value raise with the decreasing input voltage is essential. Hence, it is noted that passive elements (inductor and capacitor) are carefully chosen based on the input source voltage and power profile. The voltage rating capacitors are required since the voltage across the capacitors is always greater than the input voltage. Similarly, starting current and voltage surge happens because of the enormous inrush input current. Due to the resonance conditions, these surges are not avoidable, and the absence of bidirectional and soft-start capability limits the application for conventional Z-source topology. To get improvement in the conventional ZSIs, Q-ZSIs are significantly improved to make use of single-stage power conversions. Considering the circuit operations and boosting, characterizes Q-ZSIs as having similar belongings with conventional ZSIs. Figure 3 illustrates the boost-mode characteristics of ZSIs. The Q-ZSIs differ from the conventional X shape-ZSIs by providing continuous input current through lower capacitor C2 [10]. Regardless of the control strategy of Q-ZSIs, during ST states, the duty ratio is limited concerning inductor rating directly. Hence, there is a possibility of continuous conduction with reduced input inductor current ripples. Besides, Q-ZSI provides the cross conduction switching states to provide the boosting by mutual sharing of inverter switching (top and bottom), which improves the inverter reliability [11]. The Q-ZSI has advantages of reduced component (L and C) ratings, lower switching stress, and continuous current mode operation. The standard ground-sharing option in the Q-ZSI is an additional feature, which is high indeed for PV modules [19]. Even though Q-ZSI has several advantages over conventional X-shape ZSI; it has low DC-link utilization in constant boost operation. To overcome this weakness, Q-ZSIs modified with additional passive components have been proposed [19,20].

Different Advanced Z-Source Topologies
Due to the advantages and challenges, power electronics researchers have given much interest in impedance-source topology development. These topologies are categorized into two ways; 1. Transformer based and 2. Without transformer (non-magnetically coupled).  Selected limitations are present in non-magnetically coupled topologies such as low modulation ratio and lesser input-to-output gain. Therefore, this topology needs higher DC-link voltage, which may increase the semiconductors stress needlessly. Besides, the circuit cost and size for these converters are undesirable. Even though the magnetically coupled converters are attractive for their boosting performance, due to the higher DC ripple, the inverter suffers from high harmonics. The disadvantages of magnetically coupled topologies are; (1) raising the shoot-through and magnetizing current while switching; (2) the tightly coupled transformer leads to low leakage impedance; and (3) the need for the snubber circuit is mandatory when the coupling is not fulfilled. Hence, non-magnetic type converters are not highly preferred for PV fed applications [6]. Considering the non-magnetic type converters group, X-shape and Q-impedance converters offer low passive components rating, less duty cycle conversion ratio, and direct conversion. However, it has the poor performance to maintain the input current, reverse blocking capability for the switch, buck-boost operation, absence of bidirectional conversion and direct current control ability. Hence, the paper proposes a coupled inverter connected modified Q-impedance converter to provide single conversion mode power flow operation with multi-level output.

Proposed Modified Q-Impedance Converter Fed Coupled Inductor Multilevel Inverter.
The traditional Z source inverters can only allow unidirectional power conversion flow with boosting operation. Nevertheless, the proposed topology is different from the conventional Z source inverter or Q-ZSI family to exchange the diode for bi-directional power flow; the proposed Q-ZSI achieve the boosting capability with single-stage conversion associated with the inverter switching scheme as shown in Figure 5. The first suggestion of a proposed modified Q-impedance network is to obtain the continuous input current is controlled possibility. It consists of the three operating states; (1) active state, (2) shoot-through state, and (3) open-zero states. When related to the conventional X-Z/Q-Z topology, the proposed structure streams the minimum DC voltage on capacitor C2 as well as deliver continuous input current [11,19]. Acknowledging straightforwardness in the control strategy for the proposed quasi-Z-source MLI functions with two operating modes; (1) shoot-through (ST) and, (2) non-shoot-through (NST). In ST mode, among all inverter phase leg, only one leg is conducting for providing ST. In NST mode, all the three leg switches in the inverter are forming the switching states to make a level in MLI. Hence, the inverter is working similar to a standard inverter. The current Z-source inverter switching states are premeditated with two zero states, and six active states. Figure 6 shows the Proposed modified Q-impedance network. The proposed inverter possesses the two open-zero, six active, and one shoot-through states. State-1: Figure 7a shows the active states of the inverter. This mode assumes inductors, L1 and L2 and capacitors, C1 and C2 with chosen identical values as VC1 = VC2 = VC, VL1 = VL2 = VL to maintain a symmetrical output nature. The Kirchhoff's voltage law is applied in Figure 7a, Considering the steady-state average voltage of the inductors in one switching event must be zero.
, the steady-state voltage average of inductors is zero at one single switching period. Hence, State-2: In this shoot-through state, when any inverter leg is shorted, the PV array voltage is zero, and the diode is off. Thus, the inverter output voltage is zero due to short circuit as shown in Figure  7b, from the equivalent circuit of Figure 7b the KCL equation is given below, State-3: This is considered to be an open-zero state, where the inverter is switching legs act as an open circuit, and therefore the added capacitor voltages (VC1 and VC2) appear across the Vab. Now, the inductor (L1 and L2) currents flow through diode D1 to charge the capacitors (C1 and C2) as exposed in Figure 7c.
From the circuit operation of the proposed inverter, the total switching period is classified as TA Since, The converter DC output voltage boosting (Vboost) has two control degrees of choice (TA and Tsh). In Mode-2, the converter is in shoot-through states, where Top = 1 − TA. Hence the converter provides minimum voltage gain with a specified duty ratio of TA. When converter operation moves from shoot-through states to the open-zero states, the output gain would be situated in the middle of the Mode-1 and Mode-2. The marked red area in Figure 8a shows the mode shift of the converter. Therefore, the converter voltage output can be adjusted to the desired values with two control degrees of freedom Top and TA. Figure 8b shows the radar graph of energy storage capability on C, L, diode voltage stress and switch voltage stress in boost mode for conventional QZ and proposed QZ. It shows the proposed QZ have better energy storage capability and lesser diode and switching voltage stress than conventional QZ.

Modes of Operation of Coupled Inductor MLI
The proposed coupled inductor MLI contains a structure having six switches in three legs (u, v and w). The leg v and leg w are connected with identical turns coupled inductor (LM1 and LM2). The ST operation is done through any leg. If the leg u is used for ST, then the switch S1 and S2 are turned ON simultaneously. Since the ST is allowed in any of the MLI legs, the switching reliability is significantly improved. During the Non-ST (active state), the MLI is functioning with either one upper switch and two-lower switches/two-upper switches, and one-lower switch. Hence, during the active state, the inverter is operating with eight modes of operation to produce five-level voltages (−Vdc,−Vdc/2, 0, Vdc/2, and Vdc).
During the regular inverter operating conditions, the boosted voltage is appearing across the inverter and provides pure DC current. For the period of the ST time, the inductor is maintaining its voltage precisely equal to capacitor voltage VC and hence current increases through the inductors leniently and limits the inductor current ripples. The eight modes of operation and their corresponding equivalent circuits of the proposed coupled inductor connected MLI is illustrated in Figure 9. It is a single-phase circuit with two legs associated with coupled circuits. The quasi fed MLI provides Vpv + VS as input voltage to the coupled inductors (LM1 and LM2). The mutual inductance (M) of the coupled inductors provides the five-level voltage output with a reduction of the switching devices. The level making of the inverter is done through the LM1 and LM2 with the identical sum. The inductor LM1 = LM2 = L is connected between leg v and w. The voltage equation can be expressed as, Where, Vin = input voltage, Vbn = load voltage, and Vwn = w leg voltage Applying current law of Kirchhoff's', the leg current can be written as, Hence, The inverter leakage inductance LM1 and LM2 are designed approximately equal to the mutual inductance value; hence leakage inductance equals mutual inductance (L = M). Therefore, the voltage equation on Vbn can be written as, The voltage output of the inverter can be delivered as, The different modes of operation of active inverter switching for level making are explained as follows; Mode-1: During Mode-1, the inverter switches S1, S4, and S6 are turned ON, and S2, S3, and S5 are turned OFF (see Figure 10) Mode-2: During Mode-2, the inverter switches S1, S4, and S5 are turned ON, and S2, S3, and S6 are turned OFF (see Figure 11). Hence, the inverter produces half of the Vdc (Vs = inverter input voltage).   Figure 11. During Mode-2, the inverter switches S1, S4, and S5 are turned ON.
Mode-3: During the Mode-3, the inverter switches S1, S3, and S6 are turned ON, and S2, S4, and S5 are turned OFF (see Figure 12). Hence, the inverter produces half of the Vdc. From Equation 12 the load voltage is derived as, = − = .   Mode-6: During Mode-6, the inverter switches S2, S4, and S5 are turned ON, and S1, S3, and S6 are turned OFF (see Figure 15). Hence, the inverter produces half of the Vdc.  Mode-7: During Mode-7, the inverter switches S2, S3, and S6 are turned ON, and S1, S4, and S5 are turned OFF (see Figure 16). Hence, the inverter produces half of the Vdc.    Table 1 shows the consolidation of the eight modes of operations of the inverter. Of these eight modes, six modes are producing the voltage in different forms between +Vdc to −Vdc. The Mode-4 and Mode-5 are producing the zero voltages, and hence, any one of the modes can be used for zero voltage. Figure 18 illustrates the all mode operation output voltage structure for proposed MLI.

Modified Space Vector PWM
The Space Vector PWM is a continuous switching PWM technique, which explicitly selects the active and zero states placed within the carrier period [30]. While designing for the boost converter circuitry, the vector-based algorithm possesses the additional switching states which must be imposed to acquire a higher voltage gain in the traditional impedance source inverters. It may lead to impact the switches in the form of stress or failure of a switch [8]. While looking into the traditional strategy, the upper and lower switch combination must be short as the voltage gain may impose distortion on voltage. The proposed space vectors consist of normalized state operation, which generates the voltage gain by operating u, v, w legs upper or lower switches, as shown in Figure 10. The condition ST is incorporated with the regular zero vector operation. The projected control algorithm realizes the least number of switching operations to improve the efficiency of an inverter over one switching cycle, as indicated in Figure 18 In a three-phase balanced system, the voltage equation of Space Vector PWM is predefined as, Here, Vref is a reference vector (target vector), From Figure 19b in the sector-1, vector Vref can be synthesized as, The V1 and V2 are the adjustment operating vectors at T1 and T2. The Ts is a switching period, and T0 is zero vector time. The pulse period of the active vector is calculated from the below equation when operating in a given switching period Ts.
Hence, the zero-vector time: The proposed Space Vector PWM strategy is selecting the voltage vector switching sequence, according to Vref. The Vref is the reference vector of output Vab. Hence, the output voltage of the inverter is selected by using switch S1. According to Table 1, when S1 is turned ON, the inverter output voltage Vab is either in positive voltage or zero. Hence the relation is framed between S1 and Vab, for the smooth implementation.
When S1 is turned ON, the Vab > 0 and S1 is low, consequently Vab < 0. Nevertheless, the other switching states should be appropriately combined with S1 to make the desired voltage level of the inverter. In order to select the stable switching states, the dwell time (Td) of the switch is calculated in every switching frequency Ts sampling period. The dwell time concerning inverter DC-link voltage Vin is defined as: Here, the Vref is related to the sampling period Ts. The ST duty ratio for inverter must be predefined for every switching cycle by adding the ST time within the TS. Figure 19a shows the dwell time control of inverter, and it is related to TS (= 1/fS), and Vin. To locate the selected switching vector for the Vref, a new method of vector identification is proposed. The strategy is to locate the Vref value and to find out the different switching states in the space vector diagram (SVD) hexagon (see Figure 20). Hence the control strategy is designed in two steps: (1) locate the real and imaginary equivalent of Vref, and (2) find out the control vector within the sector. Figure 19b represents the proposed control strategy in which, from the Vref slope, the real and imaginary equivalent of Vx and Vy are determined and compared with the targeted switching vector V1 and V1'. Here, when the condition is Vy < a Vx + b, then V1 is selected. Else V1' is selected. Once this targeting vector is selected, the Td is calculated and then active switching time, ST time and zero switching time is calculated according to the inverter output voltage requirement. Figure 20 represents the overall SVD for the proposed control strategy. Here, the entire active targeted vector is placed inside the SVD sector until the hexagonal boundary. The zero vectors [1,1,1] and [0, 0, 0] are placed at the origin. The control switching vector is directly related to the inverter modulation index (ma), where Vin and Vref are related to the inverter output. The maximum inverter control in the linear modulation range is allowed only until √ Vin [23]. The switching pulse patent of the proposed PWM is prearranged in Figure 21. Once the active and zero states are done, the ST state patent is included in the switching sampling period. The ST state is calculated based on the VPV value. Figure  22 represents the inverter switching pulse. The zero-state sharing ST state and ST time is calculated directly from the following equations: Where B is a boosting factor.

Simulation Result
The PV powered Q-impedance network connected coupled inductor multilevel inverter and its control switching schemes strategy is designed in MATLAB/Simulink software simulation platform ( Figure 23). The inverter is powered by 500 Watts peak power PV. The PV module is arranged to get 100 to 120 V to meet the 330 V DC-link voltage of the inverter. The insulation level of the PV array is 1000 W/m 2 for 10 s, 800 W/m 2 from 10 s to 30 s. The temperature of the PV array is 400°C for 10 s and 300 °C from 10 s onwards. The variation in PV array power input can be overcome by the Perturb and Observe the MPPT algorithm to obtain the constant DC voltage from the PV array. Table 2 shows the simulation parameter for the proposed inverter. The inverter performance is investigated with and without LC filters.  In order to validate the inverter performance simulation is carried out when the PV input power is kept at 500 W and the input PV voltage, VPV is maintained at 120 V. The impedance network duty ratio (TA and TST) is maintained at 20% to 25% to preserve the inverter input (DC-link) voltage 250 to 350 V. The inverter operation is investigated with their modulation index range ma = 0 to 0.866. The simulation study is carried out for different impedance network duty ratio TST and inverter modulation index range ma. Initially, the inverter is operated with a maximum modulation index of 0.886 with the ST switching time TST of 25%. Figure 24 shows the PWM pulse of inverter switches S1 and S6. The ST time between switch S1 and S2 is represented in Figure 25, in which the 25% switching time is used for ST event, and hence impedance network can boost input PV voltage nearly 290% and achieved 349 V in the output side of the impedance network (DC-link voltage of inverter). During the operation, the voltage of impedance network capacitors VC1 and VC2 shows uniform charging and discharging profile (see Figure 26) along with the uniform inductors current profile ( see Figure 27). Hence, during the ST period, the impedance network can draw the constant current and provide a regulated boost DC-link voltage to the MLI. Figures 28 and 29 illustrates the captured the inverter input DC-link voltage and multi-level output voltage across the load (Vab) respectively. From the results, it can be seen that the 120 V input PV voltage is boosted to 349 V. The inverter load voltage Vab is observed as 247.3 V (RMS). The corresponding Vab voltage THD spectrum is shown in Figure 30 (without filter). Here the inverter voltage THD is observed as 14.15%, which is higher due to the participation of passive elements in the impedance network. Hence the LC filter is connected across the load, and harmonics spectrum is captured (see Figure 31 and Figure 32). The output voltage THD perceived is very less as 2.81%. The inverter load current waveform and its corresponding current THD spectrum are captured and shown in Figure 33a,b. As expected, the current THD is very less (1.7%).  Next, the simulation study is extended to TST = 20% with 0.866 ma. In this operating condition, the impedance network has boosted the input PV voltage to nearly 230% and maintaining the inverter DC-link voltage at 280 V. The observed DC-link voltage and impedance network capacitor voltages are shown in Figures 34 and 35. While operating the inverter with a modulation index value of ma = 0.866, the inverter has produced the output voltage of 197.23 V, as shown in Figure 36. The inverter output voltage THD is shown in Figure 37. Using LC filter in the inverter output terminal similar to 25% TST performance, the voltage THD for TST = 20% is maintained lesser value as 2.71%. Correspondingly the current THD is observed as 1.70%. In order to validate the higher ST switching time, the simulation is extended to TST = 30% with different modulation indices. During this operating condition, the impedance network passive elements are utilized fully and hence the voltage THD triumphs to a higher value. Figures 38 and 39 illustrates the inverter output voltage and its corresponding voltage THD (without LC filter) for ma = 0.6. Though the inverter voltage is preserved as 292V nearly, the voltage THD is poor. Tables 3 and 4 illustrates inverter voltage and its THD performances for ma = 0.86 and ma = 0.6 through different duty ratio from 10% to 30% without and with an LC filter, respectively.   From the tabulated results, it could be seen that DC-link voltage has a linear variation with DST. However, the THD of the inverter voltage increases when increasing the DST. For any value less than or equivalent to DST 25% in any modulation index, the inverter provides a wide range of voltage variation with better voltage and current THD performance.

Experimental Result
The proposed PV powered Q-impedance fed coupled inductor multilevel inverter experimental setup was built using six MOSFETs IRF640. The switching signals were associated with the MLI through gate driver TLP250. The switching frequency, fs of the inverter is fixed 10 kHz for the 50 Hz inverter output. The 500 W PV module is arranged to get 100 to 120 V to meet 330 V DC-link voltage to the MLI. The RL load (resistance = 10 Ω and inductance = 5 mH) and LC filter (inductance and capacitor values of 2.5 mH, and 50 µF respectively) are used in the inverter output terminal. Figure 40 shows the experimental setup photograph. The impedance network and other parameters used for the inverter are the same as the simulation model given in Table 2. The control switching scheme strategy is designed in PIC16F778A microcontroller, and the collaborative results are shown in keyset two channels digital signal oscilloscope (DSO). The experimentation is carried out for the 500W constant PV power for 100 V and 5 amps current. The impedance network duty ratio is maintained at 25% with the aim of inverter constant DC-link voltage 300V. The inverter operation is investigated with its modulation index range ma = 0 to 0.866. Initially, the inverter is operated with maximum ma = 0.886, and the results are captured. Figure 41 shows the PWM pulse of inverter switches S1 and S2. The ST time between switch S1 and S2 is represented, in which the 25% switching time is used for ST event, and hence impedance network  can generate 300% boosting to maintain the DC-link voltage. Figure 42a shows the current waveform of impedance network inductor L1 and L2. Figure 42b displays the voltage waveform of impedance network capacitors C1 and C2. The voltage profile across the impedance network capacitors VC1 and VC2 are indicating that variation in the VC1 and VC2 are identical. It can be observed that voltages VC1 and VC2 are equally charging the voltage since both are connected in series. Hence the proposed impedance network can provide regulated DC-link voltage to the inverter. Figure 43a,b shows the inverter output voltage (without filters) and input voltage waveform at ma = 0.866. The results show the measured five-level inverter voltage with symmetrical set output voltage 0V, ± 125 V, ± 250 V. The THD value of load voltage is captured using power analyzer and is found to be about 17.1% (shown in Figure 44). The same experimentation is investigated further with filter, and the results are captured. Figure 45a,b shows the filtered output load and load current respectively, where the current and voltage are maintaining their THD lesser as 3.1% and 1.4% respectively ( Figure   To understand the inverter input current control, the duty cycle is varied to 25% and 30%, and results are observed. As expected, the inverter is maintaining the input current regulation at 25% DST. However, when DST is applied to 30%, the impedance network starts losing its input current regulation. Figure 47 illustrates the output voltage of MLI and impedance input current at 25% and 30% DST. From the results, it could be seen that the input PV voltage is boosted via the impedance network to achieve the load voltage of 230 V peak to peak. The DC-link voltage is regulated with a minor ripple of 3%, and hence inverter can maintain its half symmetry and THD of the output voltage is perceived as less. The interesting point to notice at this stage is that the inverter can draw constant current since the impedance network input inductor LS limits the current. The proposed inverter reliability study is conducted for different inverter operating conditions. Table 5 illustrations the switching loss, inverter efficiency, and THD of the proposed inverter for DST 10% to 30% and ma = 0.86. From the results, it can seem that the efficiency is higher in all duty cycle. During the 10% DST, the inverter efficiency is about 95.68%. However, there is a small dip inefficiency at 20% and 30% duty cycle.  The proposed inverter topology, in comparison with other reported topologies for the gain accomplishments, are deliberated in Table 6. In terms of passive element usage and maximum achievable voltage gain, the proposed topology is better than topology presented in [45][46][47]. By comparing the proposed topology with inverter proposed in [36], though the proposed inverter used one extra inductor, the voltage gain is high (3 times). Figure 48 illustrates the passive components rating, cost, boosting, and THD comparisons with other similar topologies [31,39] and [48]. The proposed inverter topology attains fewer passive elements usage, higher voltage gain conversion and better voltage THD than [31,39], and [48]. Thus, the proposed inverter topology presents its efficiency and suitability for PV standalone and grid-connected systems.

Conclusions
The proposed Q-source MLI coupled inverter ZSI is a combination of modified Q-source impedance network with six switches coupled inductor connected single-phase five-level MLI. The quasi-Z source coupled inductors MLI tied photovoltaic system with modified space vector PWM produces a maximum voltage gain of 140%. The suggested topology generates the five-level output voltage with the higher voltage gain (maximum voltage gains of 310%) with exceptionally low voltage and current THD. Besides, the proposed MLI reduces the switching stress on the inverter for all the duty cycles in the switching algorithm, when increasing the duty cycle, the boost factor also increases. The proposed quasi Q-ZSI has the merits of operation such as reliability, reduced passive components, voltage boosting capability and reduction in switching stress. The modified space vector PWM is proposed to integrate the boosting and regular inverter switching state within one sampling period.
In comparison with other MLI, it utilizes only half of the power switch, lower modulation index to acquire high voltage gain. The performance of the proposed boost MLI topology and control algorithm is theoretically investigated and validated through MATLAB/Simulink software and experimental upshots. The proposed topology is an attractive solution for stand-alone and gridconnected PV applications.