Hybrid DC Converter with Current Sharing and Low Freewheeling Current Loss

: A new hybrid high-frequency link pulse-width modulation (PWM) converter using voltage balance capacitor and current balance magnetic coupling is proposed to realize low freewheeling current loss and wide load range of soft switching operation. Series-connected H-bridge converter is adopted for high voltage applications. In addition, a voltage balance capacitor and a current balance magnetic coupling core are employed for achieving voltage and current balance. To extend zero-voltage switching (ZVS) range of switches at lagging-leg of phase-shift PWM converter, soft switching LLC converter is linked to the lagging-leg of phase-shift PWM converter. Therefore, the wide ZVS load operation is realized in the presented hybrid converter. The other high freewheeling current disadvantage in conventional phase-shift PWM converter is improved by a snubber circuit used on low-voltage side. Thus, the primary current during the freewheeling state is decreased and close to zero. In addition, the conduction losses on primary-side components of studied converter are reduced. The secondary-sides of phase-shift PWM converter and LLC resonant converter are series-connected to achieve power transfer between input and output sides. Experimental results using a laboratory prototype are provided to demonstrate the e ﬀ ectiveness of the studied circuit and control


Introduction
Medium voltage high-frequency link power converters have been presented and developed for boat electric power applications [1], industry power units [2], dc microgrids [3][4][5] and dc traction vehicles [6,7] to reduce the environmental impacts and global warming issue. To deal the medium voltage input such as 750 V, power switches, 1200 V insulated gate bipolar transistor (IGBT) or silicon carbide (SiC), can be adopted in conventional pulse-width modulation (PWM) converters to achieve power transfer or energy conversion. The drawback of IGBT power devices is low switching frequency operation and high turn-off switching loss. The disadvantage of the SiC power devices is their high cost. MOSFET power devices have the advantages of low cost and high performance capabilities to realize and develop modern power converters. Three-level PWM converters [8][9][10] can be used for high voltage input applications by using low voltage stress power switches. Full bridge converters are widely adopted to accomplish high power output. Pulse-width modulation with phase shift technique can improve power devices to be turned on under soft switching condition. However, the main weaknesses of phase-shift PWM converters are high freewheeling current and switching loss under low load condition. In [11], the snubber circuit is used on the output-side in order to lessen voltage overshoots on the rectifier diodes and also decrease the freewheeling current at the commutation state. To improve the switching loss of power switches at lagging-leg of phase-shift PWM converter under low load condition, an auxiliary circuit connected to the lagging-leg has been used in [12]. To achieve high efficiency PWM converter, phase-shift PWM converters with a resonant circuit connected to lagging-leg have been studied and developed in [13,14] to extend the soft switching range. For increasing power rating and circuit efficiency, the modular converter with series or parallel connection of several low power rating circuits has been studied and presented in [15]. The main challenge of modular converter is current balancing issue on each modular. Several current control approaches have been discussed in [16,17] to accomplish the current balance for each modular.
A hybrid PWM converter is studied and presented to achieve the advantages of low freewheeling current loss, the balanced current and voltage on two circuit modules and low switching loss on power switches. Two series-connected circuit modules are adopted to reduce the voltage stress on active devices and current stress on rectifier diodes. A flying capacitor is adopted on the primary-side to achieve voltage balance of input split capacitors. LLC converters sharing the lagging-leg switches of phase-shift PWM converters are used in the presented circuit to realize wide load range of soft switching operation. Two magnetic current balancing components are adopted on phase-shift PWM converters and LLC converters to achieve current sharing between two circuit modules. To reduce the high circulating current problem of conventional phase-shift PWM converters, a passive snubber is connected to the secondary-side rectified terminal. The structure and operation principle of the converter are discussed in Sections 2 and 3. In Sections 4 and 5, the circuit analysis and experiments with 1.68 kW prototype are provided. Finally, a conclusion of the studied converter is given in Section 6.

Circuit Diagram
In medium input voltage applications, the phase-shift PWM circuit topologies are widely used for medium and high-power converters. However, the conventional phase-shift PWM converter has the drawbacks of hard switching problem of power switches at the lagging-leg and high freewheeling current problem at the commutation state. For high voltage applications, three-level PWM dc converters or cascade converters shown in Figure 1 have been proposed to reduce voltage stress of active switches using high frequency power MOSFETs. The advantages of the cascade converters are less current rating of active switches compared to three-level converters and possible modular operation to extend input voltage range. However, the current sharing and input voltages balance are main problems of cascade full bridge converter. The circuit schematic in Figure 2a can overcome the problems of input voltage and current balance issues using a balance capacitor (highlighted in blue) between two circuit modules and a magnetic coupling element on primary-side (highlighted in red)). For extending the soft switching operation range at lagging-leg switches, LLC converter (remark in purple) and phase-shift PWM converter share the same lagging-leg switches shown in Figure 2b. Since a LLC converter has inductive input impedance characteristics, the wide soft switching operation of lagging-leg switches can be realized in the presented circuit and the weaknesses of conventional phase-shift PWM converters are overcome. Two phase-shift PWM and two LLC circuits are used on the input-side and two full-wave diode-rectifiers are adopted on the output-side. PWM scheme is adopted to control two full bridge converters. The magnetic coupling component MC1 is adopted to achieve current balance of i p1 and i p2 . If the currents i p1 and i p2 are balanced, the induced voltages on primary and secondary sides of MC1 are zero. If |i p1 | > |i p2 |, the induced voltages V MC1,1 and V MC1,2 decrease and increase respectively so that |i p1 | and |i p2 | will be decreased and increased respectively. After i p1 = i p2 , the induced voltages V MC1,1 = V MC1,2 = 0. A voltage balance capacitor C b is connected between two full bridge circuits. Since S 1 , S 2 , S 5 and S 6 have the same duty cycle (d = 0.5), one can obtain V Cb = V C1 = V C2 = V in /2. Two full bridge circuits are series connection on primary-sides and parallel connection on secondary-sides with a single transformer T 1 to reduce the current rating on primary-side of phase-shift PWM circuits. Passive snubber circuit, C p , D p1 and D p2 , is used to decrease i p1 and i p2 to zero at the commutation interval. Then, the high freewheeling current issue in conventional phase-shift PWM converter is eliminated. Since the switching frequency of LLC converters is close to series resonant frequency, the lagging-leg switches S 3 , S 4 , S 7 and S 8 are turned on at ZVS operation. At the active states (v AB and v DE = +V in /2 or −V in /2) of full bridge circuits, both PWM converters and LLC converters can achieve power transfer between V in and V o . On the other hand, only LLC resonant circuits achieve power transfer at the commutation state (v AB and v DE = 0 V).

Principles of Operation
In the proposed circuit topology, each active device has Tsw/2 turn-on time. The switching signals S1-S4 and S5-S8 are identical. The power components in the first and second circuits are identical to simplify the circuit analysis. In the proposed converter, nT1,p1 = nT1,p2 (primary turns of T1), nT2,p1 = nT2,p2 (primary turns of T2), CS1 = ... = CS8 = Coss, L1 = L2 = Llk1, Lr1 = Lr2 = Lr, and Cr1 = Cr2 = Cr. Figure 3 gives the PWM waveforms of the studied circuit and the related step circuits during one-half of switching period are provided in Figure 4.

Principles of Operation
In the proposed circuit topology, each active device has T sw /2 turn-on time. The switching signals S 1 -S 4 and S 5 -S 8 are identical. The power components in the first and second circuits are identical to simplify the circuit analysis. In the proposed converter, n T1,p1 = n T1,p2 (primary turns of T 1 ), n T2,p1 = n T2,p2 (primary turns of T 2 ), C S1 = . . . = C S8 = C oss , L 1 = L 2 = L lk1 , L r1 = L r2 = L r , and C r1 = C r2 = C r . Figure 3 gives the PWM waveforms of the studied circuit and the related step circuits during one-half of switching period are provided in Figure 4.

Principles of Operation
In the proposed circuit topology, each active device has Tsw/2 turn-on time. The switching signals S1-S4 and S5-S8 are identical. The power components in the first and second circuits are identical to simplify the circuit analysis. In the proposed converter, nT1,p1 = nT1,p2 (primary turns of T1), nT2,p1 = nT2,p2 (primary turns of T2), CS1 = ... = CS8 = Coss, L1 = L2 = Llk1, Lr1 = Lr2 = Lr, and Cr1 = Cr2 = Cr. Figure 3 gives the PWM waveforms of the studied circuit and the related step circuits during one-half of switching period are provided in Figure 4.     Step 1 [t0, t1]: Before time t0, S1, S4, S5 and S8 conduct. At time t0, active devices S5 and S1 are turned off. ip1 and ip2 will charge CS1 and CS5 and discharge CS2 and CS6. If the energy on Lo, L1 and L2 is larger than CS1, CS2, CS5 and CS6, then CS6 and CS2 are discharged and the zero-voltage switching of S6 and S2 can be realized at t1. Therefore, the time duration in this step is calculated: where n1 = nT1,p1/nT1,s turns ratio of transformer T1. Since iLr1 < iLm1,T2 and iLr2 < iLm2,T2, the secondary-side rectifier diodes D4 conducts. Step 1 [t 0 , t 1 ]: Before time t 0 , S 1 , S 4 , S 5 and S 8 conduct. At time t 0 , active devices S 5 and S 1 are turned off. i p1 and i p2 will charge C S1 and C S5 and discharge C S2 and C S6 . If the energy on L o , L 1 and L 2 is larger than C S1 , C S2 , C S5 and C S6 , then C S6 and C S2 are discharged and the zero-voltage switching of S 6 and S 2 can be realized at t 1 . Therefore, the time duration in this step is calculated: where n 1 = n T1,p1 /n T1,s turns ratio of transformer T 1 . Since i Lr1 < i Lm1,T2 and i Lr2 < i Lm2,T2 , the secondary-side rectifier diodes D 4 conducts.
Step 2 [t 1 , t 2 ]: The voltages v CS2 = v CS6 = 0 at t 1 . The body diodes of switches S 6 and S 2 conduct due to i p1 (t 1 ) > 0 and i p2 (t 1 ) > 0. Therefore, the ZVS turn-on operation of S 6 and S 2 are realized.
0, i p1 and i p2 decrease and D p1 conducts. Therefore, the primary voltages of T 1 is equal to n 1 v Cp and the voltage on L o is equal to v Cp − V o1 . Since v Lo < 0, i Lo decreases in step 2. The time interval in step 2 is calculated in Equation (2): Since the primary voltages of T 1 are positive, the primary currents i p1 and i p2 will decrease to zero during the circulating state. LLC resonant circuits are operated at resonant frequency (f sw ≈ f r ). The rectifier diodes D 4 is conducting to deliver power to output V o2 .
Step 3 [t 2 , t 3 ]: The secondary-side diode current i D1 decreases to zero at time t 2 . The currents i p1 = i Lm1 and i p2 = i Lm2 so that the wheeling currents are reduced in this step. The inductor current i Lo flows through passive components D p1 and C p1 and i Lo decreases due to v Cp < V o1 . LLC resonant converter achieves energy transfer through T 2 and D 4 .
Step 4 [t 3 , t 4 ]: Active devices S 8 and S 4 are turned off at t 3 . i Lr1 < 0 and i Lr2 < 0 so that C S7 and C S3 are discharged. At time t 4 , C oss3 is discharged to zero. Due to LLC resonant converters operated at the series resonant frequency, the ZVS turn-on operation of S 7 and S 3 are realized.
Step 5 [t 4~t5 ]: v Cs3 and v CS7 decrease to zero voltage at t 4 . Since i S7 (t 4 ) and i S3 (t 4 ) are negative, the antiparallel diodes of S 7 and S 3 are forward biased. Therefore, the ZVS operation of S 7 and S 3 is achieved after time t 4 . At step 5, the ac side voltages Thus, i Lo decreases and i p1 and i p2 decrease. LLC resonant converters are resonant with input voltage V in /2 so that i Lr1 and i Lr2 increase. At t 5 , |n 1 i p1 + n 1 i p2 | = i Lo so that D p1 becomes reverse biased and D p2 becomes forward biased. The time interval between t 4 and t 5 can be calculated as: No power is transferred in step 5 and the duty cycle loss in step 5 is calculated in (4): Step 6 [t 5 , t 6 ]: This step starts at time t 5 when D p1 (D p2 ) are reverse (forward) biased. Since D p2 conducts, it can obtain v Lo = v Cp2 and i Lo increases. L 1 and C p /(n 1 ) 2 are resonant in step 6. In order to ensure D p2 becomes reverse biased before step 7, the half resonant period by L 1 and C p /(n 1 ) 2 must be less than d eff,min T sw (the minimum turn-on time). In step 6, v T1,p1 = v T1,p2 = −(v Cp +V o1 ) and i p1 = i p2 = −(i Lo + i Cp )/(2n 1 ).
Step 7 [t 6 , t 7 ]: At time t 6 , i Dp2 = 0. In this step, passive components D p1 and D p2 are reverse biased, v Lo = V in /(2n 1 ) − V o1 and i Lo increases. S 6 and S 2 turn off at t 7 and the first half switching cycle is ended.

Circuit Analysis
In the proposed converter, phase-shift PWM converter realize power transfer to V o1 in steps 5-7 in the one-half of switching period and LLC resonant converter achieve power transfer to V o2 in every switching cycle. Since the switching frequency of LLC converter is fixed and close to series resonant frequency, the output voltage V o2 is unregulated. The ZVS turn-on of S 3 , S 4 , S 7 and S 8 can be achieved due to LLC converter operation with the following condition: where i Lm1,T2,max and i Lm2,T2,max are the maximum magnetizing currents on L m1,T2 and L m2,T2 , respectively. According to the switching frequency, transformer turns ratio, load voltage and the magnetizing inductances, i Lm1,max and i Lm2,max are obtained in Equation (6): The dead time between S 3 and S 4 is calculated in Equation (7): From the given dead time t d , the maximum magnetizing inductances L m1,T2 = L m2,T2 = L m,T2 are expressed in Equation (8): Since the LLC converter has unity voltage gain at resonant frequency, the output voltage V o2 is calculated in Equation (9): The zero-voltage switching condition of S 1 , S 2 , S 5 and S 6 is expressed in Equation (10): According to flux balance on leakage inductance on the secondary-side, the average voltage on C p is obtained as V Cp ≈ V in /(2n 1 ) − V o1 . The output voltage V o1 on steady state is calculated in Equation (11) by applying flux balance on L o : where the effective duty cycle d eff = d − d 5,loss and d is duty ratio of phase-shift PWM converter. Thus, the load voltage V o is expressed in Equation (12) and the dc voltage gain is calculated in Equation (13): The ripple current ∆i Lo is expressed in Equation (14): The minimum output inductance L o is derived in Equation (15) under the given ripple current ∆i Lo : The ripple currents on the magnetizing inductors of T 1 are calculated in Equation (16): The theoretical voltage stress of S 1~S8 is V in /2. The voltage stress of D 1 and D 2 are equal to V in /n 1 . The voltage stresses of D 3 and D 4 are equal to V in /(2n 2 ). The approximate voltage ratings of diodes D p1 and D p2 are V in /[4n 1 (1 − d e f f )]. The approximate average currents of D 1 and D 2 are equal to dI o and the average currents of D 3 and D 4 are (0.5 − d)I o . The inductor ratio L m1,T2 /L r1 of LLC converter is selected as 8. From the obtained L m1,T2 , the L r1 and L r2 are equal to L m1,T2 /8 and C r1 and C r2 are equal to 1/[4π 2 f 2 sw L r1 ].

Design Considerations and Test Results
The design procedures and the test results are provided in this section with the following electric specifications: V in = 750-800 V, V o = 48 V, I o = 35 A and f r (resonant frequency of LLC converter) = f sw (switching frequency) = 60 kHz. The assumed load voltages V o1 = 28 V and V o2 = 20 V. Since f sw = f r , the voltage gain of LLC resonant circuit is equal to unity. Therefore, n 2 of transformer T 2 can be calculated and expressed in Equation (17): G20N50C power MOSFETs with 500 V/20 A voltage/current stress and C oss = 300 pF are used for power devices S 1~S8 . The maximum magnetizing inductance of T 2 can be calculated as: where t d = 0.5 µs. The magnetic core EER42 is used to implement transformer T 2 with the magnetizing inductances L m1,T2 = L m2,T2 = 0.664 mH, the primary turns n T2,p1 = n T2,p2 = 30 and the secondary turns n T2,s = 3. Therefore, the series resonant inductances L r1 = L r2 = L m1,T2 /8 = 83 µH and the series resonant capacitances C r1 and C r2 are expressed as C r1 = C r2 ≈ 1/[4π 2 f 2 sw L r1 ] ≈ 85 nF. From the assumed d eff,max = 0.3, the turns ratio n 1 of transformer T 1 is calculated as: The magnetic core EER42 is used to design transformer T 1 with the following parameters: L m1,T1 = L m2,T1 = 4 mH, n T1,p1 = n T1,p2 = 57 and n T1,s = 6. The duty cycle loss d 5,loss is assumed 0.01. Therefore, the necessary inductances L 1 and L 2 of full bridge converter are calculated in Equation (20): If the ripple current ratio ∆i Lo /I o,rated is assumed 0.2, then the minimum output inductance L o is obtained in Equation (21): The inductance L o = 10 µH is used in the prototype circuit. MPR40100PT with V RRM = 100 V/I F = 40 A are adopted for the secondary-side diodes D 1 -D 4 , D p1 and D p2 . The other capacitors C 1 = C 2 = 180 µF/450 V, C b = 2 µF and C o1 = C o2 = 2000 µF. The magnetic cores EER 42 are used for current balance magnetic cores MC1 and MC2 with n p = n s = 24. Figure 5 gives the test results of switching waveforms of S 1 , S 4 , S 5 and S 8 at 750 V and 800 V input cases under full load. The switching signals S 1 (S 4 ) and S 5 (S 8 ) are identical and the PWM signals of S 4 (S 8 ) are lagging to the PWM signals of S 1 (S 5 ). Figure 6 shows the experimental voltages v AB and v DE and currents i p1 and i p2 of the phase-shift PWM converters under 20% and 100% loads.
The primary-side currents i Lp1 and i Lp2 are well balanced. The duty cycle on v AB and v DE at 100% load is larger than the duty cycle at 20% load due to d 5,loss in step 5 is related to I o . One can observe that the freewheeling currents of i p1 and i p2 are improved and close to zero. Figure 7 provides the experimental waveforms of the LLC resonant circuits at 20% and 100% loads. The inductors currents i Lr1 and i Lr2 are well balanced. Since f sw = f r , S 3 , S 4 , S 7 and S 8 are turned on at ZVS operation over whole load range. Figure 8 provides the test waveforms of capacitor voltages at primary-side under the full load with 800 V input. The capacitor voltages V C1 , V C2 and V Cb are all balanced. Figure 9a,b show the measured secondary-side currents of phase-shift PWM converter at 100% load. Passive snubber diode D p1 is forward biased when the ac side voltages v AB and v DE are zero voltage (the circulating state) and diode D p2 is forward biased when diode current i D1 or i D2 is greater than inductor current i Lo . Figure 9c provides the test waveforms of the output currents of LLC resonant converter at 100% load. The measured input current I in , load current I o and load voltage V o at 800 V input and 100% load are provided in Figure 9d. Figure 10a,b illustrate the experimental voltage and current of S 1 at 20% and 100% loads. One can observe that S 1 is turned on under zero voltage for both 20% and 100% loads. Likewise, the measured waveforms of S 4 at lagging-leg at 20% and 100% loads are provided in Figure 10c,d. S 4 is also turned on under zero voltage for both 20% and 100% loads. The other switches at leading-leg and lagging-leg have the same turn-on characteristics as S 1 and S 4 , respectively. The measured results shown in Figures 5-10 of the proposed hybrid converter and theoretical waveform analysis are agreed each other. Figure 11a provides the picture of a laboratory prototype. Figure 11b gives the measured efficiencies of the proposed converter and the full bridge LLC converter in reference (Lin, 2018) at 750 V input and different load conditions. The nominal rated power of the studied circuit is 1680 W and the measured circuit efficiency at 750 V input is 93.1%.
Energies 2020, x, x FOR PEER REVIEW 10 of 16 the duty cycle at 20% load due to d5,loss in step 5 is related to Io. One can observe that the freewheeling currents of ip1 and ip2 are improved and close to zero. Figure 7 provides the experimental waveforms of the LLC resonant circuits at 20% and 100% loads. The inductors currents iLr1 and iLr2 are well balanced. Since fsw = fr, S3, S4, S7 and S8 are turned on at ZVS operation over whole load range. Figure  8 provides the test waveforms of capacitor voltages at primary-side under the full load with 800 V input. The capacitor voltages VC1, VC2 and VCb are all balanced. Figure 9a,b show the measured secondary-side currents of phase-shift PWM converter at 100% load. Passive snubber diode Dp1 is forward biased when the ac side voltages vAB and vDE are zero voltage (the circulating state) and diode Dp2 is forward biased when diode current iD1 or iD2 is greater than inductor current iLo. Figure 9c provides the test waveforms of the output currents of LLC resonant converter at 100% load. The measured input current Iin, load current Io and load voltage Vo at 800 V input and 100% load are provided in Figure 9d. Figure 10a,b illustrate the experimental voltage and current of S1 at 20% and 100% loads. One can observe that S1 is turned on under zero voltage for both 20% and 100% loads. Likewise, the measured waveforms of S4 at lagging-leg at 20% and 100% loads are provided in Figure  10c,d. S4 is also turned on under zero voltage for both 20% and 100% loads. The other switches at leading-leg and lagging-leg have the same turn-on characteristics as S1 and S4, respectively. The measured results shown in Figures 5-10 of the proposed hybrid converter and theoretical waveform analysis are agreed each other. Figure 11a provides the picture of a laboratory prototype. Figure 11b gives the measured efficiencies of the proposed converter and the full bridge LLC converter in reference (Lin, 2018) at 750 V input and different load conditions. The nominal rated power of the studied circuit is 1680 W and the measured circuit efficiency at 750 V input is 93.1%.

Conclusions
This paper presents a PWM circuit topology to achieve a low voltage rating on active devices, wide soft switching load range and low freewheeling current compared to the conventional phaseshift PWM converter. Two series-connected phase-shift PWM circuits are used at input-side so that the voltage rating of active devices is reduced. One balance capacitor is used to accomplish voltage balance issue for two input split capacitors. LLC circuit shares the lagging-leg switches of phase-shift PWM circuit so that the ZVS operation capability of lagging-leg switches is improved. Magnetic coupling elements are used to achieve current-sharing issue between two phase-shift PWM circuits. Snubber circuit is employed on the output-side of phase-shift PWM circuit to improve the (d) Figure 10. Test waveforms of the active devices (a) S1 (leading-leg switch) under 20% load and 800 V input (b) S1 (leading-leg switch) under rated power and 800 V input (c) S4 (lagging-leg switch) under 20% load and 800 V input (d) S4 (lagging-leg switch) under rated power and 800 V input.
(a) (b) Figure 11. The picture and efficiency of the presented circuit (a) prototype circuit (b) circuit efficiency at 750 V input.

Conclusions
This paper presents a PWM circuit topology to achieve a low voltage rating on active devices, wide soft switching load range and low freewheeling current compared to the conventional phaseshift PWM converter. Two series-connected phase-shift PWM circuits are used at input-side so that the voltage rating of active devices is reduced. One balance capacitor is used to accomplish voltage balance issue for two input split capacitors. LLC circuit shares the lagging-leg switches of phase-shift PWM circuit so that the ZVS operation capability of lagging-leg switches is improved. Magnetic coupling elements are used to achieve current-sharing issue between two phase-shift PWM circuits. Snubber circuit is employed on the output-side of phase-shift PWM circuit to improve the

Conclusions
This paper presents a PWM circuit topology to achieve a low voltage rating on active devices, wide soft switching load range and low freewheeling current compared to the conventional phase-shift PWM converter. Two series-connected phase-shift PWM circuits are used at input-side so that the voltage rating of active devices is reduced. One balance capacitor is used to accomplish voltage balance issue for two input split capacitors. LLC circuit shares the lagging-leg switches of phase-shift PWM circuit so that the ZVS operation capability of lagging-leg switches is improved. Magnetic coupling elements are used to achieve current-sharing issue between two phase-shift PWM circuits. Snubber circuit is employed on the output-side of phase-shift PWM circuit to improve the freewheeling problem at the circulating state. The feasibility and performance of the presented circuit are verified by a laboratory prototype with 1.68 kW rated power.