Optimized Design of 1 MHz Intermediate Bus Converter Using GaN HEMT for Aerospace Applications

This paper presents the possibility of using Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) instead of the conventional silicon metal oxide semiconductor field effect transistor (MOSFET) to implement a high-frequency intermediate bus converter (IBC) as part of a typical distributed power architecture used in a space power application. The results show that processing the power at greater frequencies is possible with a reduction in mass and without impacting the system efficiency. The proposed solution was experimentally validated by the implementation of a 1 MHz zero-voltage and zero-current switching (ZVZCS) current-fed half-bridge converter with synchronous rectification compared with the same converter using silicon as the standard technology on power switches and working at 100 kHz. In conclusion, the replacement of silicon (Si) transistors by GaN HEMTs is feasible, and GaN HEMTs are promising next-generation devices in the power electronics field and can coexist with silicon semiconductors, mainly in some radiation-intensive environments, such as power space converters. The best physical properties of GaN HEMTs, such as inherent radiation hardness, low on resistance and parasitic capacitances, allow them to switch at higher frequencies with high efficiency achieving higher power density. We present an optimized design procedure to guaranty the zero-voltage switching condition that enables the power density to be increased without a penalization of the efficiency.


Introduction
Mass is one of the most critical parameters in aerospace applications due to the cost of launching and the need to accommodate increasing payloads. Therefore, the lower the weight of the platform, the larger the mass available for useful loads, like transponders in telecommunication satellites. Consequently, the mass reduction of the power systems is one of the main aims of advances in aerospace technology. This mass reduction is associated with (1) an increase of the efficiency of DC/DC power conversion units, which reduces the associated thermal dissipation and permits the use of smaller solar panels and batteries, and (2) a size reduction of the reactive components of power converters (inductors, transformers, and capacitors) when switching frequency is increased.
Currently DC/DC power converters used in the aerospace field are based on hard rad Si (Silicon) metal oxide semiconductor field effect transistor (MOSFETs) as switching devices. Si MOSFETs These types of loads demand high performance from their power sources, with accurately regulated low voltages (1 to 3.3 V), high currents up to 20 A, and fast transient responses. The wellknown and proven centralized power distribution architectures are incapable of meeting all these requirements while minimizing weight and space on board. Distributed power architectures (DPAs) with DC/DC point-of-load (POL) converters seem to be a promising solution [15][16][17]. Depending on the constraints and with a suitable design, these DPAs with POL architecture could provide an efficient solution for digital electronics loads and for general secondary power distribution purposes in aerospace systems.
Galvanic isolation, conversion, and voltage regulation are implemented using two cascaded converters in a distributed architecture. The first converter is an intermediate bus converter (IBC), which is responsible for galvanic isolation, and converts the main bus voltage to an intermediate voltage level. The second converter is a non-isolated POL converter, which transforms this intermediate voltage to the level required by the load voltage. The POL converters are physically near to the load circuits, where the DC distribution losses are minimized and parasitic inductance is reduced, thereby improving the performance and dynamic response [18]. Figure 1 shows a basic distributed power architecture (DPA). Some design restrictions must be considered to ensure the compatibility of the IBC and the POL impedance overlap. The selection of the IBC voltage level requires special attention because of its impact on the global system efficiency and the constraints implied for the POL design optimization. To validate the benefits of this power distribution system, the output voltage of the IBC was chosen to be compatible with the input of the POL, and a high output current for the required power level was chosen.

Intermediate Bus Converter
A suitable topology for the IBC was chosen considering parameters such as efficiency, power switch stress, manufacturing complexity, and cost. The result was a trade-off among three primary topologies: push-pull, half-bridge, or full-bridge. Regarding the output arrangement for these proposed converters, two secondary output schemes are available: the centre-tapped or the current doubler rectifier. The converter selected was a current-fed half-bridge topology with galvanic isolation and synchronous rectification in the secondary side. It is the best compromise considering efficiency, sizing of key parts and cost. This topology has been chosen because voltage stress of primary power mosfets cannot exceed power bus voltage, and synchronous rectification to reduce the conduction losses of secondary side. Figure 2 shows a simplified schematic of this configuration.  Some design restrictions must be considered to ensure the compatibility of the IBC and the POL impedance overlap. The selection of the IBC voltage level requires special attention because of its impact on the global system efficiency and the constraints implied for the POL design optimization. To validate the benefits of this power distribution system, the output voltage of the IBC was chosen to be compatible with the input of the POL, and a high output current for the required power level was chosen.

Intermediate Bus Converter
A suitable topology for the IBC was chosen considering parameters such as efficiency, power switch stress, manufacturing complexity, and cost. The result was a trade-off among three primary topologies: push-pull, half-bridge, or full-bridge. Regarding the output arrangement for these proposed converters, two secondary output schemes are available: the centre-tapped or the current doubler rectifier. The converter selected was a current-fed half-bridge topology with galvanic isolation and synchronous rectification in the secondary side. It is the best compromise considering efficiency, sizing of key parts and cost. This topology has been chosen because voltage stress of primary power mosfets cannot exceed power bus voltage, and synchronous rectification to reduce the conduction losses of secondary side. Figure 2 shows a simplified schematic of this configuration. In this topology, we take advantage of parasitic elements such as the leakage inductance of the transformer (Llk) and the parasitic capacitance of the power transistors (Cds) (Figure 2) to obtain a resonant switching behaviour, which provides higher performance than the conventional hard switching half-bridge. With a proper design, we can obtain zero-voltage and zero-current switching (ZVZCS) commutations [19].
In the next section, we show that the value of the tuning capacitors (Ct1, Ct2) has to be adjusted to achieve zero-current switching. This value has to guarantee that the current resulting from the resonance between each one of these capacitors and the leakage inductance of the transformer (Llk) are zero at both the beginning and the end of the conduction time intervals (Ton), i.e., when the turnon and turn-off switching transitions of the transistors are produced.
The transistors turn on after the off-time intervals (Tgap; Figure 3). To achieve zero-voltage switching, the transformer has to be designed with a proper magnetizing inductance value. This value has to ensure that the current flows through this inductance at the end of both conduction intervals Ton, and therefore its stored energy, are large enough to perform the following actions during Tgap:

•
Complete discharge of the parasitic capacitances Cds of both the half-bridge transistors and the synchronous rectifier transistors, which will be turned on after Tgap; • Complete charge of the parasitic capacitances (Cds) of both the half-bridge transistors and the synchronous rectifier transistors that have just turned off; • Complete charge of the transformer parasitic capacitance (Clk_trafo).
GaN HEMT transistors were selected to implement secondary side synchronous rectification due to their low channel resistance, higher achievable switching frequency (their rise and fall times are in the order of a few nanoseconds), and the absence of a source to drain parasitic diode, which allows the transistor conduction to be controlled in that direction. The use of this feature in the synchronous rectifier is explained in more detail in Section 3 Finally, the arrangement of the GaN HEMT of the synchronous rectifier stage was chosen to ensure a current flow from source to drain. Thereby, the gate trigger of these transistors was easier because the reference point was the output ground. As shown in Figure 2, each rectifier branch was constituted by two paralleled transistors to reduce the channel resistance in conduction mode. In this topology, we take advantage of parasitic elements such as the leakage inductance of the transformer (L lk ) and the parasitic capacitance of the power transistors (C ds ) ( Figure 2) to obtain a resonant switching behaviour, which provides higher performance than the conventional hard switching half-bridge. With a proper design, we can obtain zero-voltage and zero-current switching (ZVZCS) commutations [19].
In the next section, we show that the value of the tuning capacitors (C t1 , C t2 ) has to be adjusted to achieve zero-current switching. This value has to guarantee that the current resulting from the resonance between each one of these capacitors and the leakage inductance of the transformer (L lk ) are zero at both the beginning and the end of the conduction time intervals (T on ), i.e., when the turn-on and turn-off switching transitions of the transistors are produced.
The transistors turn on after the off-time intervals (T gap ; Figure 3). To achieve zero-voltage switching, the transformer has to be designed with a proper magnetizing inductance value. This value has to ensure that the current flows through this inductance at the end of both conduction intervals T on , and therefore its stored energy, are large enough to perform the following actions during T gap : • Complete discharge of the parasitic capacitances C ds of both the half-bridge transistors and the synchronous rectifier transistors, which will be turned on after T gap ; • Complete charge of the parasitic capacitances (C ds ) of both the half-bridge transistors and the synchronous rectifier transistors that have just turned off; • Complete charge of the transformer parasitic capacitance (C lk_trafo ).
GaN HEMT transistors were selected to implement secondary side synchronous rectification due to their low channel resistance, higher achievable switching frequency (their rise and fall times are in the order of a few nanoseconds), and the absence of a source to drain parasitic diode, which allows the transistor conduction to be controlled in that direction. The use of this feature in the synchronous rectifier is explained in more detail in Section 3 Finally, the arrangement of the GaN HEMT of the synchronous rectifier stage was chosen to ensure a current flow from source to drain. Thereby, the gate trigger of these transistors was easier because the reference point was the output ground. As shown in Figure 2, each rectifier branch was constituted by two paralleled transistors to reduce the channel resistance in conduction mode.

Circuit Description and Operation Principle
The main waveforms of the converter are shown in Figure 3, on which the explanation that follows will be based. The switching sequence of the primary-side transistors follows the order established by the operation of a classical half-bridge converter with a maximum duty cycle of 50% for each transistor. The operation of this converter will consist of a succession of four states: Ton1, GAP1, Ton2, and GAP2. Table 1 reflects the condition for each transistor that will have in each state. For simplicity, we distinguish only two equivalent states: the conduction of one of the transistors in primary side (GAN1 or GAN2) (Ton = Ton1 = Ton2) and the non-conduction of both transistors (Tgap = TGAP1 = TGAP2). Transistors GAN3 and GAN5 of the synchronous rectifier conduct during the on time

Circuit Description and Operation Principle
The main waveforms of the converter are shown in Figure 3, on which the explanation that follows will be based. The switching sequence of the primary-side transistors follows the order established by the operation of a classical half-bridge converter with a maximum duty cycle of 50% for each transistor. The operation of this converter will consist of a succession of four states: T on1 , GAP 1 , T on2 , and GAP 2 . Table 1 reflects the condition for each transistor that will have in each state. For simplicity, we distinguish only two equivalent states: the conduction of one of the transistors in primary side (GAN1 or GAN2) (T on = T on1 = T on2 ) and the non-conduction of both transistors (T gap = T GAP1 = T GAP2 ). Transistors GAN3 and GAN5 of the synchronous rectifier conduct during the on time of the GAN2 transistor, whereas transistors GAN4 and GAN6 conduct during the on time of transistor GAN1. During T on1 , the transistor GAN1 is in conduction mode and the resonance between the capacitor C t1 and the leakage inductor of the transformer (L lk ) takes place. Its equivalent circuit is shown in Figure 4a. This resonance is evidenced by the sinusoidal waveform of the current flowing through the primary of the transformer (i(t) in Figure 3). This resonant current is reflected to the secondary side of the transformer and flows through the GAN4 and GAN6 transistors in the source to drain direction, finally feeding the output load after being filtered by capacitor C out . Both the turning on and off of transistors GAN1, GAN4, and GAN6 occurs when the current flowing through them is zero. However, a small amount of current is circulating through them at these moments due to the magnetizing inductance of the transformer, which contributes to charging/discharging the parasitic capacitances.
Energies 2020, 13, x FOR PEER REVIEW 6 of 20 of the GAN2 transistor, whereas transistors GAN4 and GAN6 conduct during the on time of transistor GAN1. During Ton1, the transistor GAN1 is in conduction mode and the resonance between the capacitor Ct1 and the leakage inductor of the transformer (Llk) takes place. Its equivalent circuit is shown in Figure 4a. This resonance is evidenced by the sinusoidal waveform of the current flowing through the primary of the transformer (i(t) in Figure 3). This resonant current is reflected to the secondary side of the transformer and flows through the GAN4 and GAN6 transistors in the source to drain direction, finally feeding the output load after being filtered by capacitor Cout. Both the turning on and off of transistors GAN1, GAN4, and GAN6 occurs when the current flowing through them is zero. However, a small amount of current is circulating through them at these moments due to the magnetizing inductance of the transformer, which contributes to charging/discharging the parasitic capacitances. When the Ton1 interval finishes, the gap state (Tgap1) starts. During this time interval, the transformer magnetizing current charges the drain-source capacitor of GAN1 (Cds1) to an approximate value of Vin and discharges the drain-source capacitor of GAN2 (Cds2) to zero volts. Simultaneously, part of the magnetizing current is reflected to the secondary side of the transformer and charges the drain-source capacitors of the GAN3 (Cds3) and GAN5 (Cds5) transistors to a voltage Vout, and discharges the drain-source capacitors of GAN4 (Cds4) and GAN6 (Cds6) to zero volts. Finally, another small part of the magnetizing current charges/discharges the parasitic capacitance of the transformer (Clk_trafo). Once the capacitor charge/discharge process is finished, the GAN2, GAN4, and GAN6 transistors turn on at zero voltage, and a new Ton interval, equivalent to the previous one, will occur, although now it will be the capacitor Ct2 that will resonate with Llk.
During the gap interval, the linear charge of both capacitors Ct1 and Ct2 is also produced via the input current source ILin. The charge of Ct1 starts after its resonance interval. The charge of Ct2, which began after the end of its corresponding resonance interval, continues in this interval.
A deeper analysis of the different equivalent circuits was required to obtain the design equations that allow the converter design to be optimized. When the T on1 interval finishes, the gap state (T gap1 ) starts. During this time interval, the transformer magnetizing current charges the drain-source capacitor of GAN1 (C ds1 ) to an approximate value of V in and discharges the drain-source capacitor of GAN2 (C ds2 ) to zero volts. Simultaneously, part of the magnetizing current is reflected to the secondary side of the transformer and charges the drain-source capacitors of the GAN3 (C ds3 ) and GAN5 (C ds5 ) transistors to a voltage V out , and discharges the drain-source capacitors of GAN4 (C ds4 ) and GAN6 (C ds6 ) to zero volts. Finally, another small part of the magnetizing current charges/discharges the parasitic capacitance of the transformer (C lk_trafo ). Once the capacitor charge/discharge process is finished, the GAN2, GAN4, and GAN6 transistors turn on at zero voltage, and a new T on interval, equivalent to the previous one, will occur, although now it will be the capacitor C t2 that will resonate with L lk .
During the gap interval, the linear charge of both capacitors C t1 and C t2 is also produced via the input current source I Lin . The charge of C t1 starts after its resonance interval. The charge of C t2 , which began after the end of its corresponding resonance interval, continues in this interval.
A deeper analysis of the different equivalent circuits was required to obtain the design equations that allow the converter design to be optimized.

T on Interval
The equivalent circuit used for the mathematical analysis of the conduction interval of the transistors is shown in Figure 5, where V o , C o , and R o are the output voltage, the output capacitor and the load values of the components present in the secondary side of the transformer reflected to the primary side, respectively.

Ton Interval
The equivalent circuit used for the mathematical analysis of the conduction interval of the transistors is shown in Figure 5, where Vo, Co, and Ro are the output voltage, the output capacitor and the load values of the components present in the secondary side of the transformer reflected to the primary side, respectively. As the value of Co is much larger than the resonance capacitances and its series equivalent resistance (ESR) is very low, Vo was considered constant. A complete period of operation of the converter T is constituted by the addition of two Ton time intervals and two Tgap time intervals (T = 2·Ton + 2·Tgap).
To simplify the process for obtaining the equations that define the behaviour of the circuit in the Ton time interval, the magnetizing current iLmag(t) was neglected because of its small value in relation to the overall current flowing through the primary of the transformer i(t). This reduced magnetizing current grows linearly during the Ton time interval since the voltage across Lmag is Vo.

Calculation of i(t)
As a prior step to obtaining the differential equation that defines the behaviour of i(t), the voltage drop across the capacitor Ct1 can be deduced from Figure 5, where L is the leakage inductor of the transformer: The derivative in Equation (1) is: We know that: Substituting Equation (3) into Equation (2), the tuning capacitor current is: According to the circuit topology in Figure 4, the tuning capacitor current verifies the following relation: where I is the DC input current of the converter for a given output power. Substituting Equation (5) into Equation (4) and rearranging terms, we obtain the following differential equation: As the value of C o is much larger than the resonance capacitances and its series equivalent resistance (ESR) is very low, V o was considered constant. A complete period of operation of the converter T is constituted by the addition of two Ton time intervals and two T gap time intervals To simplify the process for obtaining the equations that define the behaviour of the circuit in the Ton time interval, the magnetizing current i Lmag (t) was neglected because of its small value in relation to the overall current flowing through the primary of the transformer i(t). This reduced magnetizing current grows linearly during the Ton time interval since the voltage across L mag is V o .

Calculation of i(t)
As a prior step to obtaining the differential equation that defines the behaviour of i(t), the voltage drop across the capacitor C t1 can be deduced from Figure 5, where L lk is the leakage inductor of the transformer: The derivative in Equation (1) is: We know that: Substituting Equation (3) into Equation (2), the tuning capacitor current is: According to the circuit topology in Figure 4, the tuning capacitor current verifies the following relation: where I Lin is the DC input current of the converter for a given output power. Substituting Equation (5) into Equation (4) and rearranging terms, we obtain the following differential equation: The solution to this differential equation is given by: where ω T on is the resonance frequency during T on , which is determined by: where C t = C t1 = C t2 . Fixing a null value of the primary current at the beginning of the time interval, the value of the angle ϕ must satisfy the following expression: Substituting Equation (9) into Equation (7), i(t) is obtained as: with a maximum value of: The value of cos ϕ will be determined later applying the current balance in the tuning capacitors. Equation (11) will be used to select the current specification requirement of the HEMTs. The appearance of the waveform of the primary current i(t) during T on is shown in Figure 6.
The solution to this differential equation is given by: where ω is the resonance frequency during Ton, which is determined by: where Ct = Ct1 = Ct2. Fixing a null value of the primary current at the beginning of the time interval, the value of the angle φ must satisfy the following expression: Substituting Equation (9) into Equation (7), i(t) is obtained as: with a maximum value of: The value of cosφ will be determined later applying the current balance in the tuning capacitors. Equation (11) will be used to select the current specification requirement of the HEMTs. The appearance of the waveform of the primary current i(t) during Ton is shown in Figure 6. In Equation (10) that the primary current has to be zero at the end of the Ton time interval: The following expression, which is used afterward, is obtained when the cosine of the first term of Equation (12) is developed: Calculation of vCt1 (t) Next, the equation that determines the behaviour of v (t) during Ton as a result of the resonance between Ct1 and L is calculated. To do this, the derivative of i(t) is found from Equation (10) and replaced in Equation (1): Then, the voltages across the tuning capacitor at the beginning and at the end of the Ton interval are obtained from Equation (14): In Equation (10) that the primary current has to be zero at the end of the Ton time interval: cos ω T on T on + ϕ = cos(ϕ) The following expression, which is used afterward, is obtained when the cosine of the first term of Equation (12) is developed: cos ω T on T on − tg(ϕ)· sin ω T on T on = 1 Calculation of v Ct1 (t) Next, the equation that determines the behaviour of v C t1 (t) during Ton as a result of the resonance between C t1 and L lk is calculated. To do this, the derivative of i(t) is found from Equation (10) and replaced in Equation (1): Energies 2020, 13, 6583 9 of 20 v C t1 (t) = L lk I L in cos ϕ ω T on sen ω T on t + ϕ + V o (14) Then, the voltages across the tuning capacitor at the beginning and at the end of the T on interval are obtained from Equation (14): Figure 4 shows that the mean value of voltage v C t1 in the T on interval must be V o (neglecting losses), as shown in Figure 7, which describes the variation in v C t1 (t) in a complete period of operation of the converter.

Tgap Interval
In the following calculations, neither the leakage inductance nor the parasitic capacitance of the transformer is considered due to their small values compared to the magnetizing inductance of the transformer and to the parasitic capacitances of the GaN HEMT, respectively. For the step-down transformer, the parasitic capacitances of the GaN HEMT in the synchronous rectification stage can be neglected, as their values reflected to the primary side are much lower than those of Cds1 and Cds2. Figure 8 shows the equivalent circuit for the Tgap time interval.

Calculation of v (t)
During the Tgap interval, two processes occur simultaneously. The first one is the linear charge of capacitors Ct1 and Ct2 with the energy supplied by the input current source, which is much larger than the magnetizing current. After completion of Ton, capacitor Ct1 is charged linearly (Figures 3 and  6) at a constant current I following: This linear charge continues until a complete period T of the converter is completed. Figure 7. Evolution of the voltage across the tuning capacitor v C t1 (t) during a switching period.

T gap Interval
In the following calculations, neither the leakage inductance nor the parasitic capacitance of the transformer is considered due to their small values compared to the magnetizing inductance of the transformer and to the parasitic capacitances of the GaN HEMT, respectively. For the step-down transformer, the parasitic capacitances of the GaN HEMT in the synchronous rectification stage can be neglected, as their values reflected to the primary side are much lower than those of C ds1 and C ds2 . Figure 8 shows the equivalent circuit for the T gap time interval.  Figure 4 shows that the mean value of voltage v in the Ton interval must be Vo (neglecting losses), as shown in Figure 7, which describes the variation in v (t) in a complete period of operation of the converter.

Tgap Interval
In the following calculations, neither the leakage inductance nor the parasitic capacitance of the transformer is considered due to their small values compared to the magnetizing inductance of the transformer and to the parasitic capacitances of the GaN HEMT, respectively. For the step-down transformer, the parasitic capacitances of the GaN HEMT in the synchronous rectification stage can be neglected, as their values reflected to the primary side are much lower than those of Cds1 and Cds2. Figure 8 shows the equivalent circuit for the Tgap time interval.

Calculation of v (t)
During the Tgap interval, two processes occur simultaneously. The first one is the linear charge of capacitors Ct1 and Ct2 with the energy supplied by the input current source, which is much larger than the magnetizing current. After completion of Ton, capacitor Ct1 is charged linearly (Figures 3 and  6) at a constant current I following: This linear charge continues until a complete period T of the converter is completed.

Calculation of v C t1 (t)
During the T gap interval, two processes occur simultaneously. The first one is the linear charge of capacitors C t1 and C t2 with the energy supplied by the input current source, which is much larger than the magnetizing current. After completion of T on , capacitor C t1 is charged linearly (Figures 3 and 6) at a constant current I L in following: Energies 2020, 13, 6583 10 of 20 This linear charge continues until a complete period T of the converter is completed.
Considering Equations (8), (15), (16), and (18), from Equation (19), we obtain: Since the mean value of v Ct1 (t) in the interval T on is V o , as shown in Figure 6, and considering the symmetry of the waveform, it follows that: Therefore, from Equations (15) and (16): sen ω T on T on + ϕ = −sen(ϕ) Substituting Equation (22) into Equation (20) and operating, we obtain: With this expression, the maximum current of the GaN HEMT can be determined from Equation (11). Substituting (23) into (13), we obtain: cos ω T on T on − ω T on 2T gap + T on 2 sin ω T on T on = 1 This transcendent equation will allow ω T on to be obtained from the values of T on and T gap . The fulfilment of Equations (19) and (21) implies that the mean value over a complete period of V Ct1 is V o . Since the voltage waveform in C t2 is identical to the voltage across C t1 , even though with a T on + T gap delay time, the mean value of V Ct2 is also V o . Finally, since the mean value of V Lin in Figure 2 is 0, V in = 2V o if ideal components are considered.

Calculation of i L mag (t)
Now, the time evolution of the magnetizing current must be known to ensure that its stored energy is large enough to guarantee the zero-voltage switching (ZVS) condition. The other process that occurs in the T gap time interval is the resonance between the magnetizing inductance of the transformer and the parasitic capacitances of the two transistors of the half bridge, C ds1 and C ds2 . During T gap , the resonant current charges the parasitic capacitance of the GaN HEMT previously in conduction from 0 V to a level slightly greater than V in . This current discharge the parasitic capacitance of the GaN HEMT previously off from almost V in to 0 V. At this precise time, this last transistor is switched on, achieving a zero-voltage and zero-current commutation.
The differential equation that defines the time behaviour of the current through the magnetizing inductance can be obtained by a previous analysis of the equivalent circuit in Figure 8, where: Energies 2020, 13, 6583 Subtracting both equations, we obtain: As the waveform of the voltage across C t2 is identical to the voltage across C t1 , although with a delay time T on + T gap , the difference between v ct1 and v ct2 in the T gap time interval, as shown in Figure 3, takes a constant value equal to: Taking the derivative in Equation (27): or employing the relation between voltage and current in the parasitic capacitances: As C ds = C ds1 = C ds2 and according to the relationship between currents: Finally, the differential equation that describes the evolution of the magnetizing current is: The solution to this differential equation is given by: where ω T gap is the resonant frequency during T gap : At the beginning of the GAP state, the magnetizing inductance, L mag , will be fully charged. Since the average value of its intensity is zero and it is charged during T on with a constant voltage of V o , during T gap it will maintain this intensity at its maximum point. Considering the symmetry of magnetizing current waveform (Figure 9) whose value is: The value of angle σ must fulfil i L mag (0) = i 0 ; therefore, from Equation (33): the average value of its intensity is zero and it is charged during Ton with a constant voltage of Vo, during Tgap it will maintain this intensity at its maximum point. Considering the symmetry of magnetizing current waveform (Figure 9) whose value is: The value of angle σ must fulfil i (0) = i ; therefore, from Equation (33): Substituting (36) into (33), we obtain: Calculation of σ VLmag (t) can be obtained from Equation (37) as: Substituting (36) into (33), we obtain: Calculation of σ V Lmag (t) can be obtained from Equation (37) as: Taking (38) for t = 0: Substituting i 0 from Equation (35) into (39), we obtain: As a result of this study, the maximum value of the magnetizing current can be known.

Condition to Guarantee ZVS Condition Accomplishment
From Figure 2, as shown in the waveforms in Figure 3, the v ds 2 voltage of GAN2 when GAN1 is conducting results from the addition of the voltages across the capacitors C t1 and C t2 . As the voltage across capacitor C t2 is identical to that across C t1 , although with a delay time T on + T gap , we obtain: and for t = T on , considering Equation (22): Magnetizing current is responsible for charging/discharging the drain to source capacitances. Therefore, the contribution of the magnetizing current during T gap must be large enough to charge C ds1 from 0 V to v ds (charge) and discharge C ds2 from v ds (discharge) to 0 V: The condition to guarantee the zero-voltage commutation of the transistors is obtained by integration with Equation (37):

Design Procedure
Firstly, the following converter specifications must be known: input and output voltages (to determine the transformer turns ratio), output power (to determine the input current assuming a typical efficiency of 95% for these type of converters), and switching frequency. With this information, the switches to be employed can be selected and their parasitic capacitances can be determined. In a first iteration of the design procedure, the duration of the on state, T on , is chosen so that 2T on /T is in the order of 70% of the switching period. This also determines the duration of the gap state T gap .
As explained above, during the gap state, the charging and discharging occur of the drain to source capacitances of the half-bridge switches from the stored energy in the magnetizing inductance at the end of the ON state. The initial value of this magnetizing current is i 0. The iterative design procedure continues selecting an initial value of i o , which at least permits the charging/discharging of the C ds capacitances for T gap , assuming a constant current process and a final value of 2V o , that is: Then, from (35), the magnetizing inductance that provides i o at time T on is: The value of L mag can be adjusted using an air gap in the implemented transformer. Now, the resonance frequency during the gap state ω Tgap can be known from Equation (34) and the value of σ angle, from Equation (40). The maximum value of the magnetizing current i Lmax can be calculated from Equation (36).
After, a numerical solution for the exact value of the duration of the gap state to guarantee the ZVS condition can be obtained from Equation (45). Once the value of T gap is obtained, as the period has a fixed value, the value of T on must be recalculated. If necessary, a new iteration is performed with these new values of T on and T gap .
As T on is already known, the value of the resonance frequency during the on state, ω Ton , can be determined using numerical calculation of Equation (24).
Next, the leakage inductance of the implemented transformer, L lk , is experimentally measured. The required values of the resonant capacitances C t are obtained from Equation (8). Then, we calculate the ϕ angle from Equation (23) to finally obtain the maximum value of the primary current I max from Equation (11). This value of I max should be much greater than i o . The flowchart in Figure 10 summarizes the design procedure.

Reverse Conduction Control of the Synchronous Rectifier Transistors
Reverse conduction of the GaN HEMT used as synchronous rectifier transistors, during the on states, is due to the generation of a conduction channel by applying a positive voltage V gs only during these states. determined using numerical calculation of Equation (24).
Next, the leakage inductance of the implemented transformer, Llk, is experimentally measured. The required values of the resonant capacitances Ct are obtained from Equation (8). Then, we calculate the φ angle from Equation (23) to finally obtain the maximum value of the primary current Imax from Equation (11). This value of Imax should be much greater than io. The flowchart in Figure 10 summarizes the design procedure.  As previously mentioned, the transistors of the synchronous rectification stage must be in the off state during the T gap time interval. A voltage V gs = 0 V can be applied to ensure this condition. However, the GaN HEMT transistor could begin to drive in the reverse direction if the gate is directly connected to the source (Figure 11a) and the source to drain voltage (V sd = V gd ) increases and reaches the threshold value for the generation of the conduction channel. This situation can occur if the secondary voltage reaches the voltage across C out plus this threshold voltage. This conduction interval would provide a method for the discharge of the magnetizing inductance; therefore, the loading and unloading processes of the parasitic capacitances of the half-bridge and synchronous rectifier transistors would not be completed, as shown in Figure 12. Consequently, the V ds voltage of the transistors to be connected would not be 0 V at the switching time. This would slightly increase the losses in the converter.

Reverse Conduction Control of the Synchronous Rectifier Transistors
Reverse conduction of the GaN HEMT used as synchronous rectifier transistors, during the on states, is due to the generation of a conduction channel by applying a positive voltage Vgs only during these states.
As previously mentioned, the transistors of the synchronous rectification stage must be in the off state during the Tgap time interval. A voltage Vgs = 0 V can be applied to ensure this condition. However, the GaN HEMT transistor could begin to drive in the reverse direction if the gate is directly connected to the source (Figure 11a) and the source to drain voltage (Vsd = Vgd) increases and reaches the threshold value for the generation of the conduction channel. This situation can occur if the secondary voltage reaches the voltage across Cout plus this threshold voltage. This conduction interval would provide a method for the discharge of the magnetizing inductance; therefore, the loading and unloading processes of the parasitic capacitances of the half-bridge and synchronous rectifier transistors would not be completed, as shown in Figure 12. Consequently, the Vds voltage of the transistors to be connected would not be 0 V at the switching time. This would slightly increase the losses in the converter.    This undesired reverse conduction can be prevented by employing a negative polarization voltage Vgs (Figure 11b). As V = V + V is fulfilled, under the same value of voltage Vsd, the voltage Vgd is prevented from reaching its threshold value for entering conduction. As the primary voltage at the end of the gap interval of GAN2 is determined by Equation (15), the required value of Vgs is obtained from: with = (49) This undesired reverse conduction can be prevented by employing a negative polarization voltage V gs (Figure 11b). As V gd = V gs + V sd is fulfilled, under the same value of voltage V sd , the voltage V gd is prevented from reaching its threshold value for entering conduction. As the primary voltage at the end of the gap interval of GAN2 is determined by Equation (15), the required value of V gs is obtained from: with n = number of primary turns number of secundary turns (49) Solving for V gs : V gs ≤ V gd(threshold) − L lk I L in ω T on tan ϕ n (50) Figure 12 shows the effect of the undesired reverse conduction of the synchronous rectifier transistors at the end of the gap state, defaulting the ZVS condition.

Experimental Design
A breadboard was implemented, working at a switching frequency of 1 MHz, input voltage of 50 V, output voltage of 6 V, and output power of 150 W. The transformer turns ratio, n (50), was four with an output current of 25 A. Following the design procedure, the on time was initially fixed to 350 ns and the gap time to 150 ns. To validate the benefits of using GaN HEMTs up to 1 MHz, we implemented another breadboard using a silicon MOSFET working at 100 kHz.

Selection of the Switches
Equation (11) provides the maximum value of the current through the half-bridge transistors. The maximum value of the current through the synchronous rectifier transistors was obtained multiplying the previous one by the transformer turns ratio and considering the two paralleled transistors.
The maximum operating voltage across the half-bridge transistors is slightly greater than the input voltage due to the resonance in the tuning capacitors. European Space Agency (ESA) requirements [20] establish that the transistor voltage in normal operation should not exceed 80% of the maximum voltage supported by the transistor. Transistors with a maximum voltage of 80 V were selected because the 60 V transistors do not meet the ESA requirements and the 100 V one is oversized.
For the selection of the synchronous rectifier transistors, we must consider that: V max_ sec = V Cout + V sec _trafo = 6 + 6 = 12 V (51) Considering again the ESA requirements, transistors with a maximum voltage of 30 V were found to be suitable for the rectification stage. Table 2 shows the requirements and the selection of the different transistors.

Transformer Design
Once the transformer turns ratio is known, the transformer design can be initiated, prioritizing the minimization of the values of L lk and C lk . To do this, the transformer was implemented using a planar ferrite core type E 32/6/20-3F4 and several 100 µm thick copper sheets to complete the required four turns on the primary side and one turn on each one of the secondary outputs. In order to achieve those goals, Ferroxcube's 3F4 Magnesium-Zinc ferrite was selected, as it has a relative permeability of 1000 was chosen, as it exhibits low loss in the 1-2 MHz range. The magnetizing inductance can be adjusted by means of the air gap. Figure 13 depicts the two planar transformers built for the 100 kHz and 1 MHz prototypes.

Calculation of Ctuning
As the transformer leakage inductance Llk was 37 nH and the measured value of the printed circuit parasitic inductances was 52 nH, the resonant inductance was 89 nH. From Equation (8), the required tuning capacitance Ctuning was 100 nF. X7R ceramic capacitors were employed for its implementation.

Calculation of Coutput
Several aspects must be considered to choose a proper output capacitance value. Firstly, the primary reflected value of the output capacitor must be much greater than the tuning capacitor Ct, following Equations (52) and (53): The output capacitor must be selected to limit the peak-to-peak output voltage ripple to a reasonable value. The output voltage ripple is given by: where ∆v is the capacitive voltage ripple: and ∆v is the resistive voltage ripple due to the series equivalent resistance (ESR):

Calculation of C tuning
As the transformer leakage inductance L lk was 37 nH and the measured value of the printed circuit parasitic inductances was 52 nH, the resonant inductance was 89 nH. From Equation (8), the required tuning capacitance C tuning was 100 nF. X7R ceramic capacitors were employed for its implementation.

Calculation of C output
Several aspects must be considered to choose a proper output capacitance value. Firstly, the primary reflected value of the output capacitor must be much greater than the tuning capacitor C t , following Equations (52) and (53): The output capacitor must be selected to limit the peak-to-peak output voltage ripple to a reasonable value. The output voltage ripple is given by: An output capacitance of 220 µF was implemented by connecting ten 22 µF capacitors in parallel to reduce the parasitic resistance to an approximate value of 5 mΩ. As such, output voltage ripple was about 300 mV and the power losses in the capacitor were nearly 2.3 W in worst-case conditions. To ensure the cut-off of the synchronous rectifier transistors during the Tgap time interval, a series connection of a diode and a small inductance was placed in the off path of the gate drive circuit ( Figure 15). This configuration provides a negative biasing of the gate with respect to the source during Tgap without needing an auxiliary negative voltage source, as is shown in the oscillogram of Figure 16. To ensure the cut-off of the synchronous rectifier transistors during the T gap time interval, a series connection of a diode and a small inductance was placed in the off path of the gate drive circuit ( Figure 15). This configuration provides a negative biasing of the gate with respect to the source during T gap without needing an auxiliary negative voltage source, as is shown in the oscillogram of Figure 16. To ensure the cut-off of the synchronous rectifier transistors during the Tgap time interval, a series connection of a diode and a small inductance was placed in the off path of the gate drive circuit ( Figure 15). This configuration provides a negative biasing of the gate with respect to the source during Tgap without needing an auxiliary negative voltage source, as is shown in the oscillogram of Figure 16.  i is the primary current (5 A/div), Vds_GAN1 is the drain to source of GAN1 (20 V/div), Vds_GAN2 is the drain to source of GAN2 (20 V/div) and Vgs_GAN3 is the gate to source of GAN3 working as synchronous rectifier (5 V/div). Time base: 200 ns/div.

Experimental Results
In the previous theoretical analysis, the only parasitic capacitances considered charged/discharged during the gap state were those of the half-bridge transistors. However, other smaller parasitic capacitances are charged/discharged, whose values were previously neglected.

VDS_GAN1 VDS_GAN2
i VGS_GAN3 Figure 16. Experimental main waveforms of the IBC working at 1 MHz. i is the primary current (5 A/div), Vds _GAN1 is the drain to source of GAN1 (20 V/div), Vds _GAN2 is the drain to source of GAN2 (20 V/div) and Vgs _GAN3 is the gate to source of GAN3 working as synchronous rectifier (5 V/div). Time base: 200 ns/div.

Experimental Results
In the previous theoretical analysis, the only parasitic capacitances considered charged/discharged during the gap state were those of the half-bridge transistors. However, other smaller parasitic capacitances are charged/discharged, whose values were previously neglected. These parasitic capacitances correspond to the transformer, to the synchronous rectifier transistors, and to the printed circuit board. Therefore, converter start-up requires fine adjustment of the transformer magnetizing inductance by slightly varying its air gap. Due to this adjustment, the switching on of the transistors was conducted at 0 V. Figure 16 shows the 1 MHz experimental waveforms of the converter working at maximum output power (150 W). Both the drain-to-source voltage of the half-bridge transistors and the primary current were as expected for a ZVZCS resonant converter.
The measured efficiency of the converter is shown in Figure 17. The obtained results for the 1 MHz GaN HEMT converter were compared with the achieved with another prototype working at 100 kHz and implemented using silicon MOSFET transistors. The experimental efficiencies of both prototypes were very similar.
Energies 2020, 13, x FOR PEER REVIEW 18 of 20 These parasitic capacitances correspond to the transformer, to the synchronous rectifier transistors, and to the printed circuit board. Therefore, converter start-up requires fine adjustment of the transformer magnetizing inductance by slightly varying its air gap. Due to this adjustment, the switching on of the transistors was conducted at 0 V. Figure 16 shows the 1 MHz experimental waveforms of the converter working at maximum output power (150 W). Both the drain-to-source voltage of the half-bridge transistors and the primary current were as expected for a ZVZCS resonant converter.
The measured efficiency of the converter is shown in Figure 17. The obtained results for the 1 MHz GaN HEMT converter were compared with the achieved with another prototype working at 100 kHz and implemented using silicon MOSFET transistors. The experimental efficiencies of both prototypes were very similar. Finally, Table 3 compares the weight, volume, and power density between these two prototypes. Power density was improved with the GaN HEMT converter, although this characteristic was not optimized in this initial prototyping stage that represent a proof of concept. Table 3. Volume, weight and power density of the two implemented prototypes. Figure 17. Evolution of the efficiency with the output power for the same topology but implemented with two different semiconductor technologies. Finally, Table 3 compares the weight, volume, and power density between these two prototypes. Power density was improved with the GaN HEMT converter, although this characteristic was not optimized in this initial prototyping stage that represent a proof of concept.

Conclusions
In this study, we propose the use of GaN HEMTs in a real DC/DC converter for a space power application. An intermediate bus converter based on an GaN HEMTs half-bridge ZVZCS resonant converter working at 1 MHz was designed and implemented. The experimental results and performance were compared with the same converter using silicon MOSFET transistors and working at 100 kHz. The experimental obtained confirmed the potential of GaN HEMTs to be used in power DC/DC converters for space applications, improving the power density while maintaining a similar efficiency. It should be noted that without having been able to have a magnetic material with lower losses for the megahertz range, the power density has been increased by 82%, maintaining the same efficiency as for the 100 kHz version. The efficiency is maintained, even though the frequency has increased around ten times, which is due to the excellent switching and conduction characteristics of the GaN HEMTs-among others, the small gate capacitance and the lower channel resistance in conduction should be pointed out. An optimized design procedure has been proposed to guaranty the zero-voltage switching condition, enabling an increase in the power density without a penalization of the efficiency.
In conclusion, the advantages provided by the proposed GaN HEMTs indicate that they will be able to replace the conventional silicon transistors in aerospace applications, considering their inherent radiation tolerance and small size, providing higher efficiency and smaller total size at the system level.