A Dynamic Multi-Cell FCL to Improve the Fault Ride through Capability of DFIG-Based Wind Farms

: Endowing wind farms (WFs) with fault ride through (FRT) capability is crucial to their continuous availability under various operating conditions. This paper proposes a dynamic adaptive multi-cell fault current limiter (MCFCL) topology to enhance the FRT capability of grid connected WFs. The proposed MCFCL consists of one transient cell (TC) and multi resistive cells (RCs) directly connected to the grid’s high voltage without using any series injection transformers nor any series connection of semiconductor switches. The transient cell of the MCFCL includes two transient limiting reactors (TLRs) to mitigate the transient fault current and limit the rate of change of the currents of the semiconductor switches during fault occurrence. The number of RCs in the MCFCL is determined based on voltage sag level. These latter are inserted in the fault path to provide an adaptive voltage sag compensation mechanism according to the voltage sag level. Assessment of the MCFCL under various sag conditions, showed that the MCFCL is able to e ﬀ ectively compensate for a wide range of voltage sags without any over voltage at the WF’s terminal. Comparison analysis with the conventional single-cell bridge-type FCL (SBFCL) showed the superior performance of the proposed MCFCL.


Introduction
To facilitate the integration of an increased number of wind turbines into the power grid, many countries have adopted new grid codes [1]. These latter aim at specifying the electrical performance that generation units must comply with in order to ensure the safe and reliable operation of power grids. Fault ride-through (FRT) capability which aims at mitigating the adverse effects of grid faults is among the aspects covered by grid codes [1,2]. This capability helps to WFs to remain connected to the grid for a certain time, under faulty conditions [2]. This measure prevents the widespread tripping of WTs due to grid disturbances and thwarts local or system wide instabilities [1,2].
Though hardware schemes such as static synchronous compensators (STATCOM), dynamic voltage restorers (DVR), unified interphase power controllers (UIPC) and energy storage systems (ESS) are reliable interfaces that can fulfil the FRT requirements of WFs; they require high capacity and accordingly high-cost power converters, thus making these solutions costly and impractical. Among the hardware schemes, FCLs were found to be effective FRT protection schemes [3,4]. Various FCL technologies have been proposed and developed in the literature to mitigate fault currents. They are generally classified into superconducting FCLs (SFCLs) [12,13], and solid-state FCLs (SSFCLs) [14,15]. Employing SFCLs in WFs provides a feasible interconnection mechanism to enhance FRT. However, they require high-cost superconducting materials and cooling systems when used in high voltage systems [14].
Recently, the bridge-type FCLs (BFCLs), which are classified as SSFCLs are receiving more attention as an effective measure to meet the WF requirements [15]. Though various BFCL topologies have been proposed and documented in the literature, they were reported to be used for FRT enhancement for the first time in [14]. In this topology, the discharging resistor (DR) was located in the DC side and the DR was used to consume the excess active power of the WF generators and improve their FRT capability. Firouzi et al. proposed a sliding mode controller-Based BFCL for Fault Ride-Through Performance Enhancement of DFIG-Based Wind in [15]. The authors further proposed a transformer-type BFCL with multi-resistors instead of a single DR to improve the DFIG FRT performance in [16]. Using a three-phase coupling transformer, however, was shown to reduce the efficiency of the BFCL under asymmetrical faults and increase its cost. The DR in the DC side was transferred into the AC side and implemented in parallel with the BFCL in [17]. Hossain used a BFCL with a series inductor and resistor to improve the transient stability of DFIG-based WTss [18]. A series capacitor and a resistor were used in [19], as limiting impedance to support the interconnection point voltage by supplying the necessary reactive power. Kartijkolaie et al. proposed to place the resistor in the DC side of the BFCLto consume the DFIG's active power and improve its FRT capability [20].
All the above mentioned BFCL-based techniques are based on single-cell FCLs. Their components and limiting impedance are designed considering the system voltage level and worst voltage sag condition, respectively. Additionally, they place the limiting impedance in series with the faulty line path, which can cause destructive over voltage at the WF's interconnection point for lower voltage sag level. Also, the limiting impedance switching in the single-cell BFCL (SBFCL) increases the failure rate and voltage stress of the semiconductor switches.
To mitigate the above problems, we propose in this paper a dynamic multi-cell FCL (MCFCL) topology. Its main contributions are as follows: • A multi-cell FCL that has a resistor in each cell and is directly connected to the power grid without using the series transformer, thus reducing the volume and cost of the MCFCL.

•
A FCL topology that puts the suitable number of cells in the fault path in accordance with the voltage sag level, thus providing an adaptive voltage sag compensation mechanism. • A design that is able to effectively mitigate voltage sag conditions ranging from low to severe and prevent the occurrence of over-voltages in the WF terminals. The remainder of the paper is organized as follows. The proposed MCFCL power circuit is detailed in Section 2. An analytical study of the proposed topography is provided in Section 3. The proposed topology is implemented to a DFIG-based WF and its performance is assessed under various voltage sag conditions in Section 4. Some concluding remarks are provided in Section 5.

Proposed Multi-Cell Fault Current Limiter (MCFCL) Topology
The proposed MCFCL configuration is illustrated in Figure 1a. The MCFCL consists of two main parts, including a transient cell (TC) and n resistive cells (RC) coupled in series arrangement to meet high voltage operation requirements. The TC of the MCFCL include two diodes (D 1 and D 2 ) and two transient limiting reactors (TLRs) to limit the transient fault current at the fault occurrence instant. Each RC of the MCFCL consists of two gate-turn off (GTO) semiconductor switches and one limiting resistor.

MCFCL Operation
The basic operating principle of the MCFCL is divided into normal and faulty operating conditions. Under normal conditions, all the RCs' GTO switches are closed. Therefore, the limiting resistors of RCs (R1-Rn) are bypassed. The AC line current (iL) passes through the D1-LD1-T11-T1n path and charges the LD1 to the peak value of the current iL. Also, for the negative half cycle of operation, the current iL flows through the D2-LD2-T21-T2n path and charges the LD2 to the peak value of the line current. Figure 1b illustrates the line current flow path under normal conditions for the positive and negative half cycle of operation, respectively. After several cycles, the LD1 and LD2 act as a DC current source. Thus, diodes D1 and D2 are freewheeling and result in a zero voltage drop under normal conditions. Note however, that under normal conditions, the flowing line current from TLRs and the semiconductor switches results in some power and voltage losses. However, the latter can be ignored in HV systems. When a short circuit fault occurs in the downstream of the MCFCL, the raising rate of the fault current is suppressed by the TLRs of the TC. Then, considering the coupling voltage level; the MCFCL control system will turn off the GTO switches. Therefore, the MCFCL inserts the combinational of limiting resistors according to Table 1, in fault path to restrict the fault current and compensate the voltage sag at the acceptable level. Figure 1c represents the fault current path under faulty operating conditions for the state S1 according to Table 1.

MCFCL Operation
The basic operating principle of the MCFCL is divided into normal and faulty operating conditions. Under normal conditions, all the RCs' GTO switches are closed. Therefore, the limiting resistors of RCs (R 1 -R n ) are bypassed. The AC line current (i L ) passes through the D 1 -L D1 -T 11 -T 1n path and charges the L D1 to the peak value of the current i L . Also, for the negative half cycle of operation, the current i L flows through the D 2 -L D2 -T 21 -T 2n path and charges the L D2 to the peak value of the line current. Figure 1b illustrates the line current flow path under normal conditions for the positive and negative half cycle of operation, respectively. After several cycles, the L D1 and L D2 act as a DC current source. Thus, diodes D 1 and D 2 are freewheeling and result in a zero voltage drop under normal conditions. Note however, that under normal conditions, the flowing line current from TLRs and the semiconductor switches results in some power and voltage losses. However, the latter can be ignored in HV systems. When a short circuit fault occurs in the downstream of the MCFCL, the raising rate of the fault current is suppressed by the TLRs of the TC. Then, considering the coupling voltage level; the MCFCL control system will turn off the GTO switches. Therefore, the MCFCL inserts the combinational of limiting resistors according to Table 1, in fault path to restrict the fault current and compensate the voltage sag at the acceptable level. Figure 1c represents the fault current path under faulty operating conditions for the state S1 according to Table 1. S 1 -S n represent the pair GTO switches' states of each cell. 1 and 0 represent the ON and OFF states of GTO switches, respectively. Also, V max T represents the maximum acceptable voltage of each cell. V PCC and V Th are the measured coupling voltage and the threshold value. After fault period, the coupling voltage starts to recover to pre-fault level. Once the coupling voltage exceeds the threshold value, the semiconductor switches are closed with sequenced arrangements.

MCFCL Control System
The control system of the MCFCL is illustrated in Figure 1d. Note that the grid coupling voltage succeeding the MCFCL location is used to detect the fault and control the MCFCL operation. First, the voltage at coupling point (V PCC ) and the threshold value (V Th ) are compared. If V PCC < V Th , the adaptive control circuit detects the fault. Following this, the control system determines the suitable number of cells, which should be inserted in fault path according to Table 1. When the fault is cleared, the V PCC return back to the pre-fault voltage. When the V PCC becomes greater than the V Th , the MCFCL control circuit opens the GTO switches with sequenced arrangements, respectively.

Procedure to Determine the Number of MCFCL Cells
The number of MCFCL cells is selected based on the voltage rating of the semiconductor switches of each RC. The maximum acceptable voltage of each cell is represented by V max T , which is the voltage rating of each GTO switch in each cell. The maximum voltage drop on each cell is obtained by: where V g and Z g represent the grid voltage and impedance, respectively. To ensure that the voltage drop of each cell is within acceptable ranges, the following inequality: V max T > V m should be satisfied. Hence, Equation (1) can be re-written as follows: The number of cells is obtained from (2) as follows:

Analytical Study of the Proposed MCFCL Topology
The configuration of a single phase MCFCL is illustrated in Figure 2a. To simplify the analysis, we consider a MCFCL with two cells, including one TC and one RC, which are located between the power source and the load. Vs and Zs represent the voltage and impedance source, respectively. Z L represents the sum of the load and line impedance in this system. V D and V F are the diodes and GTO switches forward voltages, respectively. Based on the grid operation condition, the MCFCL is divided into two conditions: normal and faulty.  Figure 2b shows the MCFCL performance under both normal and faulty conditions. Under normal conditions, both TLRs currents (id1 and id2) are charged to the positive and negative peak values of line current, respectively. Considering V = L di/dt, the voltage drop on these reactors is low and has no effect on the system performance in this case. The MCFCL operation under faulty condition is represented by periods P1-P4. When the short circuit fault occurs at t = t0, the line currents (iL) and id1 start to increase. The period P1 (t0 < t < t1), represents the MCFCL performance under this condition. Figure 3a represents the equivalent power circuit of the MCFCL for the period P1. Note that during P1, the line current (iL) flows through the D1-LD1-T1 path and charges the DC reactor (LD1). The line current can be expressed by: where R = rd1+ Rs and L = LD1+Ls.
(a)  Figure 2b shows the MCFCL performance under both normal and faulty conditions. Under normal conditions, both TLRs currents (i d1 and i d2 ) are charged to the positive and negative peak values of line current, respectively. Considering V = L di/dt, the voltage drop on these reactors is low and has no effect on the system performance in this case. The MCFCL operation under faulty condition is represented by periods P 1 -P 4 . When the short circuit fault occurs at t = t 0 , the line currents (i L ) and i d1 start to increase. The period P 1 (t 0 < t < t 1 ), represents the MCFCL performance under this condition. Figure 3a represents the equivalent power circuit of the MCFCL for the period P 1 . Note that during P 1 , the line current (i L ) flows through the D 1 -L D1 -T 1 path and charges the DC reactor (L D1 ). The line current can be expressed by: where R = r d1 + R s and L = L D1+ L s .  Figure 2b shows the MCFCL performance under both normal and faulty conditions. Under normal conditions, both TLRs currents (id1 and id2) are charged to the positive and negative peak values of line current, respectively. Considering V = L di/dt, the voltage drop on these reactors is low and has no effect on the system performance in this case. The MCFCL operation under faulty condition is represented by periods P1-P4. When the short circuit fault occurs at t = t0, the line currents (iL) and id1 start to increase. The period P1 (t0 < t < t1), represents the MCFCL performance under this condition. Figure 3a represents the equivalent power circuit of the MCFCL for the period P1. Note that during P1, the line current (iL) flows through the D1-LD1-T1 path and charges the DC reactor (LD1). The line current can be expressed by: where R = rd1 + Rs and L = LD1+Ls.  Solving (4), yields the following expression for iL: At t = t2, the control system of the MCFCL detects the fault and turns the GTO switches (T1 and T2) off. The period P2 (t1 < t < t2), represents the MCFCL performance under this condition. Figure 3b represents the equivalent power circuit of the MCFCL for the period P2. Note that during P2, the current iL is less than its counterpart id1 and the diodes D1 and D2 are in freewheeling state. Considering Figure 3b, the line current is derived as follows: Using (6), we can express the current iL as follows: where R = Rs + R and L = Ls. In period P3 (t2 < t < t3), the iL flows through D2-LD2-R path and charges the DC reactor (LD2). Figure 3c represents the equivalent power circuit of the MCFCL for the period P3. The voltage equation in this period is expressed by: Considering (8), the line current is expressed by: where R = rd1 + Rs + R and L= LD1 + Ls. In period P4 (t2 < t < t3), the iL is less than the id2 and the diodes D1 and D2 are freewheeling state. Note that the equivalent power circuit of the MCFCL for period P4 is the same as the one depicted in Figure 3b. Accordingly, the line current equation in this period is expressed using Equation (7).

Implementation to a DFIG-Based WF
To assess the performance of the proposed MCFCL topology, we implemented it to the single line diagram depicted in Figure 4a and simulated it using PSCAD/EMTDC software. The simulated WF is connected to the grid through the MCFCL and a 0.7 kV/20 kV transformer. A 20 MW aggregated DFIG-type WT is used to model the WF. Three short circuit faults with different fault impedances are considered to assess the performance of the MCFCL under three voltage sag ranges. Additionally, a comparison analysis with a SBFCL scheme [17] is carried over. In this case we swapped the MCFCL in the system shown in Figure 4a by a SBFCL and compared their performance. The values of RD = 30 Ω and LD = 10 mH are considered in this study. Figure 4b represents the SBFCL Solving (4), yields the following expression for i L : At t = t 2 , the control system of the MCFCL detects the fault and turns the GTO switches (T 1 and T 2 ) off. The period P 2 (t 1 < t < t 2 ), represents the MCFCL performance under this condition. Figure 3b represents the equivalent power circuit of the MCFCL for the period P 2 . Note that during P 2 , the current i L is less than its counterpart i d1 and the diodes D 1 and D 2 are in freewheeling state. Considering Figure 3b, the line current is derived as follows: Using (6), we can express the current i L as follows: where R = R s + R and L = L s . In period P 3 (t 2 < t < t 3 ), the i L flows through D 2 -L D2 -R path and charges the DC reactor (L D2 ). Figure 3c represents the equivalent power circuit of the MCFCL for the period P 3 . The voltage equation in this period is expressed by: Considering (8), the line current is expressed by: where R = r d1 + R s + R and L = L D1 + L s . In period P 4 (t 2 < t < t 3 ), the i L is less than the i d2 and the diodes D 1 and D 2 are freewheeling state. Note that the equivalent power circuit of the MCFCL for period P 4 is the same as the one depicted in Figure 3b. Accordingly, the line current equation in this period is expressed using Equation (7).

Implementation to a DFIG-Based WF
To assess the performance of the proposed MCFCL topology, we implemented it to the single line diagram depicted in Figure 4a and simulated it using PSCAD/EMTDC software. The simulated WF is connected to the grid through the MCFCL and a 0.7 kV/20 kV transformer. A 20 MW aggregated DFIG-type WT is used to model the WF. Three short circuit faults with different fault impedances are considered to assess the performance of the MCFCL under three voltage sag ranges. Additionally, Energies 2020, 13, 6071 8 of 14 a comparison analysis with a SBFCL scheme [17] is carried over. In this case we swapped the MCFCL in the system shown in Figure 4a by a SBFCL and compared their performance. The values of R D = 30 Ω and L D = 10 mH are considered in this study. Figure 4b represents the SBFCL power circuit. The parameters of the system under study are provided in Table 2. The dynamics of the wind turbine, DFIG, and its control system are briefly described in the next section.

Implementation to a DFIG-Based WF
To assess the performance of the proposed MCFCL topology, we implemented it to the single line diagram depicted in Figure 4a and simulated it using PSCAD/EMTDC software. The simulated WF is connected to the grid through the MCFCL and a 0.7 kV/20 kV transformer. A 20 MW aggregated DFIG-type WT is used to model the WF. Three short circuit faults with different fault impedances are considered to assess the performance of the MCFCL under three voltage sag ranges. Additionally, a comparison analysis with a SBFCL scheme [17] is carried over. In this case we swapped the MCFCL in the system shown in Figure 4a by a SBFCL and compared their performance. The values of RD = 30 Ω and LD = 10 mH are considered in this study. Figure 4b represents the SBFCL power circuit. The parameters of the system under study are provided in Table 2. The dynamics of the wind turbine, DFIG, and its control system are briefly described in the next section.

DFIG-Based Wind Turbine Model
The mechanical power (P m ) of the wind turbine can be expressed as [21,22]: where P m (10) P wt represents the mechanical power extracted from the wind energy, ρ, v w and λ are the air density, the wind speed, and the tip speed ratio, respectively. R is the blade radius, and C P (β, λ) as follows: The drive train system is modelled using the two-mass system detailed in [21]. Figure 4c shows the DFIG connected to the WT. The RSC and grid side converter (GSC) control systems are also depicted in this figure. The DFIG stator and rotor power circuit voltage and flux relations in the d-q synchronous reference frame are expressed by the following Equations (5) and (6): V qr = R r i qr + dϕ qr dt − (ω s − ω r )ϕ dr (16) λ qs = L s i qs + L m i qs (17) λ ds = L s i ds + L m i ds (18) λ qr = L s i qr + L m i qr (19) λ dr = L s i dr + L m i dr (20) Indices s, r, q and d represent the stator, rotor, q-axis and d-axis components of stator and rotor voltage and flux. L m is the magnetizing inductance. The RSC of the DFIG controls the output active and reactive power. Also, the GSC of the DFIG controls the DC link capacitor voltage and the grid coupling voltage (V PCC ). Additional details concerning the DFIG control system can be found in [5,6].

Simulation Results
To assess the performance of the proposed FRT scheme, we apply three short circuit faults with different fault impedances to the PCC bus at t = 5 s for 150 ms as shown in Figure 4a. In these conditions the PCC voltage drops to 0.01 pu, 0.35 pu and 0.75 pu, respectively. This enables us to analyze the performance of the proposed SBFCL scheme under low, medium, and severe voltage sag conditions, respectively.
The SBFCL resistance is R D = 30 Ω and each RC resistance of the MCFCL is R = 10 Ω. The wind speed is considered 14 m/s in this study. Considering system voltage, the MCFCL has four cells, include one TC and three RCs. Also, the voltage sag is divided into three range as demonstrated in Table 3. The switching states and voltage sag ranges are represented as Table 3.  In this condition, the fault resistance is set to be R f = 0.5 Ω, which results in a 0.25 voltage sag at PCC. The conventional SBFCL inserts the R D = 30 Ω in the fault path. However, the MCFCL control circuit turns off the S 1 and puts the R = 10 Ω in series with line in scenario C, considering Table 2. Figure 5 demonstrates the MCFCL performance for this condition.  Figure 5d shows the DC link voltage of DFIG. Considering this figure, it increases to 1.5 pu in this condition for scenario A. In scenario B, it gradually decreases during fault period and then raises to 2.2 pu after fault clearance. However, by using the MCFCL, the DC link voltage remains constant.

Medium Voltage Sag Condition
For this condition, the fault resistance is decreased, and the PCC voltage is decreased to 0.35 pu. The control circuit of the MCFCL opens switches S1 and S2 to insert two cells resistance in the fault path in scenario C, considering Table 2. Figure 6 shows the MCFCL performance for this condition. Figure 6a shows the output active power from WF for this voltage sag level. In this voltage sag level, the output active power from WF drops to 0.15 pu for scenario A. In scenario B, the active power in fault period remains constant, however; it increases to 2.5 pu and then drops after fault period. However, the MCFCL provide the lowest active power fluctuation during and after fault. Figure 6b shows the WF reactive power. Considering this figure, the MCFCL in scenario C has the lowest reactive power fluctuation. Figure 6c shows the terminal voltage for three scenarios in this condition. In scenario A, the terminal voltage drops to 0.4 pu. In scenario B, the terminal voltage raises to 1.2 pu It can be observed from Figure 5a, that the output active power from WF drops to 0.55 pu for scenario A. In scenario B, the active power remains constant during fault occurrence, however; it's post-fault dynamics show a sharp increase to 3 pu followed by a sudden decrease to near zero, which is harmful for the generator. However, scenario C reveals that using the MCFCL results in lower oscillations in the active power during the fault period and after fault clearance, which provides faster stabilization under faulty conditions. Figure 5b depicts the dynamics of the WF's reactive power. Note noticeable fluctuations of the WF's reactive power during post-fault in scenario B. However, with the MCFCL in scenario C, the reactive power fluctuations are lowest, and it quickly returns back to its pre-fault value. Figure 5c shows the dynamics of the terminal voltage for three scenarios under low voltage condition. Considering this figure, the terminal voltage drops to 0.75 pu in scenario A.
In scenario B, it raises to 1.5 pu and the DFIG stator experiences transient over-voltage. However, in scenario C, the terminal voltage is 0.9 pu and remains in acceptable range by using the MCFCL. Figure 5d shows the DC link voltage of DFIG. Considering this figure, it increases to 1.5 pu in this condition for scenario A. In scenario B, it gradually decreases during fault period and then raises to 2.2 pu after fault clearance. However, by using the MCFCL, the DC link voltage remains constant.

Medium Voltage Sag Condition
For this condition, the fault resistance is decreased, and the PCC voltage is decreased to 0.35 pu. The control circuit of the MCFCL opens switches S 1 and S 2 to insert two cells resistance in the fault path in scenario C, considering Table 2. Figure 6 shows the MCFCL performance for this condition. Figure 6a shows the output active power from WF for this voltage sag level. In this voltage sag level, the output active power from WF drops to 0.15 pu for scenario A. In scenario B, the active power in fault period remains constant, however; it increases to 2.5 pu and then drops after fault period. However, the MCFCL provide the lowest active power fluctuation during and after fault. Figure 6b shows the WF reactive power. Considering this figure, the MCFCL in scenario C has the lowest reactive power fluctuation. Figure 6c shows the terminal voltage for three scenarios in this condition. In scenario A, the terminal voltage drops to 0.4 pu. In scenario B, the terminal voltage raises to 1.2 pu during fault period in this condition. But, in scenario C, it is 0.9 pu and remains in acceptable range by using the MCFCL. Figure 6d shows the DC link voltage for all scenarios. It increases to 2 pu in scenario A. In scenario B, the DC link voltage increases after fault clearance to 1.5 pu and then recovers to its pre-fault value. However, in scenario C, it remains constant during and after fault.   Figure 7 depicts the MCFCL performance under severe voltage sag condition for the above mentioned three scenarios. In this condition, the control circuit of the MCFCL opens S1, S2, and S3 and inserts three RCs resistances in series with a line like the SBFCL.   Figure 7 depicts the MCFCL performance under severe voltage sag condition for the above mentioned three scenarios. In this condition, the control circuit of the MCFCL opens S1, S2, and S3 and inserts three RCs resistances in series with a line like the SBFCL.   Based on the above results, we can confirm that:

Severe Voltage Sag Condition
• Using the SBFCL produces high transient over voltage under low and medium voltage sag conditions, which is harmful for the DFIG under short circuit fault current.

•
The proposed MCFCL scheme is able to properly mitigate a wide range of voltage sag levels without producing any transient over voltage.

•
The MCFCL outperforms the SBFCL in terms of FRT performance and transient over-voltage under medium and low voltage sag levels.

•
Response and performance of both SBFCL and MCFCL are the same under severe voltage sag levels.

Conclusions
This paper proposed a novel MCFCL topology to mitigate voltage sags and facilitate the integration of DFIG-based WFs into the high voltage power grid. The proposed scheme includes one TC and multiple RCs directly connected to the grid without using the series transformer, which reduces the cost and volume of the MCFCL. It also inserts a suitable number of RCs in the fault path to provide an adaptive voltage sag compensation mechanism in accordance with the voltage sag level. Assessment of the proposed approach under various sag conditions, showed that the MCFCL is able to effectively compensate for a wide range of voltage sags and prevent the occurrence of over-voltages in the WF terminal. A major advantage of the proposed MCFCL scheme is its ability to insert a suitable number of cells in the fault path to provide the adequate voltage sag compensation in accordance with the severity of the voltage sag. A comparison analysis with the conventional single-cell bridge-type FCL (SBFCL) showed that, although the performance of the MCFCL is similar to that of SBFCL under severe