DC-DC High-Voltage-Gain Converters with Low Count of Switches and Common Ground

This paper presents a new concept and research results of DC-DC high-voltage-gain, high-frequency step-up resonant converters. The proposed topologies are optimized towards minimizing the number of switches and improvements in efficiency. Another relevant advantage of such type of converters is that they have a common input and output negative point. The proposed converters are based on the resonant switched-capacitor voltage multiplier circuit, and that is why they are compared with a classic converter from this family. The included results show the operating principle, possible switching methods with the consideration of their impact on the voltage gain level, as well as the voltage and current ripples. The operating concepts and analytical calculations are confirmed by simulation and experimental results.


Introduction
Switched capacitor (SC) circuits can be effectively used in power electronic converters [1]. The significant advantages of SC-based DC-DC power converters are high-voltage-gain, low volume, and quasi inductiveless design. To achieve oscillating currents, low-volume inductors can be used in those converters. They can be designed as air-chokes, or even be based on parasitic inductances of the circuits, resulting in a decrease in the weight of the converter. The design without ferrite chokes allows for the use of the converter in high ambient temperature and/or with a low-volume heat sink.
SC DC-DC converters represent one of the classes of non-isolated step-up converters [2][3][4]. Nowadays, there are a significant number of applications where isolated DC-DC step-up converters are required [3], due to technical reasons and safety requirements. However, various kinds of non-isolated converters are extensively developed as well. One of the prospective applications for non-isolated DC-DC step-up converters proposed in the literature [5][6][7][8][9][10] are photovoltaic (PV) systems. High step-up DC-DC converters are often required in grid-connected PV systems to transfer the energy from a low-voltage PV source to the grid [5,6]. In transformerless PV systems [7,8], as well as in microinverters [9], dual-stage DC-AC converters are one of the investigated solutions.
The SC step-up DC-DC converter could be a competitive solution to the switch-mode boost converter. An example of such an idea is presented in Reference [10]. The non-isolated step-up converter can be used not only for a single stage supply, but as a part of a system composed of series-connected converters as well. In such systems, isolation can be implemented in another stage of conversion, e.g., by using a series resonant converter [6,11].
High-voltage-gain in SC-based DC-DC converters can be achieved by applying a suitable topology concept. In References [12][13][14], an SC voltage multiplier (SCVM) has been presented. It is significant decrease in the number of switches. One of the converters presented in this paper requires only three switches, which is below the number of transistors used in a full-bridge LLC converter. Other advantages of the SC converters, such as: high gain, high power density and low weight (no transformer or bulky choke), fast dynamic response [3], ability for operation in high temperature (no ferrites), and simple control, can make them an alternative solution for existing topologies intended for high-voltage-gain non-isolated DC-DC conversion. SC-based topologies can be suitable for the miniaturization of converters that can be applied in emerging power electronics applications, such as wearable technology.
For the operational parameters of an SC converter, the switching strategy applied for a given topology can be essential, which has been demonstrated in Reference [14]. For the optimization purposes analyzed in this paper, various switching strategies are proposed for the new topologies. This makes it possible to determine the advantages of the presented topologies, also taking into consideration a variety of qualities, other than the count of switches.
The proposed converters are nearly pure switched-capacitor circuits, where a vast majority of energy is transferred via capacitors rather than inductors. The resonant inductors are used to achieve oscillatory currents. The inductors can be designed as air chokes, which reduces the weight of the converters and allows them to work in higher temperatures. However, another trend in the development of very high-voltage-gain converters can be observed in the literature. The concept presented in Reference [30] is based on coupled inductor (CI) converters that achieve good parameters such as voltage ratio, efficiency, low number of switches, or low voltage stress on switches. Notwithstanding, such converters use chokes and, therefore, differ from the presented SC-based concept regarding admissible ambient temperature of operation, weight, and volume. The design comparison can be analyzed in particular case studies.
In this paper, the qualities introduced by the new topologies will be compared with those of a classic SCVM and of other converters discussed in recently published papers.
The paper is organized as follows. Section 2 demonstrates two proposed topologies of the SC converters and presents the principles of their operation. For both converters, switching strategies are analyzed. The discussion is supported by the results of computer simulations of their operation in five cases of switching strategies. Moreover, with the use of the simulation results, a number of parameters of the converters operating under various switching strategies are compared as well. Section 3 contains efficiency models of the proposed converters that demonstrate their efficiency as a function of their parameters. Section 4 presents the laboratory setup and the experimental verification of its operation, including the efficiency of the converter. All the research results are concluded in Section 5.

Operating Principle of the Converters
The operating principle of the converters in Figure 1 is similar to that of other SC multipliers, and is based on the charging and discharging of the switched capacitors in consecutive stages (time intervals). However, various switching strategies can be proposed for the new converters, which creates differences in their parameters. In the SCVM, as well as in the case of the converters proposed in this paper, the switched capacitors are recharging in resonant circuits composed of a switched capacitor and a low-volume resonant inductor. This creates ZCS (zero current switching) operating conditions, and limits the current flow between the capacitors and the voltage source connected in parallel. The main difference between the topology of the proposed converters and the classic SCVMs is that in the former case, an LC circuit that is not a part of a traditional cell is used, usually consisting of a diode and two transistors [13]. This circuit is charged using the energy of the input source and the electric charge of the switched capacitor that is the nearest to the input source. Then, the middle capacitor is discharged to the output capacitor or to the switched capacitor nearer to the output. Its function is to increase the output voltage and the amount of converted power, simultaneously maintaining the same value of the input voltage and the same cell number as in the case of a typical SCVM.
The LCSCVMa (Figure 1a) offers a larger number of strategies than the LCSCVMb (Figure 1b), due to the possibility of independent control of switches S1 and S3. The basic switching strategies can be composed of 2, 3, or 5 stages.  The main difference between the topology of the proposed converters and the classic SCVMs is that in the former case, an LC circuit that is not a part of a traditional cell is used, usually consisting of a diode and two transistors [13]. This circuit is charged using the energy of the input source and the electric charge of the switched capacitor that is the nearest to the input source. Then, the middle capacitor is discharged to the output capacitor or to the switched capacitor nearer to the output. Its function is to increase the output voltage and the amount of converted power, simultaneously maintaining the same value of the input voltage and the same cell number as in the case of a typical SCVM.

Switching Strategy Concepts for the LCSCVMa
The LCSCVMa (Figure 1a) offers a larger number of strategies than the LCSCVMb (Figure 1b), due to the possibility of independent control of switches S 1 and S 3 . The basic switching strategies can be composed of 2, 3, or 5 stages.  The main difference between the topology of the proposed converters and the classic SCVMs is that in the former case, an LC circuit that is not a part of a traditional cell is used, usually consisting of a diode and two transistors [13]. This circuit is charged using the energy of the input source and the electric charge of the switched capacitor that is the nearest to the input source. Then, the middle capacitor is discharged to the output capacitor or to the switched capacitor nearer to the output. Its function is to increase the output voltage and the amount of converted power, simultaneously maintaining the same value of the input voltage and the same cell number as in the case of a typical SCVM.

Switching Strategy Concepts for the LCSCVMa
The LCSCVMa (Figure 1a) offers a larger number of strategies than the LCSCVMb (Figure 1b), due to the possibility of independent control of switches S1 and S3. The basic switching strategies can be composed of 2, 3, or 5 stages.  The main difference between the topology of the proposed converters and the classic SCVMs is that in the former case, an LC circuit that is not a part of a traditional cell is used, usually consisting of a diode and two transistors [13]. This circuit is charged using the energy of the input source and the electric charge of the switched capacitor that is the nearest to the input source. Then, the middle capacitor is discharged to the output capacitor or to the switched capacitor nearer to the output. Its function is to increase the output voltage and the amount of converted power, simultaneously maintaining the same value of the input voltage and the same cell number as in the case of a typical SCVM.

Switching Strategy Concepts for the LCSCVMa
The LCSCVMa ( Figure 1a) offers a larger number of strategies than the LCSCVMb (Figure 1b), due to the possibility of independent control of switches S1 and S3. The basic switching strategies can be composed of 2, 3, or 5 stages.  The main difference between the topology of the proposed converters and the classic SCVMs is that in the former case, an LC circuit that is not a part of a traditional cell is used, usually consisting of a diode and two transistors [13]. This circuit is charged using the energy of the input source and the electric charge of the switched capacitor that is the nearest to the input source. Then, the middle capacitor is discharged to the output capacitor or to the switched capacitor nearer to the output. Its function is to increase the output voltage and the amount of converted power, simultaneously maintaining the same value of the input voltage and the same cell number as in the case of a typical SCVM.

Switching Strategy Concepts for the LCSCVMa
The LCSCVMa ( Figure 1a) offers a larger number of strategies than the LCSCVMb (Figure 1b), due to the possibility of independent control of switches S1 and S3. The basic switching strategies can be composed of 2, 3, or 5 stages.           To characterize the switching strategies, Table 1 contains the idealized control logic waveforms of the transistors (signals S 1 to S 4 ), as well as the description of the particular operation stages. Dead times have been neglected in Table 1, but they have been taken into account in the simulations and experiments. Capacitor C 2 ( Figure 1) is not referred to as a switched capacitor. The maximum switching frequency (strategy C3) is defined as:

Switching Strategy Concepts for the LCSCVMa
where T pulse is the sum of the duration time T 0 /2 of a single current pulse of any transistor and the dead time t d (any period of time denoted as 1-5 in Table 1), and Figure 1). All the simulation results were obtained for the following parameters: U in = 50 V, L n = 620 nH, C n = 1.47 µF, f 0 = 166.7 kHz, T pulse = 4.2 µs (f Smax = 119 kHz), C out = 100 µF, P out = 200 W (n = 1, 2, 3). A resistance of 100 mΩ has been inserted into each branch as an equivalent to parasitic resistances. The time period T pulse , as well as the duty cycle of the switching signals of the transistors, remain constant in each switching strategy. The selection of the switching frequency depends on the power of the converter, achievable resonant inductance, and switching losses [13]. This parameter, as well as the others, can be fixed in the following steps. In the ZCS mode, the SC converters' transistors do not operate in the ZVS mode, and during their turn-ons, the output charge is shorted (C oss losses). The limit of C oss losses determines the switching frequency of the transistors taking into consideration their type and voltage stresses. The oscillation frequency should be nearly equal to the switching frequency to minimize conduction losses [13]. This frequency depends on the product of L n C n , and allows to select C n for a known value of L n . The maximum power of the converter depends on capacitance C n and the switching frequency [13], and it should be higher than or equal to the rated power for the selected parameters. The simulation results presented in this section have been obtained with the use of ICAP/4 simulation package based on the IsSpice4 simulator.

Simulation Results of the Switching Strategy C1
Figure 2 presents steady-state simulation waveforms of the LCSCVMa controlled according to strategy C1. From all the results, it can be seen that the switched capacitors are recharged by oscillatory currents and each stage of the switching is longer than the half-period of the oscillations.
The entire switching cycle is composed of five stages (Table 1). According to the principle of operation, turning on switches S 1 and S 3 involves the charging of the switched capacitors C 1 and C 3 . Capacitor C 3 is being charged from capacitor C 2 of the internal branch whose voltage is going down in this stage. The diode D 2 remains turned off, as u C2 > u C1 and u C2 > u in (Figure 2). In the next stage, switch S 2 is turned on, and capacitor C 2 is being charged from the source u in and capacitor C 1 connected in series with it. The charging of the output capacitor, from capacitors C 2 and C 3 connected in series, occurs in the next stage when the switch S 4 is turned on. At the same time, capacitor C 1 is being charged from the source. In the next two stages, capacitor C 2 and capacitor C out are being charged, consecutively.
The advantage of this switching strategy is reducing the number of the performed switching operations, which leads to switching losses limitation. In three of five stages of the switching period, only one switch is affected.
The input current has various values in each switching state, which is a drawback of this strategy. Therefore, a low-frequency component f S = f ac-in = f Smax /2.5 appears in current i in , as well as in all other currents and voltages in the circuit. Using this kind of switching requires using a large input filter and a large output capacitor. From the standpoint of the components' volume and input current filtering, this strategy is not favorable.
The output voltage used for the voltage gain calculation in relation (3) has been measured as the average value of the waveform presented in Figure 3 together with the output current. Further results, given in Equations (4)- (7), were obtained in the same manner.
In this strategy, the measured average value of the output voltage of the converter equals U out = 178 V. For the input voltage of the converter U in = 50 V (maintained by the voltage source in simulations), the voltage gain of the converter under switching strategy C1 equals: 2.1.2. Simulation Results of the Switching Strategy C2 Figure 4 presents simulation waveforms in the LCSCVMa controlled according to strategy C2. In this strategy, each switching period consists of three stages. The first two switching stages correspond to those in strategy C1. In the third stage, only transistor S 3 is on. The last two stages of strategy C1 do not occur here, and capacitor C 2 is charged and discharged only once in a switching period. The number of the switching operations is lower in comparison to that in strategy C1. The spectrum of currents and voltages shows more favorable qualities in strategy C2 versus C1, as the 50 kHz components are not present (the lowest frequency is 75 kHz).
In this strategy, the measured average value of the output voltage of the converter equals U out = 177 V. For U in = 50 V, the voltage ratio is 2.1.3. Simulation Results of the Switching Strategy C3 Figure 5 presents simulation waveforms in the LCSCVMa controlled according to strategy C3. In this strategy, there are only two stages. In the first stage, the charging of the switched capacitors takes place (switches S 1 and S 3 are turned on). During the second stage, the output capacitor and C 2 are being charged (with switches S 2 and S 4 turned on).
In this strategy, each switch operates with a much higher frequency than in the case of strategies C1 and C2. This brings an improvement in the spectrum of the currents and voltages, as the lowest frequency is 120 kHz. It is favorable from the passive components volume optimization standpoint.
In strategy C3, the measured average value of the output voltage of the converter equals U out = 185 V, and for U in = 50 V, the voltage ratio is

Switching Strategy Concepts for the LCSCVMb
The LCSCVMb converter is simpler than the LCSCVMa, and contains three switches only. There is only one stage of charging the switched capacitors, realized by the switch S 1 , and two possible stages of discharging them, controlled by switches S 2 and S 3 . This creates two switching strategies for this converter, which are presented in Table 2. Figures 6 and 7 depict simulation waveforms of the LCSCVMb controlled according to these strategies.

Strategy C4
Energies 2020, 13, x FOR PEER REVIEW 9 of 22  Similarly to strategy C2 for the LCSCVMa, strategy C4 gives the following characteristic in the LCSCVMb: 1. Simultaneous charging of all the switched capacitors 2. Discharging C 1 to the internal branch (C 2 ) 3. Discharging C 2 and C 3 to the output

Strategy C5
Energies 2020, 13, x FOR PEER REVIEW 9 of 22  Similarly to strategy C3 for the LCSCVMa, strategy C5 gives the following characteristic in the LCSCVMb: 1. Simultaneous charging of all the switched capacitors 2. Simultaneous discharging of all the switched capacitors and charging the internal branch (C 2 ) Energies 2020, 13, x FOR PEER REVIEW 9 of 22

Comparison among the Topologies and Switching Strategies
In Subsections 2.1 and 2.2, a significant number of waveforms are presented for the particular strategies. The differences in the waveforms of the currents and voltages are clear, but to compare the concepts of the converters and the switching strategies, the following parameters will be taken into consideration and presented in charts: In this strategy, the measured average value of the output voltage of the converter equals U out = 172.1 V, which yields (for U in = 50 V): 2.2.2. Simulation Results of the Switching Strategy C5 Figure 7 presents simulation waveforms for the LCSCVMb controlled according to strategy C5. The current and voltage waveforms of the strategy C5 are nearly identical with those in strategy C3.
In this strategy, the measured average value of the output voltage of the converter equals U out = 181.4 V. For U in = 50 V, the voltage ratio is:

Comparison among the Topologies and Switching Strategies
In Sections 2 and 2, a significant number of waveforms are presented for the particular strategies. The differences in the waveforms of the currents and voltages are clear, but to compare the concepts of the converters and the switching strategies, the following parameters will be taken into consideration and presented in charts: The data are presented in Table 3, where the parameters of the SCVM (on the basis of Reference [14] for an appropriate strategy) are included as well.  The data are presented in Table 3, where the parameters of the SCVM (on the basis of Reference [14] for an appropriate strategy) are included as well.    Table 3). Quantity  Table 3). Quantity proportional to undesired output voltage decrease: 0.06·(200 -Uout) (axis 3). Ratios of the lowest frequencies in the input and output current: 0.4·f ac_in SCVM/f ac_in (axis 4), 0.4·f ac_out SCVM/f ac_out (axis 5).  Table 3.  Table 3.
In Figure 8, the coefficients 0.06 and 0.4 are used respectively, to better visualize the undesired output voltage decrease in regard to the theoretical value of 200 V, and the lowest frequencies in the input and output current of the discussed converters compared to those in the SCVM. In each case, a lower value on the graph is better.
From the chart presented in Figure 9a, it follows that the lowest peak-to-peak (p-p) voltages, in all the strategies, are equal the voltage across capacitor C3. Moreover, the strategies C3 and C5 show the lowest p-p voltages for all the internal capacitors (C1-C3). Figure 9b demonstrates that the currents of inductor L3 are the lowest, and the strategies with the lowest inductor currents are C3 and C5.  Table 3.  Table 3.
In Figure 8, the coefficients 0.06 and 0.4 are used respectively, to better visualize the undesired output voltage decrease in regard to the theoretical value of 200 V, and the lowest frequencies in the input and output current of the discussed converters compared to those in the SCVM. In each case, a lower value on the graph is better.
From the chart presented in Figure 9a, it follows that the lowest peak-to-peak (p-p) voltages, in all the strategies, are equal the voltage across capacitor C3. Moreover, the strategies C3 and C5 show the lowest p-p voltages for all the internal capacitors (C1-C3). Figure 9b demonstrates that the currents of inductor L3 are the lowest, and the strategies with the lowest inductor currents are C3 and C5.  Table 3.
In Figure 8, the coefficients 0.06 and 0.4 are used respectively, to better visualize the undesired output voltage decrease in regard to the theoretical value of 200 V, and the lowest frequencies in the input and output current of the discussed converters compared to those in the SCVM. In each case, a lower value on the graph is better.
From the chart presented in Figure 9a, it follows that the lowest peak-to-peak (p-p) voltages, in all the strategies, are equal the voltage across capacitor C 3 . Moreover, the strategies C3 and C5 show the lowest p-p voltages for all the internal capacitors (C 1 -C 3 ). Figure 9b demonstrates that the currents of inductor L 3 are the lowest, and the strategies with the lowest inductor currents are C3 and C5.
The same qualities are visible in charts presented in Figure 10, which clearly demonstrate that the parameters of strategy C4 are nearly the same as those of strategy C2. The same refers to strategies C5 and C3. The LCSCVMa and LCSCVMb converters can be further extended to units of higher voltage gain, similarly as in the case of the converters presented in References [13,22,25,26,29]. Taking into consideration the number of switches and diodes, as well as the frequency of the input current, both the proposed converters are very attractive for high-voltage-gain (Table 4). It should be noticed that the converter extension is very effective in the case of the LCSCVMb concept. For voltage gain G U = 8, it requires only four switches, which is an excellent result in comparison to other pure SC converters. Other parameters such as voltage stresses on the switches can be found in the literature. Table 4. Comparison of the number of switches and diodes, and the lowest frequency of the input current in selected topologies versus the voltage gain. Ref. = Reference.

Efficiency Model of the LCSCVM Converters
The analysis below concerns the LCSCVMa operating under the strategy C3 (Table 1) and LCSCVMb operating under the strategy C5 (Table 2). In both cases, there are two stages of operation. Figure 11 depicts the current paths in the LCSCVMa. In the LCSCVMb, the switch S 1 conducts the sum of currents i L1 and i L3 in the stage 1, whereas the current paths in the stage 2 are the same as in the LCSCVMa. The same qualities are visible in charts presented in Figure 10, which clearly demonstrate that the parameters of strategy C4 are nearly the same as those of strategy C2. The same refers to strategies C5 and C3.
The LCSCVMa and LCSCVMb converters can be further extended to units of higher voltage gain, similarly as in the case of the converters presented in References [13,22,25,26,29]. Taking into consideration the number of switches and diodes, as well as the frequency of the input current, both the proposed converters are very attractive for high-voltage-gain (Table 4). It should be noticed that the converter extension is very effective in the case of the LCSCVMb concept. For voltage gain GU = 8, it requires only four switches, which is an excellent result in comparison to other pure SC converters. Other parameters such as voltage stresses on the switches can be found in the literature.

Efficiency Model of the LCSCVM Converters
The analysis below concerns the LCSCVMa operating under the strategy C3 (Table 1) and LCSCVMb operating under the strategy C5 (Table 2). In both cases, there are two stages of operation. Figure 11 depicts the current paths in the LCSCVMa. In the LCSCVMb, the switch S1 conducts the sum of currents iL1 and iL3 in the stage 1, whereas the current paths in the stage 2 are the same as in the LCSCVMa. Assuming ideal power electronic switches, and a constant value of the input (Uin) and the output (Uout) voltage, as well as neglecting parasitic resistances and voltage drops across the power electronic devices, the currents in the stage 1 (Figure 11a) can be described as follows: With the characteristic impedance and the angular resonant frequency given by Assuming ideal power electronic switches, and a constant value of the input (U in ) and the output (U out ) voltage, as well as neglecting parasitic resistances and voltage drops across the power electronic devices, the currents in the stage 1 (Figure 11a) can be described as follows: With the characteristic impedance and the angular resonant frequency given by Energies 2020, 13, 5657

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where U C11 is the initial voltage across capacitor C 1 , and I 1m and I 2m /2 are the current amplitudes. Equation (8) presents the current of a typical series LC circuit supplied from a voltage source, and Equation (9) was obtained also taking into account the initial values of the capacitor voltages. The values of the passive components depend on the assumed nominal power (P nom ), switching frequency (f S ), and the volume of the resonant inductor. The values of time T pulse (1), and finally T 0 (2) and ω 0 (11), are assumed taking into account the limit of the switching losses in the converter. The capacitance of the switched capacitors is determined by the charge required to be transferred in a single switching pulse. The maximum power of the SCVM-type converter is achieved when the switched capacitors are fully discharged in a switching cycle (and then charged to the voltage equal to 2U in ). This determines the minimum capacitance, which in the SCVM composed of n switching cells is defined as follows: In a quasi inductiveless SCVM-type converter, the value of resonant inductance (L) is very small (L can be designed as a PCB air choke). Therefore, to achieve the assumed switching frequency, the capacitance of the switched capacitors can be selected considerably bigger than C min (as in the case of the experimental setup presented in this paper). In the stage 2 (Figure 11b), the currents of capacitors C 1 -C 3 and inductances L 1 -L 3 have the same values (Equations (8)-(10)) as in the stage 1, but with the opposite signs. The voltages across the capacitors C 1 , C 2 , and C 3 in the stage 1 are given by where U C21 and U C31 are the initial voltages across capacitors C 2 and C 3 , respectively. In the stage 2 (Figure 11b), the expressions for voltages have similar forms with appropriate signs and initial values.
Based on the formulas mentioned above, all the voltage initial values and the output voltage can be computed as a function of U C11 . For example, we obtain U C11 can be calculated taking into account (8) and the following relation where From Equations (16) and (18), we have (20) In practical converters, there are voltage drops across the circuit elements like the diodes and the transistors, which result in a variation of the output voltage with power and frequency.
The efficiency of an SCVM-type converter is determined by the resistances of its components, voltage drops on the diodes and transistors, the input voltage, power, and by the relation between the Energies 2020, 13, 5657 15 of 22 switching period T S and period T 0 (2), which can be expressed by f Sn (19). Therefore, it is necessary to calculate the average and rms values of the currents. It is assumed that transistors S 1 and S 3 are IGBTs, and S 2 and S 4 are MOSFETs.
For the LSCVMa, we have: Conduction losses, ∆Pc, in both converters are where r k denotes the total resistance of the branch with MOSFET transistor S k (k = 2, 4), including the resistance of the transistor. ∆U Dl is the voltage drop across diode D l , ∆U Sm is the voltage drop across IGBT transistor S m , r T is the resistance of each circuit with an IGBT transistor, and I n is its rms current. It is assumed that the voltage drops across the devices remain constant in the conducting state. We assume that all the resistances and voltage drops are the same, i.e.
The efficiency of the LSCVMa converter can be calculated as follows. The resistive losses in the circuits containing IGBTs are: Taking (21)-(26) into account, the conduction losses can be presented as The turn-off switching loss is zero, due to the ZCS switching. However, there is a turn-on switching loss, associated with charging and discharging the transistors' output capacitances. The total switching power loss, ∆P sw , is where ∆W sw is the energy lost at turn-on in the transistor's resistances in a single switching cycle, and ∆P sw0 = ∆W sw ·f 0 is power loss at resonant frequency. A way of calculating these losses is presented in Reference [31]. The efficiency is (Equations (27) and (28)) Introducing normalized quantities: We can simplify the efficiency formula to the form The efficiency of the LSCVMb can be calculated with the use of the following components: where D 4 is the LSCVMb additional diode (Figure 1b). Conduction losses, ∆Pc, of LSCVMb are as follows: and the efficiency of the LSCVMb is It can be seen from (30), (31), and (34) that the impact of the voltage drops across the diodes on the efficiency depends only on the ratio of these voltage drops to the supply voltage. The impact of the losses in the resistances is more complex. They increase with rising resistances and rising power, and decrease with rising input voltage and frequency f S . Switching losses are proportional to switching frequency f S .
The relationship between the efficiency and normalized frequency f Sn = f S /f 0 for three values of r n (30): 0.016, 0.0304, and 0.040, ∆U Dn (30) = 0.008 for the LCSCVMa and the LCSCVMb is shown in Figure 12. The value of r n = 0.0304 corresponds to, e.g., U in = 50 V, P in = 200 W, L = 500 nH, C = 1.5 µF, r = 380 mΩ, and ∆U Dn is equal to 0.008 for, e.g., ∆U D = 0.40 V and U in = 50 V. The value of relative switching losses P sw0n (30) = 0.0101 (Figure 12b) is valid, e.g., for ∆W sw (28) = 11 µJ, f 0 = 183.8 kHz, and P in = 200 W. The efficiency of the LCSCVMb is slightly lower. In both cases, it increases with increasing normalized frequency, f Sn , and strongly depends on the circuit parasitic resistances. Therefore, it is important to minimize them, and use transistors with low values of R DS(on) and V CE(on) . where D4 is the LSCVMb additional diode (Figure 1b).
Conduction losses, ΔPc, of LSCVMb are as follows: and the efficiency of the LSCVMb is 3π 64 It can be seen from (30), (31), and (34) that the impact of the voltage drops across the diodes on the efficiency depends only on the ratio of these voltage drops to the supply voltage. The impact of the losses in the resistances is more complex. They increase with rising resistances and rising power, and decrease with rising input voltage and frequency fS. Switching losses are proportional to switching frequency fS.
The relationship between the efficiency and normalized frequency fSn = fS/f0 for three values of rn (30): 0.016, 0.0304, and 0.040, ΔUDn (30) = 0.008 for the LCSCVMa and the LCSCVMb is shown in Figure 12. The value of rn = 0.0304 corresponds to, e.g., Uin = 50 V, Pin = 200 W, L = 500 nH, C = 1.5 μF, r = 380 mΩ, and ΔUDn is equal to 0.008 for, e.g., ΔUD = 0.40 V and Uin = 50 V. The value of relative switching losses Psw0n (30) = 0.0101 ( Figure 12b) is valid, e.g., for ΔWsw (28) = 11 μJ, f0 = 183.8 kHz, and Pin = 200 W. The efficiency of the LCSCVMb is slightly lower. In both cases, it increases with increasing normalized frequency, fSn, and strongly depends on the circuit parasitic resistances. Therefore, it is important to minimize them, and use transistors with low values of RDS(on) and VCE(on). The efficiency can be computed in a similar way for the other switching strategies. However, the calculations will be more complex in the case of the strategies with more than 2 stages.

Experimental Verification
This chapter presents the experimental results of the LCSCVMb converter operation. All the tests were carried out under switching strategy C5. The experimental verification confirms the proper The efficiency can be computed in a similar way for the other switching strategies. However, the calculations will be more complex in the case of the strategies with more than 2 stages.

Experimental Verification
This chapter presents the experimental results of the LCSCVMb converter operation. All the tests were carried out under switching strategy C5. The experimental verification confirms the proper operation of the converter, according to its concept. The measured voltage gain was on the expected level, and all the relevant waveforms were consistent with the simulation results as well.

Experimental Setup
All the parameters of the converter used during the experimental research, as well as a photograph of the investigated converter, are collected in Table 5. The parameters of the experimental setup correspond to the simulation model, and the major difference can be found in the inductance of the planar PCB choke. The switching frequency in the experimental measurements has been adjusted to the oscillation period of the switched capacitor currents and differs from the value selected for the simulation tests. An IGBT switch was selected as S 1 in the LSCVMb, as this switch conducts the total charging current. This current can be significant, especially when the converter contains a larger number of the switching cells. In order to generate appropriate control signals, an FPGA evaluation board (INTEL DE0) was utilized. The basic clock frequency of this device was set at 200 MHz, and the time resolution of the generated signals was 5 ns. The test setup is an example design of the converter prepared for the purpose of research, to verify its concepts and feasibility. The tests were conducted with 50 V at the input; however, the voltage range as well as power and the design concept can be rescaled to the parameters of a target application. Moreover, it is important that the prospective applications of the non-isolated DC-DC converter should comply with safety standards. setup correspond to the simulation model, and the major difference can be found in the inductance of the planar PCB choke. The switching frequency in the experimental measurements has been adjusted to the oscillation period of the switched capacitor currents and differs from the value selected for the simulation tests. An IGBT switch was selected as S1 in the LSCVMb, as this switch conducts the total charging current. This current can be significant, especially when the converter contains a larger number of the switching cells. In order to generate appropriate control signals, an FPGA evaluation board (INTEL DE0) was utilized. The basic clock frequency of this device was set at 200 MHz, and the time resolution of the generated signals was 5 ns. The test setup is an example design of the converter prepared for the purpose of research, to verify its concepts and feasibility.
The tests were conducted with 50 V at the input; however, the voltage range as well as power and the design concept can be rescaled to the parameters of a target application. Moreover, it is important that the prospective applications of the non-isolated DC-DC converter should comply with safety standards.  Figure 13a, b presents the waveforms of the switching signals with the input and output current. They confirm that the converter operates correctly according to strategy C5. From the waveforms presented in Figure 13c, it follows that the converter boosts the input voltage. The measured voltage ratio is 3.65. Figure 13d, e presents the input current waveform and the voltages across the resonant capacitors. From the waveforms presented in Figure 13d, the average voltage across the capacitors can be seen. To demonstrate more clearly the magnitude of the oscillation around the average voltage value of each resonant capacitor, the voltage traces in AC coupling mode were recorded as well (Figure 13e). Figure 13f presents voltage stresses across the switches. From these results, it follows that the voltage stresses on switches are significantly below the output voltage of the converter, which is very favorable from the switching losses standpoint.  Figure 13a,b presents the waveforms of the switching signals with the input and output current. They confirm that the converter operates correctly according to strategy C5. From the waveforms presented in Figure 13c, it follows that the converter boosts the input voltage. The measured voltage ratio is 3.65. Figure 13d,e presents the input current waveform and the voltages across the resonant capacitors. From the waveforms presented in Figure 13d, the average voltage across the capacitors can be seen. To demonstrate more clearly the magnitude of the oscillation around the average voltage value of each resonant capacitor, the voltage traces in AC coupling mode were recorded as well (Figure 13e). Figure 13f presents voltage stresses across the switches. From these results, it follows that the voltage stresses on switches are significantly below the output voltage of the converter, which is very favorable from the switching losses standpoint.  During the experimental research, the basic operation concept of the investigated converter has been checked. Furthermore, the working correctness of the examined device under different output loads was verified. The tests were carried out for three output load values: 62, 146, and 290 W, focusing especially on the transistor currents and voltages. Figure 14 present the results of the conducted tests for different output load conditions. From the results, it follows that the converter operates properly in low and medium load conditions. During the experimental research, the basic operation concept of the investigated converter has been checked. Furthermore, the working correctness of the examined device under different output loads was verified. The tests were carried out for three output load values: 62, 146, and 290 W, focusing especially on the transistor currents and voltages. Figure 14 present the results of the conducted tests for different output load conditions. From the results, it follows that the converter operates properly in low and medium load conditions. Energies 2020, 13, x FOR PEER REVIEW 19 of 22 Switch S1 Switch S2 Switch S3 Figure 14.

Test Results
Waveforms of the input current as well as the currents and voltages across switches, during experimental test proceeded with different values of converter output power: (a-c) Pout = 62 W, 2A/div, 100V/div, (d-f) Pout = 146 W, 5A/div, 100V/div, (g-i) Pout = 290 W, 10A/div, 100V/div. Switching strategy C5. Figure 15 presents the results of the spectral analysis calculated for the input and output currents. The calculations have been carried out with the use of MATLAB software, based on the recorded experimental data. The data was collected by the digital oscilloscope (Tektronix MDO3104) with the sampling rate of 1 MS/s. The experimental results of the output voltage of the LCSCVMb converter and its efficiency are presented in Figure 16. The efficiency is on an acceptable level. The voltage and efficiency drop versus power is typical for such SC-based converters, and results from their resistive losses. It should be Figure 14. Waveforms of the input current as well as the currents and voltages across switches, during experimental test proceeded with different values of converter output power: (a-c) P out = 62 W, 2A/div, 100V/div, (d-f) P out = 146 W, 5A/div, 100V/div, (g-i) P out = 290 W, 10A/div, 100V/div. Switching strategy C5. Figure 15 presents the results of the spectral analysis calculated for the input and output currents. The calculations have been carried out with the use of MATLAB software, based on the recorded experimental data. The data was collected by the digital oscilloscope (Tektronix MDO3104) with the sampling rate of 1 MS/s. Switch S1 Switch S2 Switch S3 Figure 14.
Waveforms of the input current as well as the currents and voltages across switches, during experimental test proceeded with different values of converter output power: (a-c) Pout = 62 W, 2A/div, 100V/div, (d-f) Pout = 146 W, 5A/div, 100V/div, (g-i) Pout = 290 W, 10A/div, 100V/div. Switching strategy C5. Figure 15 presents the results of the spectral analysis calculated for the input and output currents. The calculations have been carried out with the use of MATLAB software, based on the recorded experimental data. The data was collected by the digital oscilloscope (Tektronix MDO3104) with the sampling rate of 1 MS/s. The experimental results of the output voltage of the LCSCVMb converter and its efficiency are presented in Figure 16. The efficiency is on an acceptable level. The voltage and efficiency drop versus power is typical for such SC-based converters, and results from their resistive losses. It should be  The experimental results of the output voltage of the LCSCVMb converter and its efficiency are presented in Figure 16. The efficiency is on an acceptable level. The voltage and efficiency drop versus power is typical for such SC-based converters, and results from their resistive losses. It should be noticed that the presented experimental setup is optimized towards the converter cost reduction. It was designed on a two-layer PCB of 35 µm. To increase the efficiency by reducing the parasitic resistance, a more expensive PCB and switches can be selected.
Energies 2020, 13, x FOR PEER REVIEW 20 of 22 noticed that the presented experimental setup is optimized towards the converter cost reduction. It was designed on a two-layer PCB of 35 μm. To increase the efficiency by reducing the parasitic resistance, a more expensive PCB and switches can be selected.

Conclusions
The presented concepts of the new topologies, as well as the comparison of parameters presented in Table 3, and charts in Figures 8-10, lead to the following conclusions: • The major idea of the proposed new converters is based on the elimination of the number of switches in a voltage multiplier (SCVM), while maintaining its proper operation. By the modification of an SCVM, the new topology concepts LCSCVMa and LCSCVMb were proposed, with a reduced number of switching cells and redesigned functions of the diodes. Depending on the technology of practical implementation, either of these converters can be more attractive than the other. • Various switching strategies are possible for the converters, which affect the parameters of operation related to switching losses and the sizing of the passive components of the converter, but also the required input and output filters.

•
The converter operates properly with a wide range of output loads.

•
From the compared results, it follows that the most effective topology, the LCSCVMb, can operate with nearly the lowest parameters of AC component in the voltages on capacitors, and the highest frequency in the input and output current. This allows for a reduction of the converter volume, especially by optimizing the input and output filters.

•
The discussed converters demonstrated an improvement in the SCVM topology, which may result in a prospective cost reduction.
Funding: This research received no external funding.

Conflicts of Interest:
The authors declare no conflict of interest.

Conclusions
The presented concepts of the new topologies, as well as the comparison of parameters presented in Table 3, and charts in Figures 8-10, lead to the following conclusions: • The major idea of the proposed new converters is based on the elimination of the number of switches in a voltage multiplier (SCVM), while maintaining its proper operation. By the modification of an SCVM, the new topology concepts LCSCVMa and LCSCVMb were proposed, with a reduced number of switching cells and redesigned functions of the diodes. Depending on the technology of practical implementation, either of these converters can be more attractive than the other. • Various switching strategies are possible for the converters, which affect the parameters of operation related to switching losses and the sizing of the passive components of the converter, but also the required input and output filters.

•
The converter operates properly with a wide range of output loads.

•
From the compared results, it follows that the most effective topology, the LCSCVMb, can operate with nearly the lowest parameters of AC component in the voltages on capacitors, and the highest frequency in the input and output current. This allows for a reduction of the converter volume, especially by optimizing the input and output filters.

•
The discussed converters demonstrated an improvement in the SCVM topology, which may result in a prospective cost reduction.