Stability Analysis and Optimal Design for Virtual Impedance of 48 V Server Power System for Data Center Applications

: In the past literature on virtual impedance to series systems, most of the discussion focused on stability without in-depth research on the system design of the series converter and the overall output impedance. Accordingly, this study takes an open-loop resonant LLC converter series-connected closed-loop Buck converter as an example. First, the conditions required for the direct connection of the small-signal model in the series, the e ﬀ ect of feedback compensation on the input impedance of the load stage, the operating frequency, and passive components of the two-stage converter are discussed in detail—the relationship between the matching and the output impedance. Afterwards, a mathematical model is used to discuss the e ﬀ ect of adding parallel virtual impedance on the output impedance of the overall series converter and then derive an optimized virtual impedance design. Finally, an experimental platform of 48 V to 12 V and maximum wattage of 96 W are implemented. The output impedance of the series converter is measured with an impedance analyzer to verify the theoretical analysis proposed in this paper.


Introduction
The series converter architecture is used extensively in various applications to compensate for the shortcomings of single-stage converters incapable of having both high efficiency and wide voltage conversion ratio. In the data center [1], the common voltage conversion rates are 48 V to 12 V, 48 V to 6 V, 48 V to 4 V, depending on the demand of the load side and the performance of maximum efficiency to choose the most appropriate voltage conversion rate. The typical combination of series converters is generally divided into two stages. The front stage uses open-loop operation, which performs preliminary voltage regulation or pure electrical isolation. The latter stage uses closed-loop control to regulate the output voltage. The switching characteristics of the open-loop LLC converter operating at the first resonance frequency can enable the switch between zero-voltage-switching (ZVS) and zero-current-switching (ZCS), and efficiently convert 48 V to suitable intermediate voltage amplitude. The subsequent Buck converter's duty cycle can be designed to be larger, and a lower voltage power switch can be used to reduce the switch on-resistance and improve the conversion efficiency of the Buck converter. This approach maximizes the efficiency of the overall two-stage converter.
With regard to the familiar series converter combination in the recent application of point of load (POL) power supply in the data center [2], the series architecture used is roughly divided into two categories: open-loop LLC series closed-loop Buck and open-loop switching tank converter (STC) [3,4] series closed-loop Buck. This combination of STC series closed-loop Buck has the advantages of high efficiency and high-power density. However, in applications where high voltage conversion and Figure 1 shows an LLC converter with a turns ratio of one. According to the derivation of literature [14][15][16], Figure 2 shows the small-signal LLC converter model. ω s is the angular frequency of the switching frequency, and ω o is the resonance frequency of L r and C r .
Energies 2020, 13, x FOR PEER REVIEW 3 of 22 resonant tank of the previous-stage LLC converter from the perspective of stability and overall output impedance. Section 5 reviews the principle, implementation method, and design constraints of the parallel virtual impedance. Section 6 discusses the impact of virtual impedance on the output impedance of the overall converter and analyzes the best virtual impedance design criteria. Section 7 verifies the derivation's correctness by simulating and implementing the circuit according to the results derived from the sixth section. Section 8 concludes the entire article. Figure 1 shows an LLC converter with a turns ratio of one. According to the derivation of literature [14,15,16], Figure 2 shows the small-signal LLC converter model. s ω is the angular frequency of the switching frequency, and o ω is the resonance frequency of r L and r C .  Although Figure 2 contains three disturbance sources such as 2 v K , 1 v G , and d G , ˆs ω is zero given that the LLC converter operates in an open loop. When discussing the output impedance, the disturbance will only leave the disturbance of the output voltage and set the disturbance ˆg v of the input voltage to zero. Thus, when discussing the output impedance, we must only understand the three parameters of e R , e C , and e L. The equations are as follows:

Individual Review of the Small-Signal Model of LLC and Buck Converters and Discussion on the Conditions for the Direct Connection of Small-Signal Models
where eq X and eq R are Energies 2020, 13, x FOR PEER REVIEW 3 of 22 resonant tank of the previous-stage LLC converter from the perspective of stability and overall output impedance. Section 5 reviews the principle, implementation method, and design constraints of the parallel virtual impedance. Section 6 discusses the impact of virtual impedance on the output impedance of the overall converter and analyzes the best virtual impedance design criteria. Section 7 verifies the derivation's correctness by simulating and implementing the circuit according to the results derived from the sixth section. Section 8 concludes the entire article. Figure 1 shows an LLC converter with a turns ratio of one. According to the derivation of literature [14,15,16], Figure 2 shows the small-signal LLC converter model. s ω is the angular frequency of the switching frequency, and o ω is the resonance frequency of r L and r C .  Although Figure 2 contains three disturbance sources such as 2 v K , 1 v G , and d G , ˆs ω is zero given that the LLC converter operates in an open loop. When discussing the output impedance, the disturbance will only leave the disturbance of the output voltage and set the disturbance ˆg v of the input voltage to zero. Thus, when discussing the output impedance, we must only understand the three parameters of e R , e C , and e L. The equations are as follows:

Individual Review of the Small-Signal Model of LLC and Buck Converters and Discussion on the Conditions for the Direct Connection of Small-Signal Models
where eq X and eq R are Although Figure 2 contains three disturbance sources such as K v2 , G v1 , and G d ,ω s is zero given that the LLC converter operates in an open loop. When discussing the output impedance, the disturbance will only leave the disturbance of the output voltage and set the disturbancev g of the input voltage to zero. Thus, when discussing the output impedance, we must only understand the three parameters of R e , C e , and L e . The equations are as follows: where X eq and R eq are Energies 2020, 13, 5253 4 of 21 When the switching frequency of the designed LLC converter is equal to the resonant frequency, X eq can be obtained as infinity according to Equation (4), R e can be obtained as zero according to Equation (1), and C e can be obtained as infinity according to Equation (2); and according to Equation (3) available L e is twice of L r . Then, through the conversion between the dependent voltage source and current source in Figure 2, the output impedance model of the LLC converter can be equivalent to the impedance of π 2 4 L r in parallel with the output capacitor C f and the load resistance R L as shown in Figure 3.
When the switching frequency of the designed LLC converter is equal to the resonant frequency, eq X can be obtained as infinity according to Equation (4), e R can be obtained as zero according to Equation (1), and e C can be obtained as infinity according to Equation (2); and according to Equation, (3) available e L is twice of r L. Then, through the conversion between the dependent voltage source and current source in Figure 2, the output impedance model of the LLC converter can be equivalent to the impedance of in parallel with the output capacitor f C and the load resistance L R as shown in Figure 3.  Figure 4 illustrates the Buck converter's small-signal model, and its small-signal modeling method is built using the switch state averaging method [17]. The equivalent switching small-signal model is established by averaging the switching states. With the Buck converter's LC filter (LO, CO and rCo), the small-signal model of the Buck converter can be established. However, when discussing the small-signal model of a single converter individually, the input voltage source is an ideal constant voltage source. Therefore, considering the significant changes in the input voltage during the state's derivation variables of each component is unnecessary. In the actual series system, considering that the post-stage converter's input voltage is no longer an ideal constant voltage source, the small-signal model of the entire machine in the series system should be re-modeled by the state-space averaging method. In practical applications, multi-level converters may use different control mechanisms for individual control, such as the frequency conversion control commonly used in LLC converters and Buck converters' pulse-width-modulation (PWM) control. Using different control modes will make it difficult for the entire system to be modeled using the state-space averaging method. Thus, when analyzing the small-signal model of the system in series, most of the individual small-signal models are directly connected in series for analysis.   Figure 4 illustrates the Buck converter's small-signal model, and its small-signal modeling method is built using the switch state averaging method [17]. The equivalent switching small-signal model is established by averaging the switching states. With the Buck converter's LC filter (L O , C O and r Co ), the small-signal model of the Buck converter can be established.
When the switching frequency of the designed LLC converter is equal to the resonant frequency, eq X can be obtained as infinity according to Equation (4), e R can be obtained as zero according to Equation (1), and e C can be obtained as infinity according to Equation (2); and according to Equation, (3) available e L is twice of r L. Then, through the conversion between the dependent voltage source and current source in Figure 2, the output impedance model of the LLC converter can be equivalent to the impedance of in parallel with the output capacitor f C and the load resistance L R as shown in Figure 3.  Figure 4 illustrates the Buck converter's small-signal model, and its small-signal modeling method is built using the switch state averaging method [17]. The equivalent switching small-signal model is established by averaging the switching states. With the Buck converter's LC filter (LO, CO and rCo), the small-signal model of the Buck converter can be established. However, when discussing the small-signal model of a single converter individually, the input voltage source is an ideal constant voltage source. Therefore, considering the significant changes in the input voltage during the state's derivation variables of each component is unnecessary. In the actual series system, considering that the post-stage converter's input voltage is no longer an ideal constant voltage source, the small-signal model of the entire machine in the series system should be re-modeled by the state-space averaging method. In practical applications, multi-level converters may use different control mechanisms for individual control, such as the frequency conversion control commonly used in LLC converters and Buck converters' pulse-width-modulation (PWM) control. Using different control modes will make it difficult for the entire system to be modeled using the state-space averaging method. Thus, when analyzing the small-signal model of the system in series, most of the individual small-signal models are directly connected in series for analysis.  However, when discussing the small-signal model of a single converter individually, the input voltage source is an ideal constant voltage source. Therefore, considering the significant changes in the input voltage during the state's derivation variables of each component is unnecessary. In the actual series system, considering that the post-stage converter's input voltage is no longer an ideal constant voltage source, the small-signal model of the entire machine in the series system should be re-modeled by the state-space averaging method. In practical applications, multi-level converters may use different control mechanisms for individual control, such as the frequency conversion control commonly used in LLC converters and Buck converters' pulse-width-modulation (PWM) control. Using different control modes will make it difficult for the entire system to be modeled using the state-space averaging method. Thus, when analyzing the small-signal model of the system in series, most of the individual small-signal models are directly connected in series for analysis.  However, the direct series approximation method must pay attention to the voltage disturbance value on the previous stage's output capacitor. Under the general design, the capacitor's voltage ripple value comes from the parasitic series resistance (ESR) of the selected capacitor. Therefore, the more significant the ESR of the intermediate stage capacitor, the more significant the error of small signal model directly connected in series. Figure 6 is a Bode plot of the open-loop Buck converter's output impedance with an LC filter in series with different rcf. The remaining circuit parameters are D = 0.5, Lo = 33 μH, Co = 2.2 mF, rC o = 10 mΩ, Cf = 100 μF, Lf = 1 mH, rLf = 100 mΩ, RL = 3 Ω. We can verify from the results of Figure 6a,b that when the rcf is large, the error between the small-signal model and the actual system will be significant. Therefore, in the design, the capacitor with smaller ESR is used as much as possible. Apart from increasing the overall converter efficiency, it also helps simplify the analysis of small signals.

Relation between Compensation Design and Input Impedance in Series System
The cascade system's d -to-ˆo v transfer function d v c a s G can be derived from the cascade smallsignal model in Figure 5. When designing the post-stage Buck compensator, d v c a s G must be designed to meet the loop gain's stability. In this paper, the symbol v C is used to indicate the compensator's transfer function.
The output and input impedance of the front-to-back converters in the series system will affect the overall cascade architecture's stability. Therefore, the analysis separates the LC filter of the previous stage from the Buck converter of the latter stage and discusses the input impedance characteristics of the Buck converter of the latter stage in this section. Figure 7 shows a control block diagram of a simple post-stage Buck converter, which adopts a voltage mode control method for closed-loop control. However, the direct series approximation method must pay attention to the voltage disturbance value on the previous stage's output capacitor. Under the general design, the capacitor's voltage ripple value comes from the parasitic series resistance (ESR) of the selected capacitor. Therefore, the more significant the ESR of the intermediate stage capacitor, the more significant the error of small signal model directly connected in series. Figure 6 is a Bode plot of the open-loop Buck converter's output impedance with an LC filter in series with different r cf . The remaining circuit parameters are D = 0.5, L o = 33 µH, C o = 2.2 mF, r C o = 10 mΩ, C f = 100 µF, L f = 1 mH, r Lf = 100 mΩ, R L = 3 Ω. We can verify from the results of Figure 6a,b that when the r cf is large, the error between the small-signal model and the actual system will be significant. Therefore, in the design, the capacitor with smaller ESR is used as much as possible. Apart from increasing the overall converter efficiency, it also helps simplify the analysis of small signals. However, the direct series approximation method must pay attention to the voltage disturbance value on the previous stage's output capacitor. Under the general design, the capacitor's voltage ripple value comes from the parasitic series resistance (ESR) of the selected capacitor. Therefore, the more significant the ESR of the intermediate stage capacitor, the more significant the error of small signal model directly connected in series. Figure 6 is a Bode plot of the open-loop Buck converter's output impedance with an LC filter in series with different rcf. The remaining circuit parameters are D = 0.5, Lo = 33 μH, Co = 2.2 mF, rC o = 10 mΩ, Cf = 100 μF, Lf = 1 mH, rLf = 100 mΩ, RL = 3 Ω. We can verify from the results of Figure 6a,b that when the rcf is large, the error between the small-signal model and the actual system will be significant. Therefore, in the design, the capacitor with smaller ESR is used as much as possible. Apart from increasing the overall converter efficiency, it also helps simplify the analysis of small signals.

Relation between Compensation Design and Input Impedance in Series System
The cascade system's d -to-ˆo v transfer function d v c a s G can be derived from the cascade smallsignal model in Figure 5. When designing the post-stage Buck compensator, d v c a s G must be designed to meet the loop gain's stability. In this paper, the symbol v C is used to indicate the compensator's transfer function.
The output and input impedance of the front-to-back converters in the series system will affect the overall cascade architecture's stability. Therefore, the analysis separates the LC filter of the previous stage from the Buck converter of the latter stage and discusses the input impedance characteristics of the Buck converter of the latter stage in this section. Figure 7 shows a control block diagram of a simple post-stage Buck converter, which adopts a voltage mode control method for closed-loop control.

Relation between Compensation Design and Input Impedance in Series System
The cascade system'sd-to-v o transfer function G dvcas can be derived from the cascade small-signal model in Figure 5. When designing the post-stage Buck compensator, G dvcas must be designed to meet the loop gain's stability. In this paper, the symbol C v is used to indicate the compensator's transfer function.
The output and input impedance of the front-to-back converters in the series system will affect the overall cascade architecture's stability. Therefore, the analysis separates the LC filter of the previous stage from the Buck converter of the latter stage and discusses the input impedance characteristics of the Buck converter of the latter stage in this section. Figure 7 shows a control block diagram of a simple post-stage Buck converter, which adopts a voltage mode control method for closed-loop control.
Energies 2020, 13, 5253 6 of 21 Energies 2020, 13, x FOR PEER REVIEW 6 of 22 Kd in Figure 7 is the feedback voltage division ratio, Fm is the modulation gain from sawtooth to PWM, and the remaining system transfer functions can be derived from Figure 4 as follows: To obtain the closed-loop input impedance ZinCL, the control block diagram in Figure 7 shows the following: The relationship between d and ˆi n v can be summarized as (11) as where v T is the loop gain: Substituting Equation (12) into Equation (10) can derive the closed-loop output impedance ZinCL as  Figure 7 is the feedback voltage division ratio, F m is the modulation gain from sawtooth to PWM, and the remaining system transfer functions can be derived from Figure 4 as follows: To obtain the closed-loop input impedance Z inCL , the control block diagram in Figure 7 shows the following:î The relationship betweend andv in can be summarized as (11) aŝ where T v is the loop gain: Substituting Equation (12) into Equation (10) can derive the closed-loop output impedance Z inCL as Energies 2020, 13, 5253 7 of 21 Substituting Equations (6)-(9) into Equation (14), we can further obtain the following: Observation Equation (15) shows that if we want the closed-loop input impedance to be a fixed value −R L /D 2 , Equation (15) must meet two conditions. Condition one: |T v | 1. Condition two: Figure 8 is a Bode plot of the closed-loop input impedance at different T v , the remaining circuit parameters are D = 0.5, L o = 33 µH, C o = 2.2 mF, r Co = 10 mΩ, C f = 100 µF, L f = 1 mH, r Lf = 100 mΩ, R L = 3 Ω. As shown in Figure 8, under the design using T v1 closed-loop gain, given that the |T v | |1/Z inOP | is not satisfied within the closed-loop bandwidth, the input impedance characteristic within the closed-loop bandwidth is not a fixed negative resistance value. In the design using T v2 closed-loop gain, it can be regarded as a fixed impedance value within the closed-loop bandwidth because the condition of |T v | |1/Z inOP | is satisfied. Therefore, in the compensator's design, we must pay special attention to whether condition two is met, and it cannot be directly assumed that Z inCL is a fixed value within the closed-loop bandwidth.
Substituting Equations (6)-(9) into Equation (14), we can further obtain the following: Observation Equation (15) shows that if we want the closed-loop input impedance to be a fixed value ( , Equation (15) must meet two conditions. Condition one: Figure 8 is a Bode plot of the closed-loop input impedance at different Tv, the remaining circuit parameters are D = 0.5, Lo = 33 μH, Co = 2.2 mF, rCo = 10 mΩ, Cf = 100 μF, Lf = 1 mH, rLf = 100 mΩ, RL = 3 Ω. As shown in Figure 8, under the design using Tv1 closed-loop gain, given that the is not satisfied within the closed-loop bandwidth, the input impedance characteristic within the closed-loop bandwidth is not a fixed negative resistance value. In the design using Tv2 closed-loop gain, it can be regarded as a fixed impedance value within the closed-loop bandwidth because the condition of is satisfied. Therefore, in the compensator's design, we must pay special attention to whether condition two is met, and it cannot be directly assumed that ZinCL is a fixed value within the closed-loop bandwidth.

Middlebrook Stability Criterion and Corresponding LLC Design Choices
Middlebrook stability criterion must discuss the output and input impedance of the front and rear converters. Figure 9 is a schematic diagram of a typical cascade system utilized to define each symbol. Among them, ZoS is the output impedance of the previous stage, and ZiL is the input impedance of the latter stage.

Middlebrook Stability Criterion and Corresponding LLC Design Choices
Middlebrook stability criterion must discuss the output and input impedance of the front and rear converters. Figure 9 is a schematic diagram of a typical cascade system utilized to define each symbol. Among them, Z oS is the output impedance of the previous stage, and Z iL is the input impedance of the latter stage.  Figure 9. Schematic diagram of a typical series system.
To discuss the stability of the serial system, Figure 10 presents a two-port network diagram based on the serial system of Figure 9. To discuss the stability of the serial system, Figure 10 presents a two-port network diagram based on the serial system of Figure 9. To discuss the stability of the serial system, Figure 10 presents a two-port network diagram based on the serial system of Figure 9. us vˆo v bus i Figure 10. Dual-port network diagram of the series system.

G vS (s) 1/Z iS (s) G iS (s) G iS (s)ˆi
Four system transfer functions can be derived from Figure 10: where As can be seen from Equations (16)-(20), even if the previous stage's converters and the later stage are stable when the ratio Tm between the output of the front-and post-stage converter's input impedance is unstable, the overall series system will remain unstable. This phenomenon is Middlebrook's stable criterion. Figure 11 is a Bode diagram of the output impedance of the front stage and the rear stage's output impedance in a typical unstable series system. Its circuit characteristics can be regarded as an LC filter in the front stage and a power converter with a constant power load in the rear stage. The symbol ZoSP is the peak value of the output impedance of the previous stage. According to the derivation in Section 3, the closed-loop input impedance of the fixed power load's power converter is a specific value. Moreover, the particular value can be derived according to the following steps.
Assuming that the converter efficiency is 100%, the output power Po is Figure 10. Dual-port network diagram of the series system.
Four system transfer functions can be derived from Figure 10: where As can be seen from Equations (16)-(20), even if the previous stage's converters and the later stage are stable when the ratio T m between the output of the front-and post-stage converter's input impedance is unstable, the overall series system will remain unstable. This phenomenon is Middlebrook's stable criterion. Figure 11 is a Bode diagram of the output impedance of the front stage and the rear stage's output impedance in a typical unstable series system. Its circuit characteristics can be regarded as an LC filter in the front stage and a power converter with a constant power load in the rear stage. The symbol Z oSP is the peak value of the output impedance of the previous stage. According to the derivation in Section 3, the closed-loop input impedance of the fixed power load's power converter is a specific value. Moreover, the particular value can be derived according to the following steps.
Assuming that the converter efficiency is 100%, the output power P o is Under closed-loop operation, the output power is constant, and the output power is independent of the value of the input voltage. Therefore, Then, the fixed value part of the input impedance Z inConst can be derived by definition as follows, and this impedance is a negative resistance characteristic.
Energies 2020, 13, 5253 9 of 21 As can be seen from Figure 11, at frequencies f 1 and f 2 , T m (s) has insufficient phase margin. When the frequency is f sp , T m (s) has insufficient gain margin. Therefore, this series system is unstable.
(23) As can be seen from Figure 11, at frequencies f1 and f2, Tm (s) has insufficient phase margin. When the frequency is fsp, Tm (s) has insufficient gain margin. Therefore, this series system is unstable.
After understanding the Middlebrook stability criteria and the system Bode plot of Figure 11, the open-loop LLC converter's output impedance can be known as an LC parallel architecture in Section 1, which is consistent with the output impedance of the LC filter. Therefore, the same concept can explain how to design the LLC converter to stabilize the series system. Two design methods exist to stabilize the series system as shown in Figure 12. The first method is to reduce the value of ZoSP to prevent Tm (s) from having a gain of equal to 1, as shown by ZoS1 in Figure 12. However, this method must increase the LLC converter's system damping so that the system adds additional losses. The second method is to design the resonant frequency of the LLC converter far enough, far higher than the zero-crossing frequency of the latter stage constant power converter, and raise the input After understanding the Middlebrook stability criteria and the system Bode plot of Figure 11, the open-loop LLC converter's output impedance can be known as an LC parallel architecture in Section 1, which is consistent with the output impedance of the LC filter. Therefore, the same concept can explain how to design the LLC converter to stabilize the series system. Two design methods exist to stabilize the series system as shown in Figure 12. The first method is to reduce the value of Z oSP to prevent T m (s) from having a gain of equal to 1, as shown by Z oS1 in Figure 12. However, this method must increase the LLC converter's system damping so that the system adds additional losses. The second method is to design the resonant frequency of the LLC converter far enough, far higher than the zero-crossing frequency of the latter stage constant power converter, and raise the input impedance of the latter stage converter higher than the LLC output at any frequency. The impedance is shown as Z oS2 in Figure 12. However, this method will force the LLC converter's resonant frequency to be at least higher than the post-stage converter's bandwidth when the post-stage converter's system bandwidth is very high. Furthermore, the series system's overall output impedance cannot rely on closed-loop gain for sufficient attenuation. Apart from increasing the driver's driving loss, the high-frequency LLC converter will also increase the prominence of the effects of non-ideal parasitic elements on the resonant element, thereby increasing the complexity of the system as well. Therefore, in practice, other methods must be considered to solve the instability of the cascade system. impedance of the latter stage converter higher than the LLC output at any frequency. The impedance is shown as ZoS2 in Figure 12. However, this method will force the LLC converter's resonant frequency to be at least higher than the post-stage converter's bandwidth when the post-stage converter's system bandwidth is very high. Furthermore, the series system's overall output impedance cannot rely on closed-loop gain for sufficient attenuation. Apart from increasing the driver's driving loss, the high-frequency LLC converter will also increase the prominence of the effects of non-ideal parasitic elements on the resonant element, thereby increasing the complexity of the system as well. Therefore, in practice, other methods must be considered to solve the instability of the cascade system. Figure 12. Two ways to design an LLC converter to stabilize a series system.

Design and Implementation of Parallel Type Virtual Impedance
Compared with the serial-type virtual impedance, the parallel-type virtual impedance requires no additional current sensing components in manufacturing and has a lower cost, higher converter efficiency, and stable and straightforward system. Therefore, this thesis uses parallel virtual Figure 12. Two ways to design an LLC converter to stabilize a series system.

Design and Implementation of Parallel Type Virtual Impedance
Compared with the serial-type virtual impedance, the parallel-type virtual impedance requires no additional current sensing components in manufacturing and has a lower cost, higher converter efficiency, and stable and straightforward system. Therefore, this thesis uses parallel virtual impedance to perform follow-up research.
The principle of the parallel-type virtual impedance is to create virtual impedance and connect the virtual impedance parallel to the input impedance of the post-stage converter, thereby stabilizing the series system. Figure 13 illustrates its physical meaning. Z oS1 Figure 12. Two ways to design an LLC converter to stabilize a series system.

Design and Implementation of Parallel Type Virtual Impedance
Compared with the serial-type virtual impedance, the parallel-type virtual impedance requires no additional current sensing components in manufacturing and has a lower cost, higher converter efficiency, and stable and straightforward system. Therefore, this thesis uses parallel virtual impedance to perform follow-up research.
The principle of the parallel-type virtual impedance is to create virtual impedance and connect the virtual impedance parallel to the input impedance of the post-stage converter, thereby stabilizing the series system. Figure 13 illustrates its physical meaning. Figure 13. Physical meaning of the parallel type virtual impedance.

v bus Z PVI v bus
The symbol ZiLP is defined as the overall input impedance value after the parallel virtual impedance is added. The mathematical expression is: To stabilize the series system, the input impedance value of the subsequent stage can be changed in two ways: first, the phase of ZiLP is adjusted to provide sufficient phase margin when Tm (s) = 1; second, the gain of ZiLP is adjusted to raise the gain of ZiLP higher than ZoSP at any frequency and thus provide sufficient margin for Tm (s). Among them, the process of adjusting the phase is not as good as that of adjusting the gain to improve stability [11]. Moreover, the design and implementation of the analog circuit are susceptible to the phase shift of the analog filter. Consequently, the current study chooses to change ZiLP gain mode. The symbol Z iLP is defined as the overall input impedance value after the parallel virtual impedance is added. The mathematical expression is: To stabilize the series system, the input impedance value of the subsequent stage can be changed in two ways: first, the phase of Z iLP is adjusted to provide sufficient phase margin when T m (s) = 1; second, the gain of Z iLP is adjusted to raise the gain of Z iLP higher than Z oSP at any frequency and thus provide sufficient margin for T m (s). Among them, the process of adjusting the phase is not as good as that of adjusting the gain to improve stability [11]. Moreover, the design and implementation of the analog circuit are susceptible to the phase shift of the analog filter. Consequently, the current study chooses to change Z iLP gain mode.
Given that Z iLP can be higher than Z oSP under any loading conditions to ensure the series system's stability, the design method of designing Z PVI can be divided into two states from no-load and full-load as the starting point for the design. Figure 14 presents a design example.
Energies 2020, 13, x FOR PEER REVIEW 11 of 22 Given that ZiLP can be higher than ZoSP under any loading conditions to ensure the series system's stability, the design method of designing ZPVI can be divided into two states from no-load and fullload as the starting point for the design. Figure 14 presents a design example.  Figure 14 is a curve of |ZiLP| designed with the output no-load as the starting point. When the post-stage converter is no-load, the overall input impedance of the post-stage contains only ZPVIOP. Thus, the design of ZPVIOP must only consider the peak value of ZoSP and the required gain margin GM. The design formula of ZPVIOP is as follows:

ZiLP (ZPVIOP) in
Observing the curve ZiLP (ZPVIOP), if one wishes to meet the situation where one can have more Z iLP (Z PVIOP ) in Figure 14 is a curve of |Z iLP | designed with the output no-load as the starting point. When the post-stage converter is no-load, the overall input impedance of the post-stage contains Energies 2020, 13, 5253 11 of 21 only Z PVIOP . Thus, the design of Z PVIOP must only consider the peak value of Z oSP and the required gain margin GM. The design formula of Z PVIOP is as follows: Observing the curve Z iLP (Z PVIOP ), if one wishes to meet the situation where one can have more than gain margin GM under any load, the maximum output wattage of the converter P oLM will be limited. If the output load is higher than P oLM , the gain margin of Z iLP from Z oSP will be insufficient. Therefore, the converter must consider the full load and no-load conditions. Z iLP has sufficient gain margin GM, and Z iLP is equal to |Z PVIOP | at the maximum output wattage P oLM . To satisfy this condition, under the maximum output wattage P oLM , the input impedance Z iL of the original converter must be equal to −0.5Z PVIOP to achieve the following: Z iLP = Z PVIOP || − 0.5Z PVIOP = −Z PIOP . Then, the maximum output wattage P oLM can be derived: Therefore, the full load wattage P oFL of the designed converter must be less than P oLM . However, the Z PVI design method is based on the fully loaded P oFL , and the result is shown as the curve Z iLP (Z PVIFL ) in Figure 14. To make the overall input impedance equal to |Z PVIOP | under full-load P oFL and any load below full-load P oFL can have more than GM gain margin, the right half of the curve Z iLP (Z PVIOP ) must be selected. The two lines of curve Z iLP and level |Z PVIOP | must intersect when the load point is P oFL ; at this time, Z iLP = −Z PVIOP . The design formula of Z PVIFL is as follows: From Formulas (25) and (27), we know that within the following range of Z PVI design, the system can be stabilized under any load. Additionally, the gain margins at different load points are different, but the gain margin is higher than GM: After understanding the design criteria and scope of Z PVI , the control block diagram of Z PVI implementation is reviewed in [11] as shown in Figure 15. After understanding the design criteria and scope of ZPVI, the control block diagram of ZPVI implementation is reviewed in [11] as shown in Figure 15. In Figure 15, Cv is the compensator's transfer function, Fm is the modulation gain of the sawtooth wave, and Kd is the feedback voltage division gain. As can be seen from the control block diagram, if creating virtual impedance is desired through the feedforward method in the control block, the control blocks must meet the following: where Figure 15. Control block diagram of the realization of parallel virtual impedance.
In Figure 15, C v is the compensator's transfer function, F m is the modulation gain of the sawtooth wave, and K d is the feedback voltage division gain. As can be seen from the control block diagram, if Energies 2020, 13, 5253 12 of 21 creating virtual impedance is desired through the feedforward method in the control block, the control blocks must meet the following: where After finishing Formula (29), the transfer function of G PVI is as follows: In practice, G PVI can be simplified conditionally. When T v 1, G PVI can be simplified to G PVIappr , facilitating the implementation of the circuit: (32) Notably, this control block is derived using the small-signal model of a simple post-converter. Taking the Buck converter as an example, referring to the Buck small-signal model of Figure 4, the input voltage symbolv in is changed tov bus , and the input currentî in is changed toî bus . Then, we can obtain the following: (34)

Effect of Virtual Impedance on the Overall Converter's Output Impedance and the Optimal Design of Virtual Impedance
From the explanation in Section 5 and Equation (28), it can be seen that the setting of Z PVI is not a fixed value, but can be set within a range. When Z PVIOP ≤ |Z PVI | ≤ Z PVIFL , the converter can make the system stable without exceeding the full load. Therefore, this section discusses how much Z PVI parameters should be set to have the best overall output impedance performance after the power stage's circuit parameters are determined.
This section first discusses the effect of the converter's overall output impedance after adding the virtual impedance. Afterwards, the optimal design of the required impedance is explained mathematically.
As can be seen from the deduction of Section 5, the control block constructs Z PVI . Therefore, when discussing the overall converter's output impedance, the small-signal model of the converter cannot be directly connected in parallel with the physical resistance, which must be re-derived by the control block. When discussing the output impedance in a closed loop, the input voltage disturbancev in is set to zero, and the disturbance currentî o is fed from the output to observe its disturbance to the output voltagev o . Given that the duty cycle disturbanced in the closed-loop system is controlled by the output voltagev o and the interstage voltagev bus , the duty cycle disturbanced is not zero when discussing the closed-loop output impedance. Figure 16 illustrates a small signal model referring to Figure 5, setting the input voltage disturbancev in to zero and discussing the closed-loop output impedance's small-signal model. set to zero, and the disturbance current ˆo i is fed from the output to observe its disturbance to the output voltageˆo v . Given that the duty cycle disturbance d in the closed-loop system is controlled by the output voltage ˆo v and the interstage voltage ˆb us v , the duty cycle disturbance d is not zero when discussing the closed-loop output impedance. Figure 16 illustrates a small signal model referring to Figure 5, setting the input voltage disturbance ˆi n v to zero and discussing the closed-loop output impedance's small-signal model.  Figure 17 presents a block diagram of calculating individual transfer functions regarding Figure  16; a controller and a feedforward term GPVI are added, and a control block diagram with virtual impedance is drawn.   Figure 16; a controller and a feedforward term G PVI are added, and a control block diagram with virtual impedance is drawn.  The transfer function of individual control blocks can be derived from Figure 16 as follows: (38) From Figure 17, the nodal equation can be written as follows: . (42) The output impedance of the closed loop without adding the virtual impedance Z ocasCL is where Figure 18 is a design example to compare the Bode plot of |Z ocasWpvi | and |Z ocsCL |. Tables 1 and 2 in Section 7 show the circuit parameter values nd compensator design parameters. This section uses the G PVI parameters of the exact solution described according to Equation (32). The G PVIappr parameters listed in Table 2 are simplified versions, which are easily implemented in analog circuits. (42) The output impedance of the closed loop without adding the virtual impedance ocasCL where vcas D v m dvocas (44) Figure 18 is a design example to compare the Bode plot of |ZocasWpvi| and |ZocsCL|. Tables 1 and 2 in Section 7 show the circuit parameter values nd compensator design parameters. This section uses the GPVI parameters of the exact solution described according to Equation (32). The GPVIappr parameters listed in Table 2 are simplified versions, which are easily implemented in analog circuits. As can be seen from Figure 18, in the performance of the overall output impedance in the lowfrequency band, the output impedance of the system without adding the virtual impedance will perform better. To explore this phenomenon, we compare Equation As can be seen from Figure 18, in the performance of the overall output impedance in the low-frequency band, the output impedance of the system without adding the virtual impedance will perform better. To explore this phenomenon, we compare Equation (40) with Equation (41).
First, = the denominators of Z ocasWpvi and Z ocasCL are compared. According to Den(Z ocasWpvi ), the denominator of Z ocasWpvi , when individual gain products G dvbus G PVI C v F m and K D C v F m G dvocas /G dvbus G PVI C v F m are much greater than 1, Den(Z ocasWpvi ) can be approximated as follows: Energies 2020, 13, 5253

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Substituting G PVI of Formula (32) into Formula (45), Den appr (Z ocasWpvi ) can be obtained: Substituting G PVI of Formula (32) into Formula (45), Den appr (Z ocasWpvi ) can be obtained: Given that Z 1 can be regarded as approximately r Lf in the low-frequency band, Den appr (Z ocasWpvi ) can be regarded as a limited value in the low-frequency band. To reduce the steady-state error, the loop gain T vcas will design extremely high gain in the low-frequency band. Therefore, it can be seen from Equation (43) that Den(Z ocasCL ) also has exceptionally high gain in the low-frequency band and is much larger than that of Den appr (Z ocasWpvi ). Figure 19 presents a Bode diagram of |Den(Z ocasWpvi )|, |Den appr (Z ocasWpvi )| and|Den(Z ocasCL )|. As can be seen from Figure 19, in the low frequency band, |Den(Z ocasCL )| is greater than |Den(Z ocasWpvi )|. In the low frequency band, |Den(Z ocasWpvi )| and |Den appr (Z ocasWpvi )| coincide with each other.
Substituting GPVI of Formula (32) into Formula (45), Denappr (ZocasWpvi) can be obtained: Given that Z1 can be regarded as approximately rLf in the low-frequency band, Denappr(ZocasWpvi) can be regarded as a limited value in the low-frequency band. To reduce the steady-state error, the loop gain Tvcas will design extremely high gain in the low-frequency band. Therefore, it can be seen from Equation (43) that Den(ZocasCL) also has exceptionally high gain in the low-frequency band and is much larger than that of Denappr (ZocasWpvi). Figure 19 presents a Bode diagram of |Den(ZocasWpvi)|, |Denappr(ZocasWpvi)| and|Den(ZocasCL)|. As can be seen from Figure 19, in the low frequency band, |Den(ZocasCL)| is greater than |Den(ZocasWpvi)|. In the low frequency band, |Den(ZocasWpvi)| and |Denappr(ZocasWpvi)| coincide with each other. We now compare the numerator terms of ZocasWpvi and ZocasCL. Figure 20 is a Bode plot of |Num(ZocasWpvi)| and |Num(ZosCasCL)|. By observing Figure 20, |Num(ZocasWpvi)| can be seen as higher than |Num(ZosCasCL)| in the low-frequency band. Then, we compare the numerator terms of ZocasWpvi and ZocasCL. Figure 20 presents a Bode plot of |Num(ZocasWpvi)| and |Num(ZosCasCL)|. By observing Figure  20, |Num(ZocasWpvi)| can be seen as higher than |Num(ZosCasCL)| in the low-frequency band.
To explain this phenomenon, the performance of Num(ZosCasCL) is first observed at low frequencies: We now compare the numerator terms of Z ocasWpvi and Z ocasCL . Figure 20 is a Bode plot of |Num(Z ocasWpvi )| and |Num(Z osCasCL )|. By observing Figure 20, |Num(Z ocasWpvi )| can be seen as higher than |Num(Z osCasCL )| in the low-frequency band. Then, we compare the numerator terms of Z ocasWpvi and Z ocasCL . Figure 20 presents a Bode plot of |Num(Z ocasWpvi )| and |Num(Z osCasCL )|. By observing Figure 20, |Num(Z ocasWpvi )| can be seen as higher than |Num(Z osCasCL )| in the low-frequency band. To explain this phenomenon, the performance of Num(Z osCasCL ) is first observed at low frequencies: (48) Second, Num(Z ocasWpvi ) is observed. Similarly, when G dvbus G PVI C v F m is much higher than 1, Formula (48) is approximated as follows: Equations (34)-(37) are substituted into Equation (49), and the performance of Num appr (Z ocasWpvi ) at low frequencies is discussed as follows: (50) As can be seen from Equations (48) and (50), in the case of low-frequency response and D 2 r Lf is much smaller than R L , |Num(Z ocasWpvi )| is higher than |Num(Z osCasCL )| in the low-frequency band. Figure 20 also points out that |Num appr (Z ocasWpvi )| and |Num(Z osWpvi )| coincide in the low-frequency band.
By deriving the numerator and denominator terms of Z ocasWpvi and Z ocasCL , the Num(Z ocasWpvi ) of the denominator in the low-frequency band is smaller than Num(Z ocasCL ), and the numerator Den(Z ocasWpvi ) in the low-frequency band is higher than Den(Z ocasCL ). Therefore, in the overall output impedance performance of the low-frequency band, |Z ocasWpvi | is higher than |Z ocasCL |. Although the system's stability is improved after adding the virtual impedance, it will sacrifice the transient response of the output.
Reviewing Equation (47), we can find that the gain of Den appr (Z ocasWpvi ) is proportional to Z PVI . That is, the larger the Z PVI , the smaller the |Z ocasWpvi | . With Figure 14 and Equation (29), we can see that to minimize |Z ocasWpvi |, the design of Z PVI should choose Z PVI = Z PVIFL . Figure  After adding the virtual impedance, the output impedance of the overall converter will increase. Therefore, in practice, the GPVI feed-forward term will be added to a band-pass filter. Apart from adding the isolated DC term to the control loop, the ZPVI is only involved in the system in the frequency band that must increase the input impedance of the subsequent stage, thereby reducing the impact on the overall output impedance. After adding the virtual impedance, the output impedance of the overall converter will increase. Therefore, in practice, the G PVI feed-forward term will be added to a band-pass filter. Apart from adding the isolated DC term to the control loop, the Z PVI is only involved in the system in the frequency band that must increase the input impedance of the subsequent stage, thereby reducing the impact on the overall output impedance.

Simulation and Implementation Results
When the series system of the LLC series Buck is unstable, the stress on the resonant element will largely increase and the element will become damaged. Therefore, the verification uses the equivalent LC filter series Buck converter as the experimental platform. Therefore, the LC filter's input voltage V in is set to 48 V to simulate the output voltage of the LLC converter, and the impedance of the resonant tank is converted according to the turns ratio of the transformer (400/48).
The design example used in this paper is to observe and verify the stability of the system and the overall output impedance, both of which are affected by the addition of virtual impedance. The parameter design of the circuit is designed based on the limitation of the measuring instrument. Since the electronic load Chroma 63204 can only generate the disturbance current up to 20 kHz, to observe the change of the overall output impedance before and after adding virtual independence, the resonance frequency of the source equivalent LC filter is designed to be about 500 Hz. The gain of Z oS seen by the post-stage stage is slightly larger than the Z inCL seen by the second-stage converter under full load operation; this makes the series system unstable without adding virtual impedance. So when the converter's full-load output wattage is set to 96 W and the Bus voltage is 48 V, the component parameters of the post-stage LC filter can be designed. The closed-loop crossover frequency of the final converter is designed to be 10 kHz. Under the general design concept, the crossover frequency is about 1/6 to 1/10 times the switching frequency, so the Buck converter's switching frequency is set to 100 kHz. In order to make the Z inCL before the crossover frequency a fixed value, the resonance frequency of the LC filter of the Buck converter is about 600Hz, away from the closed-loop crossover frequency, and a lower peak value of |1/Z inOP | is designed. Such circuit design parameters make it easier to design the compensator so that the closed-loop gain T v has enough gain to meet |T v | |1/Z inOP |. Table 1 shows the parameter value of the series circuit, and Table 2 presents the transfer function of the feedback voltage divider, compensator, feedforward term and band pass filter, and other control terms. Figure 22 illustrates a system wiring diagram to understand the connection relationship of each transfer function.   Figure 22. System wiring diagram. Figure 23 shows the results of design and simulation cross-validation to prove that the mathematical model is consistent with the circuit simulation results. As can be seen from Figure 23, the maximum value of |ZoSP| is approximately 20.25 dB. To stabilize the system under no load, ZPVI = ZPVIOP is designed to be 42 Ω, thereby generating a gain margin of approximately 6 dB in the system. According to Equation (26), the maximum output wattage PoLM is 109.7 W. The designed full load wattage is 96 W; then, the load resistance of the full load can be reversed to 1.5 Ω. Figure 23 shows the calculation results obtained from the parameters in Tables 1 and 2. At this time, for the ZPVI** parameter in GPVI, ZPVI** = ZPVIOP is selected. Before the system adds the virtual impedance, the phase  Figure 23 shows the results of design and simulation cross-validation to prove that the mathematical model is consistent with the circuit simulation results. As can be seen from Figure 23, the maximum value of |Z oSP | is approximately 20.25 dB. To stabilize the system under no load, Z PVI = Z PVIOP is designed to be 42 Ω, thereby generating a gain margin of approximately 6 dB in the system. According to Equation (26), the maximum output wattage P oLM is 109.7 W. The designed full load wattage is 96 W; then, the load resistance of the full load can be reversed to 1.5 Ω. Figure 23 shows the calculation results obtained from the parameters in Tables 1 and 2. At this time, for the Z PVI** parameter in G PVI , Z PVI** = Z PVIOP is selected. Before the system adds the virtual impedance, the phase margin is approximately 1 dB, and the system is in an unstable state. After adding the virtual impedance to the system, the input impedance of the subsequent stage can be increased in the frequency range of 15.9 Hz to 5.3 kHz, and the gain margin is increased by approximately 6dB, which stabilizes the series system. margin is approximately 1 dB, and the system is in an unstable state. After adding the virtual impedance to the system, the input impedance of the subsequent stage can be increased in the frequency range of 15.9 Hz to 5.3 kHz, and the gain margin is increased by approximately 6dB, which stabilizes the series system.  Figure 23. Bode plot of input impedance comparison before and after adding virtual impedance.
After analyzing the frequency domain response, Figure 24 presents the time domain verification results. Figure 24a shows the simulation result. The virtual impedance is not added before t = 50 ms, and the system shows oscillation. After t = 50 ms, the virtual impedance feedforward loop is added to the system, and the system is stabilized. Figure 24b shows the test result of the physical circuit. Moreover, before the virtual impedance feedforward is added, the system shows oscillation. After After analyzing the frequency domain response, Figure 24 presents the time domain verification results. Figure 24a shows the simulation result. The virtual impedance is not added before t = 50 ms, and the system shows oscillation. After t = 50 ms, the virtual impedance feedforward loop is added to the system, and the system is stabilized. Figure 24b shows the test result of the physical circuit. Moreover, before the virtual impedance feedforward is added, the system shows oscillation. After putting in the virtual impedance feedforward loop, the system returns to stability. In Figure 24b, the voltage disturbance amplitude when v BUS and v O are unstable is smaller than the voltage amplitude under ideal conditions. The reason is that the voltage source used in the experiment is not an ideal voltage source. It only has a unidirectional power transmission function instead of bidirectional power transmission and contains its equivalent series impedance. Therefore, the simulation results using an ideal voltage source are different from the actual experimental results. However, the experimental results can still highlight adding virtual impedance to stabilize the series system. After analyzing the frequency domain response, Figure 24 presents the time domain verification results. Figure 24a shows the simulation result. The virtual impedance is not added before t = 50 ms, and the system shows oscillation. After t = 50 ms, the virtual impedance feedforward loop is added to the system, and the system is stabilized. Figure 24b shows the test result of the physical circuit. Moreover, before the virtual impedance feedforward is added, the system shows oscillation. After putting in the virtual impedance feedforward loop, the system returns to stability. In Figure 24b, the voltage disturbance amplitude when vBUS and vO are unstable is smaller than the voltage amplitude under ideal conditions. The reason is that the voltage source used in the experiment is not an ideal voltage source. It only has a unidirectional power transmission function instead of bidirectional power transmission and contains its equivalent series impedance. Therefore, the simulation results using an ideal voltage source are different from the actual experimental results. However, the experimental results can still highlight adding virtual impedance to stabilize the series system. To measure the effect of different ZPVI on the overall output impedance, we switch the band-pass filter to a high-pass filter to increase the output impedance's observable range. It can be inferred from Equation (28), and ZPVI is designed with the load resistance of RL = 1.5 Ω, then, ZPVI = ZPVIFL = 56 Ω.
ZPVI is set to ZPVI = ZPVIOP = 42 Ω and ZPVI = ZPVIFL= 56 Ω, respectively. Two feedforward designs are placed into the system. The input voltage source is Chroma 62150H-1000. The spectrum analyzer NF FRA5096 is used with the electronic load Chroma 63204 to scan the overall output impedance of the To measure the effect of different Z PVI on the overall output impedance, we switch the band-pass filter to a high-pass filter to increase the output impedance's observable range. It can be inferred from Equation (28), and Z PVI is designed with the load resistance of R L = 1.5 Ω, then, Z PVI = Z PVIFL = 56 Ω.
Z PVI is set to Z PVI = Z PVIOP = 42 Ω and Z PVI = Z PVIFL = 56 Ω, respectively. Two feedforward designs are placed into the system. The input voltage source is Chroma 62150H-1000. The spectrum analyzer NF FRA5096 is used with the electronic load Chroma 63204 to scan the overall output impedance of the two different designs as shown in Figure 25. As can be seen from Figure 25, under the design of Z PVI = Z PVIFL = 56 Ω, the overall output impedance is small. The correctness of the deduction in Section 6 is verified.
Energies 2020, 13, x FOR PEER REVIEW 21 of 22 two different designs as shown in Figure 25. As can be seen from Figure 25, under the design of ZPVI = ZPVIFL = 56 Ω, the overall output impedance is small. The correctness of the deduction in Section 6 is verified. However, the actual measurement results are not entirely consistent with the results derived from the mathematical model. The reason is that the input voltage source is not an ideal voltage source. The actual instrument used as a voltage source has its own output impedance, plus the error on the measuring instrument, these two factors make the measured overall output impedance data differ from the ideal theoretical calculation result. Nonetheless, the trend of the curve is consistent with the description of this paper.

Conclusion
This thesis takes the LLC series Buck as an example circuit to study the system stability conditions of a two-stage series system and the overall series system's output impedance performance. The entire series system's small-signal model can be directly connected in series using the individual converter's small-signal model when the ESR of the output capacitor in the individual converter is relatively small. In discussing the cascade system's stability, if the input impedance of However, the actual measurement results are not entirely consistent with the results derived from the mathematical model. The reason is that the input voltage source is not an ideal voltage source. The actual instrument used as a voltage source has its own output impedance, plus the error on the measuring instrument, these two factors make the measured overall output impedance data differ from the ideal theoretical calculation result. Nonetheless, the trend of the curve is consistent with the description of this paper.

Conclusions
This thesis takes the LLC series Buck as an example circuit to study the system stability conditions of a two-stage series system and the overall series system's output impedance performance. The entire series system's small-signal model can be directly connected in series using the individual converter's small-signal model when the ESR of the output capacitor in the individual converter is relatively small. In discussing the cascade system's stability, if the input impedance of the downstream converter is to be approximated to a specific value of negative impedance, it is necessary to check whether the open-loop input impedance and closed-loop gain meet the approximate conditions. The Middlebrook criterion has described the stability conditions of the two-stage series system. Designing a two-stage converter based on this criterion may make the converter unable to achieve the best efficiency, making the converter design a compromise between stability and efficiency performance. In order to achieve a more flexible design of the converter, the control loop is adopted to add virtual impedance to improve the system stability.
Although the parallel virtual impedance can increase the system's stability, it will increase the overall output impedance. This research establishes a complete mathematical discussion of this phenomenon to understand the design limitations when applying the parallel virtual impedance and how to choose the most appropriate design to reduce the impact of the overall output impedance. As can be seen from the mathematical derivation, the design of Z PVI must meet the series system's stability gain margin requirements at any load conditions below full load wattage P oFL of the designed converter, so the design of Z PVI must meet Z PVIOP ≤ |Z PVI | ≤ Z PVIFL . Among them, set Z PVI = Z PVIFL is the best design for parallel virtual impedance to get the lowest overall output impedance. Besides, in order to further reduce the effect of virtual impedance on the overall output impedance, a band-pass filter is needed to reduce the effect of feedforward on the overall output impedance.
The mathematical model and simulation in this paper are cross-validated to prove the correctness of the mathematical model. Furthermore, an impedance analyzer measures the actual circuit to validate this paper's mathematical derivation and discussion.