A Sliding-Mode-Based Duty Ratio Controller for Multiple Parallelly-Connected DC–DC Converters with Constant Power Loads on MVDC Shipboard Power Systems

The development of powered electronic technology has made many aware of the design and control of ship power systems (SPSs), and has made medium voltage DC (MVDC) architecture the main research direction in the future. The negative impedance characteristic of constant power load (CPL) generated by the coupling of powered electronic converters will seriously affect the stability of the systems if these converters are not properly controlled. The conventional linear control method can only guarantee the small-signal stability of the system near its equilibrium point. When the operating point changes in a large range, linear control methods will be ineffective. More importantly, research for the large-signal stability of the multi-converter system with CPLs is still rarely involved. In this paper, a sliding-mode-based duty ratio controller (SMDC) is proposed for voltage regulation and current sharing of the multiple parallelly-connected DC–DC converters system loaded by CPLs. By controlling the output voltage of each converter with SMDC, large-signal stability of the coupled bus voltage is ensured. Meanwhile, proportional current sharing between the parallel converters is achieved by droop control integrated in the reference value of converter voltage. Simulation studies were conducted in MATLAB/Simulink, where two typical operating conditions, including the variation of load power and bus voltage, were designed to verify the effectiveness of the proposed method. Moreover, a traditional PID controller was used as a comparison to reflect the superiority of the former. Simulation results showed that the proposed method is able to guarantee large-signal stability of the system in the presence of large-scale variations in load power and bus voltage. The output current of the parallel converters can also be distributed in desired proportions according to the droop coefficient.


Introduction
With the maturity of powered semiconductor technology and the development of high-energy DC equipment [1,2], the medium voltage DC (MVDC) ship power system (SPS) has gradually become the main development trend of integrated power systems for ships [3,4]. Compared with the existing AC system, DC architecture has significant advantages in achieving generator considered. Nevertheless, the stabilization methods were mainly focused on a small-signal model. A nonlinear control method considering large-signal stability for a multiple parallelly-connected DC-DC converters system is still urgently needed.
This paper proposes a sliding-mode-based duty ratio controller for the multiple parallelly-connected DC-DC converters system with CPLs. By controlling the output voltage of each converter with a sliding-mode-based duty ratio controller (SMDC), the large-signal stability of the bus voltage is ensured. Current sharing between the parallel converters was conducted by droop control strategy, which was integrated in the SMDC coefficient. Differently from the previous research, the large-signal stability of the multi-converter system with CPLs was considered.
The rest of the paper is organized as follows. In Section 2, modeling of the multi-converter MVDC SPS and the stability issues induced by CPLs are presented. In Section 3, the sliding-mode controller design procedures for DC-DC converters are proposed, including a brief introduction of a conventional sliding-mode controller design; we also describe a SMDC for parallel converters with CPLs, estimation of the control coefficient, and a proportional current sharing strategy for the parallel converters. Finally, implementation of the duty ratio controller is described. Simulation studies are presented in Section 4, for which two types of conditions, including variation of the load power and reference bus voltage, were designed for verification of the proposed controller. Comparisons between the proposed SMDC and a traditional PID controller are presented to reflect the value of the former. Finally, conclusions are presented in Section 5.

MVDC SPS Modeling and Instability Induced by CPLs
As the next-generation ship integrated power system for future fleets, the MVDC SPS is expected to have the characteristics of high power density, high reliability, and high stability. It was based on the design considerations in [2] and the recommended practice for MVDC SPS from [7]. A specific model of a zonal MVDC SPS has been presented in [21]. Generators and electrical loads are connected to the longitudinal MVDC bus via powered electronic converters. Bow and stern cross-hull disconnect switches are allocated between the port and starboard MVDC bus to provide the capability of configuring a ring bus, which is able to enhance power system survivability. A SPS with such an architecture is able to maximize a system's operational capability under the constraints of limited size and weight [7].
Taking the voltage stability of the MVDC bus as our research object, the powered electronic converters can be divided into source side and load side. Meanwhile, it is presumed that bow and stern disconnect switches are controlled in XOR state to reduce the difficulty of protection. The schematic diagram of the proposed MVDC SPS is presented in Figure 1.
Consider the rectified generator as a DC voltage source; and the propulsion motors, load centers, and high-energy equipment that regulates the high bandwidth converters can be viewed as an instantaneous CPL. Then the problem can be expressed in a more general form, as a set of multiple parallelly-connected converters loaded by CPLs and resistive loads, as shown in Figure 2. The dynamics of the system can be described by the capacitor voltage and inductor current of the parallel converters in a time-average model [22].
where The subscript i in the variables indicates the ith converter, where i = 1, 2, ..., N. i L i , v C i , and i i are the inductor current, capacitor voltage, and output current of each converter,; d i is duty ratio of each converter and the control variable of the system. v B is the voltage of the MVDC bus, P L is the power of the integrated CPL, and R is the resistance of the resistive load. L i , C i , and r i are the inductance, capacitance, and line resistance of the ith converter.
The objective of the system is to maintain voltage stability of the MVDC bus and ensure proper current sharing among the source converters in the presence of variation of load power or bus voltage.
For such a complex system, it is difficult to consider the current coupling of the parallel converters directly. Thus, it is assumed that the output current of each converter i i is proportional to the rated power of its power supply, which is Since the rated power of each generator is determined, the current sharing coefficient w i can be viewed as a constant.
In order to illustrate the impact of the negative impedance characteristic of the CPL, we start with small-signal analysis of the system around its equilibrium point. Leti L i = 0 andv C i = 0; the system equilibrium point can be calculated asī Considering small disturbances in state variables [13]: where D i , I L i , I i , V C i , and V B are the moving average values; andd i ,ĩ L i ,ĩ i ,ṽ C i , andṽ B are the small disturbances.
Moreover, to study the dynamics of the bus voltage v B , the parallelly-connected source converters are considered as a whole with an integrated equivalent capacitor C eq , where Substituting (5) into (1) and (6), the small-signal model of the system becomes Notice that the second addendum in Equation (7) is derived from the following approximation due to the fact that V B ṽ B : ; the inductance of each converter is equal to L; and the input source voltages are equal to V. Then the transfer function of the system can be obtained from (7) as In order to ensure the stability of the system, the poles of the transfer function need to be kept in the left half plane. That means that the power of the resistive load V 2 B /R needs to be greater than the constant power load P L , which is impractical in an SPS, since most of the loads are tightly regulated as CPLs.  Figure 3 shows the simulation result of the multi-converter system with CPLs and resistive load. The duty cycle of each converter is controlled in open loop, the desired bus voltage is 1000 V, and the power of CPL is 25 kW. When the system simulates without resistive load, bus voltage oscillates with equal amplitude and the system is unstable. When when system simulates with R = 1 Ω, voltage oscillation quickly reduces and the system is stabilized. As the load impedance increases, the damping effect of the resistive load decreases, and the time required for stabilization increases accordingly until V 2 B /R < P L .

The Proposed Sliding-Mode-Based Duty Ratio Controller for DC-DC Converters
In order to achieve large-signal stability of the system without changing its hardware structure, a nonlinear control method is needed. As a classic method in nonlinear control, sliding-mode control is famous for its robustness, and its capability of dealing with uncertainty of parameters in the system designing process. In sliding-mode control, trajectories are forced to reach a sliding manifold in finite time and to stay on the manifold for all time thereafter. By using a lower order model, the sliding manifold is designed to achieve the control objective [23].

The Conventional Sliding-Mode Controller for the DC-DC Converter
Taking a single input single output buck converter with a constant power load as an example, a brief introduction of a conventional sliding-mode controller design procedure is presented [24,25].
Consider a special case of single converter for (1), where N = 1 and v C = v B . A sliding-mode surface σ for this system is designed as where e v = V re f − v C is the tracking error of converter output voltage; c 1 , c 2 , c 3 are the control parameters termed sliding coefficients. To make the system's state converge to the sliding surface through controller action, a switching control law is implemented as follows: Define a candidate Lyapunov function as V = σ/2; then,V = σσ < 0 must always be satisfied in order to ensure controller stability and convergence to the sliding surface. Additionally, considering (1), (10), and (11), the ranges of sliding coefficients c 1 , c 2 , c 3 can be determined.
Finally, the switching control law u sw can be directly used as the signal for the switching circuit (e.g., MOSFET, IGBT). However, the switching frequency of the circuit will be variable, which will make the controller very sensitive to disturbances and cause great difficulties in circuit design in practical applications.

The Proposed SMDC for Parallel Converters with CPLs
In MVDC SPS, the primary objective is the stability of bus voltage. Choose the converter voltage v C i as the state variable; then let the tracking error bex is the reference value of the converter voltage. In order to have the system track v C i ≡ V re f C i , a sliding surface s = 0 is defined as The Lyapunov function of the system is defined as Rewrite s i as To ensure the stability of the control system, the time derivative of the Lyapunov function must always be negative when s = 0; that is,V The time derivative of s i isṡ The first-order and second-order derivative of the tracking errorx i can be calculated aṡx Substituting (17)- (19) into the expression ofṡ i yieldṡ The equivalent controld i of the duty ratio controller that would achieveṡ i = 0 is thus Energies 2020, 13, 3888 8 of 18 Moreover, in order to satisfy the sliding condition despite the uncertainty in system dynamics, a discontinuous term is added to d i as where sgn[·] is the sign function, and k i is a positive constant. By choosing an appropriate k i , the large-signal stability of the system can be ensured, witḣ

Robustness of the Controller to Parameter Inaccuracy
Note that the equivalent capacitor C eq in Equation (19) is an estimated value for the entire parallelly-connected system. In an ideal situation when the line resistance r i is neglected and the source voltages are identical, C eq can be calculated by C eq = ∑ C i as presented in [12].
In practice, there will be a certain deviation between the actual capacitance value and the theoretical value due to the influence of circuit parameters. Robustness of the controller to inaccurate estimation of the parameters is the key to controller design.
Firstly, it is presumed thatĈ eq = ∑ C i is the estimated value for C eq ; then, the equivalent control becomesd Substituting (22) and (24) into (20) yieldṡ To ensure large-signal stability of the system,V(s) needs to be negative definite. ThusV(s i ) < 0 should always be satisfied when s i = 0, (1) If s i > 0,ṡ i needs to be smaller than 0, which yields (2) If s i < 0,ṡ i needs to be greater than 0, which yields Since (26) and (27) need to be simultaneously satisfied, k i needs to meet the condition Notice that ∑ i C i = C eq dv B dt . Considering discrete time control, the maximum gradient of the bus voltage affordable can be presented in where ∆T is the switching cycle of the duty ratio controller, and ∆V max is the maximum deviation allowed in each cycle. Moreover, it is assumed that the actual value of the equivalent capacitance C eq is related to the estimation valueĈ eq by C eq = αĈ eq , where α ∈ (0, 2) considering a 100% estimated deviation. Thus (28) can be transformed into Then the range of k i can be determined.

Proportional Current Sharing between the Parallelly-Connected Converters
Consider the current sharing issues between the parallelly-connected buck converter system in Figure 2; Equation (2) can be reformulated as It can be observed that the current sharing is determined by the converter output voltage v C i , cable resistance r i , and bus voltage v B .
As mentioned above, the objective of system voltage regulation is to stabilize the bus voltage at a reference value, and line resistance is usually a fixed value. Therefore, the current sharing could be achieved by adjusting the reference value of v C i on the basis of bus voltage regulation, which is where I load ≡ ∑ N i=1 i i , and i i = w i I load . So far, a simplified load sharing can be realized by the open loop method in Equation (32), but its performance heavily depends on the value of the line resistance. Specifically, the larger the line impedance, the greater the difference between converter output voltage and bus voltage. The ratio of steady-state voltage ripple to this difference is comparatively smaller, and thus the output current is more stable. However, the reality is just the opposite: line impedance is usually small; thus, open-loop current sharing often makes it difficult to achieve the desired effect.
Therefore, a closed-loop proportional current sharing scheme is achieved by where e i = i i − w i I load . The error between the converter output current and the expected value is fed back to the original output through a PID link, so that the output current is more smooth and stable.

Parameter Selection and Implementation of the Duty Ratio Controller
The control block diagram of each duty ratio controller is presented in Figure 4. In order to ensure the stability and convergence speed of the system, the parameters of the controller need to be properly designed.
Except for the control parameters a 1 i , a 2 i , and a 3 i , other parameters, such as the current sharing coefficient w i and the control coefficient k i of the switching function, have already been determined.
Notice that a 1 i , a 2 i and a 3 i affect the dynamics of the sliding-mode surface and the reaching time of the controller. Meanwhile, (12) and (14) conform to the standard form of second-order linear system equation under critical damping state,ẍ + 2ω nẋ + ω n 2 x = 0, with a 2 i /a 1 i = 2ω n and a 3 i /a 1 i = ω n 2 .
Define ω n = 2π f bw , where f bw is the bandwidth and is commonly selected as 1/10 of the sampling frequency [13].
Then, the output of the proposed SMDC can be expressed as After the process of saturation and PWM generation, finally we can get the control signal required by the converter gate.
In practice, the difficulty of obtaining state variables should be considered. Measurement of the output voltage v C i of each converter and the bus voltage v B is necessary. Measuring capacitor current i C i and its summation could be complicated. In the application process, we can obtain i C i by differentiating v C i .

Simulation
Simulation studies were performed to verify the effectiveness of the proposed algorithm. The experimental system was built in MATLAB/Simulink with the Simscape Electrical library.
As shown in Figure 5, the system consisted of four distributed sources and one integrated load; the source converters were parallelly connected via MVDC bus, and the integrated CPL is depicted by a constant current source. As resistive loads have the effect of suppressing voltage oscillation, pure CPL was considered here for higher requirements on controller design. Moreover, circuit parameters of the simulation system are presented in Table 1.
For the MVDC SPS, the control objective was to maintain voltage stability of the MVDC bus and balance load sharing of the source converters by designing an appropriate duty ratio controller which is adaptable for various operating conditions. Two types of operating conditions, i.e., variation of load power demand and variation of reference bus voltage, were considered to verify the effectiveness of the proposed controller, as shown in Figure 6.
The parameters of the PID controller for current feedback in Equation (33) were designed as K p = 5, K i = 10, and K d = 0.01.
The coefficient k i of the switching function in Equation (34) can be determined by Equation (30) if we define the affordable voltage deviation in each cycle to be ∆V max = 1V, and then k 1 = 200, k 2 = 190, k 3 = 180, k 4 = 170.
Considering that the ratio of the rated power of each generator was 4:3:2:1, the current sharing coefficients of the parallel converters were designed as 0.4, 0.3, 0.2, and 0.1 for converters 1-4. With f bw = 1000 Hz, we can get a 2 i /a 1 i = 1.256 × 10 4 , and a 3 i /a 1 i = 3.944 × 10 7 . Thus the remaining control parameters can be calculated.
Furthermore, a traditional PID controller is introduced as a comparison; the controller is defined as where ε i = V re f B + w i r i I load − v C i , and K P = 5, K I = 10, K D = 0.01.

Load Power Variation
In the first case, the load power of CPL made large-scale variations during the simulation time. As shown in Figure 6a, the CPL was initially 1 MW, and then instantaneously changed to 2 MW at 0.25 s, 4 MW at 0.5 s, and finally, 6 MW at 0.75 s. Figure 7 shows the voltage response and load sharing conditions of the multi-converter system under control of the proposed SMDC controller during step changes in CPL. As shown in Figure 7a, when load power changes significantly, the bus voltage will generate an instantaneous voltage drop and quickly return to the given reference value under the action of the SMDC controller. The transient recovery time is within 0.01 s and the steady state voltage ripple is 2 V (0.2%), which is far less than the specified value 2 s and 5% in the IEEE standard for MVDC SPS [7,26]. Figure 7b shows the output voltage response of each parallelly-connected converter. As the load current increases, the output voltage difference of each converter increases accordingly due to the use of droop control strategy. Figure 7c,d shows the output current and output power of each converter, It can be seen that the distribution of output current and power of each source converter always maintains a ratio of 4:3:2:1, except for several transient processes.
As a comparison, Figure 8 shows the voltage response and load sharing under the control of the PID controller during step changes in CPL. As we can see in Figure 8a, the bus voltage is well controlled at initial state. Although the control accuracy is not perfect, it also meets the requirements of the IEEE std. While when the load power changes to 2 MW, the bus voltage starts to oscillate at a 2% level. When the load power continues to increase, the voltage oscillation increases accordingly, and finally, the voltage collapses. Figure 8c shows the current sharing between each converter. Although the distribution roughly maintains the ratio of 4:3:2:1 at initial state, the current sharing process is not stable due to the insufficient accuracy of the voltage control and the absence of current feedback. Similarly, in Figure 8d, when bus voltage becomes unstable, the power sharing cannot be balanced either. Eventually, the whole system becomes unstable.

Reference Voltage Variation
In the second case, the reference value of the MVDC bus changes from 1000 V to 800 V at 0.5 s, as shown in Figure 6b. Figure 9 shows the voltage response and load sharing conditions under SMDC control during step changes in reference bus voltage. From the simulation we can see that the voltage is well controlled at all times. A more specific view is presented in Figure 9a: the transient recovery time is within 0.005 s and the steady-state voltage ripple is within ±2 V. Figure 9c,d shows the current sharing and power sharing conditions of the parallel converters. It can be seen that except for the transient process from 0.500-0.505 s, the output current and output power of each converter is always balanced at a ratio of 4:3:2:1, and the load power of the integrated CPL is maintained at 1 MW. Likewise, the results of the PID controller are shown in Figure 10. As shown in Figure 10a, the bus voltage can remain stable most of the time, but the transient recovery time is more than 0.1s, which is longer than that of the SMDC, and the steady-state voltage ripple is bigger. Furthermore, by comparing Figures 9c and 10c, we can see that the load balancing effect obtained by the SMDC is better than that of PID.
By comparing SMDC and PID under these two typical operating conditions, we can see the limitation of the linear controller, that is, it can only keep small-signal stability near its equilibrium point. By contrast, the proposed SMDC is able to stabilize the multiple parallelly-connected converter system in the presence of large-scale variations of load power or bus voltage, and realize stable and smooth current sharing in desired proportion.

Conclusions
In this paper, a multiple parallelly-connected DC-DC converters system loaded by CPLs was analyzed; the problems of voltage stabilization and current sharing were considered. Due to the inherent negative impedance characteristics of CPL and its nonlinearity exhibited when cascaded with the source converter, a nonlinear control method is needed to ensure large-signal stability of the system. Therefore, a sliding-mode-based duty ratio controller was proposed to control converter voltage, by which large-signal stability of bus voltage is ensured. The droop control method with load current feedback is integrated in the reference value of converter output voltage for proportional current sharing. Two types of conditions, including load power variation and reference bus voltage variation, were considered in simulation studies to verify the effectiveness of the proposed SMDC. A traditional PID controller was used as a comparison to reflect the advantage of the SMDC. The simulation results show that the SMDC has better performance in face of large-scale load power variation and reference bus voltage variation, while the PID controller can only stabilize the system around the initial equilibrium point. Meanwhile, we can get a better current sharing effect with the SMDC; the output current of the parallel converters can be well distributed in the desired proportions due to accurate voltage control and droop control with current feedback.