Understanding Turn-On Transients of SiC High-Power Modules: Drain-Source Voltage Plateau Characteristics

The SiC (silicon carbide) high-power module has great potential to replace the IGBT (insulated gate bipolar transistor) power module in high-frequency and high-power applications, due to the superior properties of fast switching and low power loss, however, when the SiC high-power module operates under inappropriate conditions, the advantages of the SiC high-power module will be probably eliminated. In this paper, four kinds of SiC high-power modules are fabricated to investigate fast switching performance. The variations in characteristics of drain-source voltage at turn-on transient under the combined conditions of multiple factors are studied. A characteristic of voltage plateau is observed from the drain-source voltage waveform at turn-on transient in the experiments, and the characteristic is reproduced by simulation. The mechanism behind the voltage plateau is studied, and it is revealed that the characteristic of drain-source voltage plateau is a reflection of the miller plateau effect of gate-source voltage on drain-source voltage under the combined conditions of fast turn-on speed and low DC bus voltage, while the different values of drain-source voltage plateau are attributed to the discrepancy of structure between upper-side and lower-side in the corresponding partial path of the drain circuit loop inside the module, with the standard 62 mm package outline.


Introduction
The switching transient of power devices/modules has been widely studied, based on double pulse test (DPT) experiments. There were many reports about the influence of structure of power converter/module on switching transient, such as the issue of overshoot voltage by drain circuit loop [1,2], the oscillation issue by inductance of gate driver loop [3], the different switching speed due to the difference of module structure [4][5][6][7], the voltage/current spikes by interconnect parasitics of power converters [8], and the switching loss by parasitic capacitance of a power module/converter [9][10][11]. These studies showed that the influence of structure on switching transient was reflected in multiple fields or dimensions, e.g., overshoot voltage, oscillation, and switching loss.
There were reports about the impact of test conditions on switching transient, such as the influence of load on switching transients [12], the variations in external gate resistance caused different slew rate of drain-source voltage [13], the parameters of the gate driver circuit determined the maximum switching speed [14]. The influence of test condition on switching transient was mainly related to the field of switching speed.
For the influence of switching speed on switching transient, the research was mainly focused on the serious issues existed along with fast switching, such as the high frequency oscillation in upper-side The difference among these modules are mainly reflected in the inner structure and the used power dies including the types and the parallel number of the power dies. As shown in Figure 2, the inner structure of the module_B is same with that of the module_A, but different from that of module_C, while the structure of module_D is different from that of other modules. As shown in Table 1, there are two types of SiC-MOSFET dies adopted inside the developed modules, the type of adopted SiC-MOSFET dies in module_A is different from that of other modules. The parallel number of SiC-MOSFET dies in module_B is same with that of module_C, and the parallel number of SiC-MOSFET dies in module_D is different from that of module_B and module_C. With the various designs for the number of parallel-connected power die inside the module, the values of input capacitance of the modules are different accordingly. Thus, the various turn-on speed can be achieved for the modules under the same test conditions (same , , and ), and with a same gate driver circuit in the following experiments. This is helpful for the study of influence of turn-on speed on the turn-on transient, especially the characteristics of drain-source voltage. The difference among these modules are mainly reflected in the inner structure and the used power dies including the types and the parallel number of the power dies. As shown in Figure 2, the inner structure of the module_B is same with that of the module_A, but different from that of module_C, while the structure of module_D is different from that of other modules. The difference among these modules are mainly reflected in the inner structure and the used power dies including the types and the parallel number of the power dies. As shown in Figure 2, the inner structure of the module_B is same with that of the module_A, but different from that of module_C, while the structure of module_D is different from that of other modules. As shown in Table 1, there are two types of SiC-MOSFET dies adopted inside the developed modules, the type of adopted SiC-MOSFET dies in module_A is different from that of other modules. The parallel number of SiC-MOSFET dies in module_B is same with that of module_C, and the parallel number of SiC-MOSFET dies in module_D is different from that of module_B and module_C. With the various designs for the number of parallel-connected power die inside the module, the values of input capacitance of the modules are different accordingly. Thus, the various turn-on speed can be achieved for the modules under the same test conditions (same , , and ), and with a same gate driver circuit in the following experiments. This is helpful for the study of influence of turn-on speed on the turn-on transient, especially the characteristics of drain-source voltage. As shown in Table 1, there are two types of SiC-MOSFET dies adopted inside the developed modules, the type of adopted SiC-MOSFET dies in module_A is different from that of other modules. The parallel number of SiC-MOSFET dies in module_B is same with that of module_C, and the parallel number of SiC-MOSFET dies in module_D is different from that of module_B and module_C. The module_B has the same structure but different power dies with module_A, and also have the same power dies but different structure with module_C. The module_D is designed with only 4 parallel SiC-MOSFET dies and a consequent very small input capacitance to enable a faster turn-on at high current output. It is worth noting that the circuit is carefully designed to eliminate severe negative gate-source voltage spike during the turn-on transient.
In order to slow down appropriately turn-on speed, the additional common source path is introduced in both module_A and module_B, but for other modules, the common source path inside modules is minimized. In addition, since the turn-on speed of module_D is much higher than other modules, in order to avoid the interference due to a faster turn-on speed to the gate-source voltage of the module at turn-on transient, the difference in gate-source routings for the parallel power dies is reduced, and the symmetry of them is improved, meanwhile, the drain-source path inside module is also optimized to reduce its parasitic inductance.
Based on these designs, the influence of power dies on characteristics of v DS can be compared between module_A and module_B, while the influence of module's structure on characteristics of v DS can be compared between module_B and module_C. The impact of the faster turn-on speed on characteristics of v DS can be reflected from module_D under the same gate driver circuit and test conditions.

Introduction of the Double Pulse Test Platform
The physical picture of the clamped inductive DPT rig is shown in Figure 3a. The device under test (DUT) is the developed module. The decoupling capacitor is from KEMET. The load inductor is self-fabricated by serial-connected two inductors. The DC bus capacitor with part number of FG810K901-1 is from VDTCAP. The voltage rating of this DC bus capacitor is 900 V. Due to this, we have to ensure that the sum of the applied DC bus voltage (V DD ) and overshoot voltage is no more than 900 V at experiments. The module_B has the same structure but different power dies with module_A, and also have the same power dies but different structure with module_C. The module_D is designed with only 4 parallel SiC-MOSFET dies and a consequent very small input capacitance to enable a faster turn-on at high current output. It is worth noting that the circuit is carefully designed to eliminate severe negative gate-source voltage spike during the turn-on transient.
In order to slow down appropriately turn-on speed, the additional common source path is introduced in both module_A and module_B, but for other modules, the common source path inside modules is minimized. In addition, since the turn-on speed of module_D is much higher than other modules, in order to avoid the interference due to a faster turn-on speed to the gate-source voltage of the module at turn-on transient, the difference in gate-source routings for the parallel power dies is reduced, and the symmetry of them is improved, meanwhile, the drain-source path inside module is also optimized to reduce its parasitic inductance.
Based on these designs, the influence of power dies on characteristics of can be compared between module_A and module_B, while the influence of module's structure on characteristics of can be compared between module_B and module_C. The impact of the faster turn-on speed on characteristics of can be reflected from module_D under the same gate driver circuit and test conditions.

Introduction of the Double Pulse Test Platform
The physical picture of the clamped inductive DPT rig is shown in Figure 3a. The device under test (DUT) is the developed module. The decoupling capacitor is from KEMET. The load inductor is self-fabricated by serial-connected two inductors. The DC bus capacitor with part number of FG810K901-1 is from VDTCAP. The voltage rating of this DC bus capacitor is 900 V. Due to this, we have to ensure that the sum of the applied DC bus voltage ( ) and overshoot voltage is no more than 900 V at experiments.  The 1GHz high definition oscilloscope with part number of HDO6104A used for acquiring the voltage and current signals is from Teledyne Lecroy. A Rogowski current waveform transducer with part number of CWT miniHF 1B utilized to measure drain-source current of DUT is from PEM, the bandwidth of this current probe is 30 MHz. A passive voltage probe with part number of PP026-2 used for measuring gate-source voltage is from Teledyne Lecroy, the bandwidth of this voltage probe is 500 MHz. A high voltage differential probe with part number of HVD3106 used to obtain the drainsource voltage is from Teledyne Lecroy, the bandwidth of this high voltage probe is 120 MHz.
The schematic diagram of the DPT circuit is shown in Figure 3b. The double pulse signal is applied to the gate-source of DUT by gate-driver circuit. The gate-source voltage for turning off and turning on switches is −2.3 V and 17.5 V, respectively. The is external resistor of the gate driver circuit. The values of electrical parameter of some components in DPT rig are listed in Table 2. The 1GHz high definition oscilloscope with part number of HDO6104A used for acquiring the voltage and current signals is from Teledyne Lecroy. A Rogowski current waveform transducer with part number of CWT miniHF 1B utilized to measure drain-source current of DUT is from PEM, the bandwidth of this current probe is 30 MHz. A passive voltage probe with part number of PP026-2 used for measuring gate-source voltage is from Teledyne Lecroy, the bandwidth of this voltage probe is 500 MHz. A high voltage differential probe with part number of HVD3106 used to obtain the drain-source voltage is from Teledyne Lecroy, the bandwidth of this high voltage probe is 120 MHz.
The schematic diagram of the DPT circuit is shown in Figure 3b. The double pulse signal is applied to the gate-source of DUT by gate-driver circuit. The gate-source voltage for turning off and turning on switches is −2.3 V and 17.5 V, respectively. The R gext is external resistor of the gate driver circuit. The values of electrical parameter of some components in DPT rig are listed in Table 2. The diagram of commutation paths at turn-on transient is shown in Figure 4a, SiC MOSFET dies are in off-state off initially, the voltage applied between gate and source (V GS ) is set to V GL , the load current circulates along the loop_ 1 , as shown by the gray dash line. At turn-on transient the gate-source voltage (V GS ) increase from V GL to V GH , the circulating current starts to transfer from the loop_ 1 to the loop_ 2 , as marked by red dash line. After turn-on transient process, the load current flows fully by SiC-MOSFETs, instead of the freewheeling diodes.

Introduction of the Turn-On Transient Process for SiC High-Power Module
The diagram of commutation paths at turn-on transient is shown in Figure 4a, SiC MOSFET dies are in off-state off initially, the voltage applied between gate and source (VGS) is set to VGL, the load current circulates along the loop_①, as shown by the gray dash line. At turn-on transient the gatesource voltage (VGS) increase from VGL to VGH, the circulating current starts to transfer from the loop_① to the loop_②, as marked by red dash line. After turn-on transient process, the load current flows fully by SiC-MOSFETs, instead of the freewheeling diodes.  The typical diagram of turn-on transient for SiC high-power module is shown in Figure 4b. The whole fall process of at turn-on transient can be divided by two distinct phases. The phase from to is the 1st turn-on interval, (on). During the (on), with the rises to , the fall linearly with time and the is pulled down to a lowest value, due to the negative feedback effect. The voltage drop induced by the rising and parasitic inductance is given by where is the parasitic inductance of the whole drain circuit loop in DPT, which includes the parasitic inductance of routings from the power terminals of "DC+" to "DC−" inside the module, _ , and the parasitic inductance of drain circuit loop excluding the routings inside the module in DPT, _ .
The phase from to is the reverse recovery process of the freewheeling diodes, which is the 2nd turn-on interval, (on). It consists of two sub-phases. During sub-phase from to , the continues to rise to its maximum, since the voltage starts to be clamped to freewheeling diode, the reduces in a higher d /dt due to reverse recovery. During the sub-phase from to , the reverse recovery current of freewheeling diode decreases from its maximum to zero, the also decreases from the maximum to , the turn-on transient of SiC-MOSFET is completed at the end of this phase.
During this phase from to , the operation mode of SiC-MOSFET dies changes from saturation region to linear region. After , the SiC-MOSFET is fully turned-on. All , , characteristics are kept in oscillation state with their respective frequencies which are determined by The typical diagram of turn-on transient for SiC high-power module is shown in Figure 4b. The whole fall process of v DS at turn-on transient can be divided by two distinct phases.
The phase from t 1 to t 2 is the 1st turn-on interval, τ 1 (on). During the τ 1 (on), with the i DS rises to I O , the v DS fall linearly with time and the v gs is pulled down to a lowest value, due to the negative feedback effect. The voltage drop induced by the rising i DS and parasitic inductance is given by where L D is the parasitic inductance of the whole drain circuit loop in DPT, which includes the parasitic inductance of routings from the power terminals of "DC+" to "DC−" inside the module, L D_1 , and the parasitic inductance of drain circuit loop excluding the routings inside the module in DPT, L D_2 . The phase from t 2 to t 4 is the reverse recovery process of the freewheeling diodes, which is the 2nd turn-on interval, τ 2 (on). It consists of two sub-phases. During sub-phase from t 2 to t 3 , the i DS continues to rise to its maximum, since the voltage starts to be clamped to freewheeling diode, the v DS reduces in a higher dv DS /dt due to reverse recovery. During the sub-phase from t 3 to t 4 , the reverse Energies 2020, 13, 3802 6 of 18 recovery current of freewheeling diode decreases from its maximum to zero, the i DS also decreases from the maximum to I O , the turn-on transient of SiC-MOSFET is completed at the end of this phase.
During this phase from t 2 to t 4 , the operation mode of SiC-MOSFET dies changes from saturation region to linear region. After t 4 , the SiC-MOSFET is fully turned-on. All v gs , v DS , i DS characteristics are kept in oscillation state with their respective frequencies which are determined by the parasitic parameters in the circuit.
As shown in Figure 4b, during the v DS falls from V DD to zero, the operation mode of SiC-MOSFET dies changes from saturation region to linear region. Point_1 is the turning point for v DS , changing from τ 1 (on) to τ 2 (on) during SiC-MOSFET dies operate in saturation region, which corresponds to the moment when i DS rises to I O , while Point_2 is the turning point in v DS when the operation mode of SiC-MOSFET dies changing from saturation to linear region, which corresponds to the moment when i DS rising up to the maximum value.
Under the combined impacts of multiple factors such as various test conditions, turn-on speed and structures of DUT, the turn-on transients of v DS from t 1 to t 4 are probably varied in more than one dimension, the values of the key turning point vary, and, meanwhile, the characteristics of v DS waveforms such as the number of key turning points and the shape of drain-source voltage waveform also change, so that the different characteristics of the falling process of v DS waveforms could be observed. Therefore, in order to facilitate comparison between the modules in the following sections, we neglect the variations in the value of the turning point and just focus on changes in characteristics of v DS , such as the number of key turning points, whether there is a characteristic of point_2 or not, and whether there is a characteristic of the voltage plateau or not.

Experimental Results
The turn-on transient of SiC high-power module is essentially the charging process of the input capacitance of the module by the gate driver circuit. The rise of i DS is determined by the charging speed of the input capacitance of the module. We can simply view this system consisting of gate driver and the input capacitance of the module as a one-order low-pass resistance-capacitance (RC) network, where the output of gate driver circuit can be regarded as input signal of the network, and the gate-source voltage (v gs ) is the output of this network. The response of this network to the turn-on signal determines the ideal transient waveform of v gs and defines the turn-on speed of the module. To facilitate analysis, we use the rise time of this one-order low-pass RC network as a precursor of turn-on speed of the module. Since the module operates in saturation mode, the i DS is proportional to the v gs at turn-on transient. Hence, a shorter rise time means a faster turn-on speed for the developed modules.
The rise time of the output for the one-order low-pass RC network can be given by where t r is rise time, R g is the resistance of the whole gate driver loop, C iss is the input capacitance of the module. According to Equation (3), there are two ways to increase the turn-on speed of the developed modules for a specific gate driver circuit, namely, reducing the external gate resistance in DPT and driving a module with a lower input capacitance. Based on the input capacitance of the developed modules shown in Table 1, it is predicted that the turn-on speed of module_A is the slowest, while module_D is the fastest under the same test conditions (same V DD , I O , and R gext ). In order to investigate the influence of module's structures on the turn-on transient of v DS , the comparative experiments are carried out under various conditions of V DD . Finally, the trend of changes in influence of module's structures on characteristics of v DS with the increase of tun-on speed or the reduce of V DD is summarized.

Turn-On Transient at Condition of Relatively High V DD
The experimental results under relatively high V DD are shown in Figures 5-7, where V DD is set to be 400 V, I O is set to be 200 A, and R gext is set to be 2.4 Ω. The green, red, black, and purple lines stand for the experimental results of module_A, module_B, module_C, and module_D, respectively; the solid and dash lines stand for the experimental results of the upper-side and lower-side respectively for a corresponding module.  Figure 6 shows the comparison of turn-on transient waveforms of module_B and module_C, which have the same power dies but different structure designs. The characteristics of of module_C is different from that of the module_B, and there is only Point_1 existing in waveform, Point_2 which corresponds to the operation mode of SiC-MOSFET dies changing from saturation to linear region is not observed in , as shown in Figure 6b. In addition, the difference in value of at Point_1 between these two modules still exists but it is reduced, e.g., it is just 16.4 V on the upperside, while it is 9.6 V on the lower-side.  Figure 7 shows the comparison of turn-on transient waveforms of the modules with various turn-on speed. The turning on process of module_D is faster than that of the other modules, due to the smaller input capacitance and shorter rise time, the characteristic of in module_D is fully different from that of other two modules, Point_1 is negligible and Point_2 disappears, as shown in Figure 7b. This means that as turn-on speed increases, the falls faster at turn-on transient, as a result, the characteristics that is corresponding to the operation mode of SiC-MOSFET dies changing from saturation to linear region in (on) disappear in , and characteristics that is corresponding to the changing from (on) to (on) during the SiC-MOSFET dies operating in saturation mode, start to be weakened in .  Figure 6 shows the comparison of turn-on transient waveforms of module_B and module_C, which have the same power dies but different structure designs. The characteristics of of module_C is different from that of the module_B, and there is only Point_1 existing in waveform, Point_2 which corresponds to the operation mode of SiC-MOSFET dies changing from saturation to linear region is not observed in , as shown in Figure 6b. In addition, the difference in value of at Point_1 between these two modules still exists but it is reduced, e.g., it is just 16.4 V on the upperside, while it is 9.6 V on the lower-side.  Figure 7 shows the comparison of turn-on transient waveforms of the modules with various turn-on speed. The turning on process of module_D is faster than that of the other modules, due to the smaller input capacitance and shorter rise time, the characteristic of in module_D is fully different from that of other two modules, Point_1 is negligible and Point_2 disappears, as shown in Figure 7b. This means that as turn-on speed increases, the falls faster at turn-on transient, as a result, the characteristics that is corresponding to the operation mode of SiC-MOSFET dies changing from saturation to linear region in (on) disappear in , and characteristics that is corresponding to the changing from (on) to (on) during the SiC-MOSFET dies operating in saturation mode, start to be weakened in .   Figure 6 shows the comparison of turn-on transient waveforms of module_B and module_C, which have the same power dies but different structure designs. The characteristics of v DS of module_C is different from that of the module_B, and there is only Point_1 existing in v DS waveform, Point_2 which corresponds to the operation mode of SiC-MOSFET dies changing from saturation to linear region is not observed in v DS , as shown in Figure 6b. In addition, the difference in value of v DS at Point_1 between these two modules still exists but it is reduced, e.g., it is just 16.4 V on the upper-side, while it is 9.6 V on the lower-side. In summary, although the voltage values of the corresponding Point_1 are different from each other, the characteristics of for the modules with the same structure design are same, and the characteristics of for the modules with the different structure design are different.

Turn-On Transient at Condition of Low
The experimental results under the condition of relatively low are shown in Figures 8 and  9, where is set to be 200 V, is set to be 200 A, and is set to be 2.4 Ω. Figure 8 shows the comparison of turn-on transient waveforms of module_A and module_B in low condition, the two modules have the same structure design but different power dies. It is shown that the characteristics of of the two modules are similar, that is, only one turning point is observed. This is different from the case of high condition. The decrease of causes the characteristic corresponding to the operation mode of SiC-MOSFET dies changing from saturation to linear region in (on) disappears in . As depicted previously, the difference in values of at Point_1 between the two modules still exists. The difference in values of at Point_1 between the two modules is 13.5 V in upper-side and 40.8 V in lower-side.   Figure 7 shows the comparison of turn-on transient waveforms of the modules with various turn-on speed. The turning on process of module_D is faster than that of the other modules, due to the smaller input capacitance and shorter rise time, the characteristic of v DS in module_D is fully different from that of other two modules, Point_1 is negligible and Point_2 disappears, as shown in Figure 7b. This means that as turn-on speed increases, the v DS falls faster at turn-on transient, as a result, the characteristics that is corresponding to the operation mode of SiC-MOSFET dies changing from saturation to linear region in τ 2 (on) disappear in v DS , and characteristics that is corresponding to the v DS changing from τ 1 (on) to τ 2 (on) during the SiC-MOSFET dies operating in saturation mode, start to be weakened in v DS .
In summary, although the voltage values of the corresponding Point_1 are different from each other, the characteristics of v DS for the modules with the same structure design are same, and the characteristics of v DS for the modules with the different structure design are different.

Turn-On Transient at Condition of Low V DD
The experimental results under the condition of relatively low V DD are shown in Figures 8 and 9, where V DD is set to be 200 V, I O is set to be 200 A, and R gext is set to be 2.4 Ω. In summary, although the voltage values of the corresponding Point_1 are different from each other, the characteristics of for the modules with the same structure design are same, and the characteristics of for the modules with the different structure design are different.

Turn-On Transient at Condition of Low
The experimental results under the condition of relatively low are shown in Figures 8 and  9, where is set to be 200 V, is set to be 200 A, and is set to be 2.4 Ω. Figure 8 shows the comparison of turn-on transient waveforms of module_A and module_B in low condition, the two modules have the same structure design but different power dies. It is shown that the characteristics of of the two modules are similar, that is, only one turning point is observed. This is different from the case of high condition. The decrease of causes the characteristic corresponding to the operation mode of SiC-MOSFET dies changing from saturation to linear region in (on) disappears in . As depicted previously, the difference in values of at Point_1 between the two modules still exists. The difference in values of at Point_1 between the two modules is 13.5 V in upper-side and 40.8 V in lower-side.   is observed. This is different from the case of high V DD condition. The decrease of V DD causes the characteristic corresponding to the operation mode of SiC-MOSFET dies changing from saturation to linear region in τ 2 (on) disappears in v DS . As depicted previously, the difference in values of v DS at Point_1 between the two modules still exists. The difference in values of v DS at Point_1 between the two modules is 13.5 V in upper-side and 40.8 V in lower-side.
The characteristics of v DS for the modules with the same structure design are same, though the level of V DD takes effect on characteristics of v DS at turn-on transient and there is a difference in the value of v DS at point_1 between the different modules. Figure 9 shows However, when the turn-on speed is faster as for module_D, the voltage plateau is observed from the characteristic of for both upper-side and lower-side, also, the value of for the voltage plateau in upper-side is higher than that of lower-side by about 50 V. Table 3 shows the comparison about characteristics of . Under the condition of relatively high , the characteristics of are greatly affected by the module's structure. If the module's structures are same, the characteristics of will be the same, even if the power dies inside the modules are different from each other. On the other hand, if the structures of the modules are different, the characteristics of are deviated from each other even if the used power dies and their parallel number inside the modules both are same. In addition, the faster turn-on speed can further alter the characteristics of , so that the characteristic of Point_1 for changing from (on) to (on) become less obvious. Under the condition of low , the difference of module's structures does not cause the significant different characteristics of ,but the module design with faster turn-on speed causes the distinct characteristics of voltage plateau in between upper-side and lower-side of the module. However, when the turn-on speed is faster as for module_D, the voltage plateau is observed from the characteristic of v DS for both upper-side and lower-side, also, the value of v DS for the voltage plateau in upper-side is higher than that of lower-side by about 50 V. Table 3 shows the comparison about characteristics of v DS . Under the condition of relatively high V DD , the characteristics of v DS are greatly affected by the module's structure. If the module's structures are same, the characteristics of v DS will be the same, even if the power dies inside the modules are different from each other. On the other hand, if the structures of the modules are different, the characteristics of v DS are deviated from each other even if the used power dies and their parallel number inside the modules both are same. In addition, the faster turn-on speed can further alter the characteristics of v DS , so that the characteristic of Point_1 for v DS changing from τ 1 (on) to τ 2 (on) become less obvious. Under the condition of low V DD , the difference of module's structures does not cause the significant different characteristics of v DS , but the module design with faster turn-on speed causes the distinct characteristics of voltage plateau in v DS between upper-side and lower-side of the module.

Turn-On Transient at Conditions of a Lower V DD and Various Turn-On Speed
Based on the qualitative comparison and analysis of experimental results shown in Figures 5-9, it can be supposed that the characteristics of voltage plateau shown from the v DS waveforms at turn-on transient are due to the combined impacts of fast turn-on speed and low V DD with a specific module structure.
In order to reveal the mechanisms behind the characteristics of the voltage plateau and the impacts of turn-on speed, test conditions and module structure, another experiment is carried out with module_D, in which V DD is fixed at a low value 100 V and the turn-on speed is controlled with three groups of external resistors (R gext ). Figure 10 shows the comparison of characteristics of v DS among the various turn-on speeds by using different R gext . The green, black, and red lines stand for the experimental results under the condition of R gext equal to 11 Ω, 5 Ω, and 2.4 Ω, respectively, and the solid and dash lines stand for the upper-side and lower-side, respectively.

Turn-On Transient at Conditions of a Lower and Various Turn-On Speed
Based on the qualitative comparison and analysis of experimental results shown in Figures 5-9, it can be supposed that the characteristics of voltage plateau shown from the waveforms at turnon transient are due to the combined impacts of fast turn-on speed and low with a specific module structure.
In order to reveal the mechanisms behind the characteristics of the voltage plateau and the impacts of turn-on speed, test conditions and module structure, another experiment is carried out with module_D, in which is fixed at a low value 100 V and the turn-on speed is controlled with three groups of external resistors ( ). Figure 10 shows the comparison of characteristics of among the various turn-on speeds by using different . The green, black, and red lines stand for the experimental results under the condition of equal to 11 Ω, 5 Ω, and 2.4 Ω, respectively, and the solid and dash lines stand for the upper-side and lower-side, respectively. From Figure 10, characteristics of voltage plateau in are observed for the cases of equals to 5 Ω and 2.4 Ω, in which the turn-on speed both are faster than 2.64 A/ns (this is turn-on speed of lower-side for the case of equals to 5 Ω.), the difference in value of the drain-source voltage plateau between upper-side and lower-side is almost same regardless of the rise of the turnon speed, which is about 25 V.
In addition, the characteristic of Point_1 is obvious for the case of equals to 11 Ω. Compared with the previous characteristics of negligible Point_1 in shown in Figure 7b, it is further confirmed by experiment that the rise of the turn-on speed strengthens the influence of module's structure on the characteristics of . Figure 11 shows  From Figure 10, characteristics of voltage plateau in v DS are observed for the cases of R gext equals to 5 Ω and 2.4 Ω, in which the turn-on speed both are faster than 2.64 A/ns (this is turn-on speed of lower-side for the case of R gext equals to 5 Ω.), the difference in value of the drain-source voltage plateau between upper-side and lower-side is almost same regardless of the rise of the turn-on speed, which is about 25 V.
In addition, the characteristic of Point_1 is obvious for the case of R gext equals to 11 Ω. Compared with the previous characteristics of negligible Point_1 in v DS shown in Figure 7b, it is further confirmed by experiment that the rise of the turn-on speed strengthens the influence of module's structure on the characteristics of v DS . Figure 11 shows In summary, for SiC high-power modules, the characteristics of are varied under combined conditions of multiple factors, such as the structure of the module, turn-on speed, , and . The influence of the module's structure on the characteristics of is weakened as the reduces, and strengthened as the turn-on speed rises. If the turn-on speed is fast enough (e.g., more than 2.64 A/ns, as shown in previous experiments), under the condition of high , the characteristic of the turning point for changing from (on) to (on) during SiC-MOSFET dies operate in saturation region will become negligible, while under condition of low , the characteristic of voltage plateau will be observed in . Furthermore, the distinct characteristics of drain-source voltage plateau between the upper-side and lower-sides of the module are related to the combined impacts of fast turn-on speed and low DC bus voltage, as well as the different structures of the two sides inside the module.

Mechanism for Characteristic of Drain-Source Voltage Plateau
The of module_D at turn-on transient is simulated by LTsipce software. The diagram of the schematic circuit for simulation is shown in Figure 12. The parasitic inductance of drain circuit loop ( ) is also divided into two parts, which are ′ and ′′ , respectively. The ′ is the parasitic inductance belong to the partial path of drain circuit loop, which is shared with path between two test points for acquiring transient , while ′′ is the parasitic inductance related to the other part of the drain loop. The influence of the module's structure on the characteristics of v DS is weakened as the V DD reduces, and strengthened as the turn-on speed rises. If the turn-on speed is fast enough (e.g., more than 2.64 A/ns, as shown in previous experiments), under the condition of high V DD , the characteristic of the turning point for v DS changing from τ 1 (on) to τ 2 (on) during SiC-MOSFET dies operate in saturation region will become negligible, while under condition of low V DD , the characteristic of voltage plateau will be observed in v DS . Furthermore, the distinct characteristics of drain-source voltage plateau between the upper-side and lower-sides of the module are related to the combined impacts of fast turn-on speed and low DC bus voltage, as well as the different structures of the two sides inside the module.

Mechanism for Characteristic of Drain-Source Voltage Plateau
The v DS of module_D at turn-on transient is simulated by LTsipce software. The diagram of the schematic circuit for simulation is shown in Figure 12. The parasitic inductance of drain circuit loop (L D ) is also divided into two parts, which are L D and L D , respectively. The L D is the parasitic inductance belong to the partial path of drain circuit loop, which is shared with path between two test points for acquiring transient v DS , while L D is the parasitic inductance related to the other part of the drain loop.
The simulation of the influence of the V DD on voltage plateau is conducted based on the upper-side of module_D. In simulation all the parameters and conditions are same with each other, except for the condition of V DD , where V DD is set to be 100 V, 200 V, 300 V, and 400 V, respectively. The value of the parasitic inductance related to the power module and DPT rig are extracted by Q3D software, which are listed in Table 4.   Table 4.   (Figures 9b and 10b). Figure 13b shows the simulation about the influence of rise of turn-on speed and on characteristics of voltage plateau. The simulation conditions are same with that of experiments shown in Figures 10 and 11. With the rise of turn-on speed, the characteristic of voltage plateau emerges. The characteristic that the increased does not change the value of voltage plateau and just increases the lasting time for the voltage plateau, which are also observed in simulation.
These simulation results about the characteristics of in voltage platform agree with the experimental results. There is a little discrepancy of voltage fluctuation over voltage plateau between experiment (see dash line in light blue color in Figure 11b) and simulation (see the dash line in light blue color in Figure 13b). In the actual experiment the is forced into stage of voltage plateau, while the enters slowly stage of voltage plateau in simulation; secondly, the fluctuates over stage of voltage plateau more violently than that of simulations. This is due to the simplification of the simulation model, and some parasitic parameters or effects that may exist in actual experiment have not been considered.   (Figures 9b and 10b).  Figure 14 shows that during the interval of ( ), the and forward voltage drop of freewheeling diodes ( _ ) are shared by and , and the transient voltage of these two parasitic inductance (which are and , respectively) are dependent on the slew rate of .
The relationship is given by  These simulation results about the characteristics of v DS in voltage platform agree with the experimental results. There is a little discrepancy of voltage fluctuation over voltage plateau between experiment (see dash line in light blue color in Figure 11b) and simulation (see the dash line in light blue color in Figure 13b). In the actual experiment the v DS is forced into stage of voltage plateau, while the v DS enters slowly stage of voltage plateau in simulation; secondly, the v DS fluctuates over stage of voltage plateau more violently than that of simulations. This is due to the simplification of the simulation model, and some parasitic parameters or effects that may exist in actual experiment have not been considered. Figure 14 shows that during the interval of τ 1 (on), the V DD and forward voltage drop of freewheeling diodes (V F_diodes ) are shared by L D and L D , and the transient voltage of these two parasitic inductance (which are v L D and v DS , respectively) are dependent on the slew rate of i DS . The relationship is given by Before the interval of ( ), the does not rise significantly, the is the sum of and _ , since the value of _ is about 1.3 V and the value of is several hundred volts, the value of is viewed as . During ( ) , the rises rapidly, the / also rise, accordingly, the voltage over the increase, as a result that the falls. After ( ) , the freewheeling diodes enter the reverse recovery process and start to regain the reverse voltage blocking capability. The voltage is clamped to the freewheeling diodes as shown by the dash line in orange color, accordingly, the shown by the solid-line in red color and the shown by the solid-line in blue color are collapsed. When the turn-on speed is slow, as shown in Figure 14a, the miller plateau of ( ) appears after ( ), there is no any overlap between them. When turn-on speed is fast enough (e.g., more than 2.64 A/ns shown in previous experiments), as shown in Figure 14b, the interval of and ( ) have a shared sub-interval between them. This shared sub-interval in ( ) is a result caused by both fast turn-on speed and low . Before the interval of τ 1 (on), the i DS does not rise significantly, the v DS is the sum of V DD and V F_diodes , since the value of V F_diodes is about 1.3 V and the value of V DD is several hundred volts, the value of v DS is viewed as V DD . During τ 1 (on), the i DS rises rapidly, the di DS /dt also rise, accordingly, the voltage over the L D increase, as a result that the v DS falls. After τ 1 (on), the freewheeling diodes enter the reverse recovery process and start to regain the reverse voltage blocking capability. The voltage is clamped to the freewheeling diodes as shown by the dash line in orange color, accordingly, the v DS shown by the solid-line in red color and the v L D shown by the solid-line in blue color are collapsed.
When the turn-on speed is slow, as shown in Figure 14a, the miller plateau of v gs (V GP ) appears after τ 1 (on), there is no any overlap between them. When turn-on speed is fast enough (e.g., more than 2.64 A/ns shown in previous experiments), as shown in Figure 14b, the interval of V GP and τ 1 (on) have a shared sub-interval between them. This shared sub-interval in τ 1 (on) is a result caused by both fast turn-on speed and low V DD .
In order to figure out the effect of this overlap between τ 1 (on) and GP on characteristics of drain-source voltage plateau, the simulation results about the slew rate of i DS are analyzed in detail. Figure 15 shows that the di DS /dt has a characteristic of plateau in this shared sub-interval by V GP and τ 1 (on). Since the tiny change in di DS /dt (just 0.4 A/ns) in this shared sub-interval, the voltage over the inductance of L D changes by about 3.2 V in this shared sub-interval. Compared with the significant drop of v DS in both the initial stage of τ 1 (on) and the whole τ 2 (on), the falling of v DS in this shared sub-interval is negligible, so that the characteristic of voltage plateau is observed in v DS . drain-source voltage plateau, the simulation results about the slew rate of are analyzed in detail. Figure 15 shows that the / has a characteristic of plateau in this shared sub-interval by and ( ). Since the tiny change in / (just 0.4 A/ns) in this shared sub-interval, the voltage over the inductance of ′ changes by about 3.2 V in this shared sub-interval. Compared with the significant drop of in both the initial stage of ( ) and the whole ( ), the falling of in this shared sub-interval is negligible, so that the characteristic of voltage plateau is observed in .
During the GP interval, the miller capacitance discharges firstly, then charges reversely by gate current, the most of gate current goes through instead of , hence, the voltage of rise so slowly and voltage plateau appears in , so that the / varies little.
According to Equation (5), the / is determined by / during the shared sub-interval by ( ) and GP, therefore, the / changes little and appear the characteristic of voltage plateau in . After the moment corresponding to Point_1, the freewheeling diodes enter the reverse recovery process and start to regain the reverse voltage blocking capability. Consequently, the voltage is clamped to the freewheeling diodes, so that the effect of on the / is not reflected on , therefore, the characteristics of drain-source voltage plateau will end at the moment when rises to . However, if the increases, this shared sub-interval will be extended, accordingly, the characteristics of voltage plateau in will also be prolonged. As shown in Figure 15b, when approaching to the end of interval ( ), with the change of / rises, the rise in voltage over results in the voltage over reduces, as a result that the characteristic of Point_1 is weakened. Figure 16 shows the simulation results about the influence of the increased on characteristics of voltage plateau in , where is set to be 400 V, is set to be 2.4 Ω, and is set to be 100 A. The increased generates the higher / over the during the conduction of freewheeling diodes, the freewheeling current in loop_① transfer faster to loop_②, on the other hand, the increased accelerates the turn-on, due to the smaller input parasitic capacitance under high , the can rise to a higher voltage then falls to miller plateau, this higher cause the current of SiC-MOSFETs rises in a higher speed. As shown in Figure 16b, the ( ) is shortened and is delayed, so that the interval of is separated with ( ). As a During the shared sub-interval by τ 1 (on) and GP, SiC-MOSFET dies operate in saturation region, where v gs > V TH and v DS > v gs − V TH , the drain-source current of SiC-MOSFET dies is given by where g f s is trans-conductance of SiC-MOSFET dies. Derivate the Equation (4) from time, we can get During the GP interval, the miller capacitance discharges firstly, then charges reversely by gate current, the most of gate current goes through C gd instead of C gs , hence, the voltage of C gs rise so slowly and voltage plateau appears in v gs , so that the dv gs /dt varies little.
According to Equation (5), the di DS /dt is determined by dv gs /dt during the shared sub-interval by τ 1 (on) and GP, therefore, the di DS /dt changes little and appear the characteristic of voltage plateau in v DS .
After the moment corresponding to Point_1, the freewheeling diodes enter the reverse recovery process and start to regain the reverse voltage blocking capability. Consequently, the voltage is clamped to the freewheeling diodes, so that the effect of V GP on the di DS /dt is not reflected on v DS , therefore, the characteristics of drain-source voltage plateau will end at the moment when i DS rises to I O . However, if the I O increases, this shared sub-interval will be extended, accordingly, the characteristics of voltage plateau in v DS will also be prolonged.
As shown in Figure 15b, when approaching to the end of interval τ 1 (on), with the change of di DS /dt rises, the rise in voltage over L D results in the voltage over L D reduces, as a result that the characteristic of Point_1 is weakened. Figure 16 shows the simulation results about the influence of the increased V DD on characteristics of voltage plateau in v DS , where V DD is set to be 400 V, R gext is set to be 2.4 Ω, and I O is set to be 100 A. The increased V DD generates the higher di DS /dt over the L D during the conduction of freewheeling diodes, the freewheeling current in loop_ 1 transfer faster to loop_ 2 , on the other hand, the increased V DD accelerates the turn-on, due to the smaller input parasitic capacitance under high v DS , the v gs can rise to a higher voltage then falls to miller plateau, this higher v gs cause the current of SiC-MOSFETs rises in a higher speed. As shown in Figure 16b, the τ 1 (on) is shortened and V GP is delayed, so that the interval of V GP is separated with τ 1 (on). As a result, the effect of miller plateau of v gs on di DS /dt is not reflected in characteristics of v DS , the characteristics of voltage plateau is not developed in v DS , furthermore, the characteristic of Point_1 becomes less obvious.
result, the effect of miller plateau of on / is not reflected in characteristics of , the characteristics of voltage plateau is not developed in , furthermore, the characteristic of Point_1 becomes less obvious.

Mechanism for Difference of Drain-Source Voltage Plateau between Upper-Side and Lower-Side
The previous experimental results show us that the measured in voltage plateau for the upper-side is higher than that of lower-side by 50 V in of 200 V, and 25 V in of 100 V. This difference is related to the distinct parasitic inductance in measuring the . The physical outline and locations of power terminals for the developed module are fixed as shown in Figure 1. When measuring the of upper-side the test probe is connected to the power terminals of "DC+" and "AC", while, when measuring the of the lower-side, the probe is connected to the terminals of "AC" and "DC-" in the DPT experiment. Figure 17 illustrates the design of inner routings of the developed module_D, the red-color indicated routings from terminal of "DC+" to terminal of "AC" and the related DBC (direct bonding copper) form the path of upper-side, while the green-color indicated routings from terminal of "AC" to terminal of "DC-" and the related DBC form the path of lower-side when measuring . The path of upper-side is significantly different from the one of the lower-side inside the module when measuring . The path of drain circuit loop inside module_D consists of the routings from terminal of "DC+" to terminal of "DC−" and the related DBC. It is obvious that the partial path of drain circuit loop shared with the path of upper-side is different from the one shared with the path of lower-side inside the module. The parasitic inductance of these shared paths between upper-side and lower-side are also different from each other, which is denoted by the _ and _ , respectively. The value

Mechanism for Difference of Drain-Source Voltage Plateau between Upper-Side and Lower-Side
The previous experimental results show us that the measured v DS in voltage plateau for the upper-side is higher than that of lower-side by 50 V in V DD of 200 V, and 25 V in V DD of 100 V. This difference is related to the distinct parasitic inductance in measuring the v DS . The physical outline and locations of power terminals for the developed module are fixed as shown in Figure 1. When measuring the v DS of upper-side the test probe is connected to the power terminals of "DC+" and "AC", while, when measuring the v DS of the lower-side, the probe is connected to the terminals of "AC" and "DC-" in the DPT experiment. Figure 17 illustrates the design of inner routings of the developed module_D, the red-color indicated routings from terminal of "DC+" to terminal of "AC" and the related DBC (direct bonding copper) form the path of upper-side, while the green-color indicated routings from terminal of "AC" to terminal of "DC-" and the related DBC form the path of lower-side when measuring v DS . The path of upper-side is significantly different from the one of the lower-side inside the module when measuring v DS .
Energies 2020, 13, x FOR PEER REVIEW 15 of 18 result, the effect of miller plateau of on / is not reflected in characteristics of , the characteristics of voltage plateau is not developed in , furthermore, the characteristic of Point_1 becomes less obvious.

Mechanism for Difference of Drain-Source Voltage Plateau between Upper-Side and Lower-Side
The previous experimental results show us that the measured in voltage plateau for the upper-side is higher than that of lower-side by 50 V in of 200 V, and 25 V in of 100 V. This difference is related to the distinct parasitic inductance in measuring the . The physical outline and locations of power terminals for the developed module are fixed as shown in Figure 1. When measuring the of upper-side the test probe is connected to the power terminals of "DC+" and "AC", while, when measuring the of the lower-side, the probe is connected to the terminals of "AC" and "DC-" in the DPT experiment. Figure 17 illustrates the design of inner routings of the developed module_D, the red-color indicated routings from terminal of "DC+" to terminal of "AC" and the related DBC (direct bonding copper) form the path of upper-side, while the green-color indicated routings from terminal of "AC" to terminal of "DC-" and the related DBC form the path of lower-side when measuring . The path of upper-side is significantly different from the one of the lower-side inside the module when measuring . The path of drain circuit loop inside module_D consists of the routings from terminal of "DC+" to terminal of "DC−" and the related DBC. It is obvious that the partial path of drain circuit loop shared with the path of upper-side is different from the one shared with the path of lower-side inside the module. The parasitic inductance of these shared paths between upper-side and lower-side are also different from each other, which is denoted by the _ and _ , respectively. The value The path of drain circuit loop inside module_D consists of the routings from terminal of "DC+" to terminal of "DC−" and the related DBC. It is obvious that the partial path of drain circuit loop shared with the path of upper-side is different from the one shared with the path of lower-side inside the module. The parasitic inductance of these shared paths between upper-side and lower-side are also different from each other, which is denoted by the L D_upper and L D_lower , respectively. The value of the L D_upper and L D_lower , were extracted by Q3D software, as shown in Table 4, in which the value of L D_upper is higher than that of L D_lower . Based on the circuit schematic shown in Figure 12 and the distinct L D which is the L D_upper for upper-side and L D_lower for lower-side, the turn-on transient waveforms of v DS for module_D are simulated by LTspice under the condition that the V DD is set to be 100 V, the I O is set to be 100 A, and the R gext is set to be 2.4 Ω. The other parameters for simulation are the same as that of the experiments shown in Figure 10 and Table 2, as well as Table 4. Figure 18 shows the simulation result about the difference of characteristics of drain-source voltage between upper-side and lower-side caused by the special structure of the module. The characteristics of voltage plateau in v DS are observed in both the upper-side and lower-side. The simulation results about the difference in the values of drain-source voltage plateau between the upper-side and lower-side is very near to the experimental result of 25 V shown in Figure 10b.
Energies 2020, 13, x FOR PEER REVIEW 16 of 18 of the _ and _ , were extracted by Q3D software, as shown in Table 4, in which the value of _ is higher than that of _ . Based on the circuit schematic shown in Figure 12 and the distinct which is the _ for upper-side and _ for lower-side, the turn-on transient waveforms of for module_D are simulated by LTspice under the condition that the is set to be 100 V, the is set to be 100 A, and the is set to be 2.4 Ω. The other parameters for simulation are the same as that of the experiments shown in Figure 10 and Table 2, as well as Table 4. Figure 18 shows the simulation result about the difference of characteristics of drain-source voltage between upper-side and lower-side caused by the special structure of the module. The characteristics of voltage plateau in are observed in both the upper-side and lower-side. The simulation results about the difference in the values of drain-source voltage plateau between the upper-side and lower-side is very near to the experimental result of 25 V shown in Figure 10b. Though the voltage plateau of in the lower-side is not as flat as that of the upper-side and has a slow downward trend, there is difference of characteristics of in the lower-side between experiment and simulation. We can see the similar characteristic in previous experiment shown in dash line in black color for lower-side under condition of equals to 5 Ω in Figure 10b. Therefore, the characteristic of voltage plateau in for the lower-side in simulation is normal, while the discrepancy in voltage plateau characteristic for of the lower-side between the experiment and simulation is probably attributed to the difference of test conditions caused by the simplification of the simulation.
In summary, the experimental results are confirmed by simulation that the combined impacts of fast turn-on speed and low causes characteristic of voltage plateau in at turn-on transient. Moreover, the special structure design of the developed module with the standard 62 mm package outline between upper-side and lower-side lead to different characteristics of characteristic of voltage plateau in of each other. The characteristic that the rise of does not change the value of voltage plateau and just prolongs the voltage plateau is also confirmed by simulation.
The voltage plateau happens at different values for the upper-side and lower-side, which is verified by simulation. The difference is attributed to the discrepancy of structure in the corresponding partial path of drain circuit loop inside SiC high-power module with the standard 62 mm package outline when measuring of upper-side and lower-side.

Conclusions
In this work, the characteristics of drain-source voltage at turn-on transient for the fabricated SiC high power modules are investigated under various test conditions (i.e., various DC bus voltages and turn-on speeds), and the characteristic of the drain-source voltage plateau is observed under the combined condition of fast turn-on speed and low DC bus voltage. The mechanisms behind the voltage plateau characteristics are studied via experiments and simulations. Though the voltage plateau of v DS in the lower-side is not as flat as that of the upper-side and has a slow downward trend, there is difference of characteristics of v DS in the lower-side between experiment and simulation. We can see the similar characteristic in previous experiment shown in dash line in black color for lower-side under condition of R gext equals to 5 Ω in Figure 10b. Therefore, the characteristic of voltage plateau in v DS for the lower-side in simulation is normal, while the discrepancy in voltage plateau characteristic for v DS of the lower-side between the experiment and simulation is probably attributed to the difference of test conditions caused by the simplification of the simulation.
In summary, the experimental results are confirmed by simulation that the combined impacts of fast turn-on speed and low V DD causes characteristic of voltage plateau in v DS at turn-on transient. Moreover, the special structure design of the developed module with the standard 62 mm package outline between upper-side and lower-side lead to different characteristics of characteristic of voltage plateau in v DS of each other. The characteristic that the rise of I O does not change the value of voltage plateau and just prolongs the voltage plateau is also confirmed by simulation.
The voltage plateau happens at different v DS values for the upper-side and lower-side, which is verified by simulation. The difference is attributed to the discrepancy of structure in the corresponding partial path of drain circuit loop inside SiC high-power module with the standard 62 mm package outline when measuring v DS of upper-side and lower-side.

Conclusions
In this work, the characteristics of drain-source voltage at turn-on transient for the fabricated SiC high power modules are investigated under various test conditions (i.e., various DC bus voltages and turn-on speeds), and the characteristic of the drain-source voltage plateau is observed under the combined condition of fast turn-on speed and low DC bus voltage. The mechanisms behind the voltage plateau characteristics are studied via experiments and simulations.
Under the condition of fast turn-on speed and low DC bus voltage, there is a shared sub-interval by the interval of miller plateau for gate-source voltage and the interval of τ 1 (on) for drain-source voltage,