A Three-Level DC-Link Quasi-Switch Boost T-Type Inverter with Voltage Stress Reduction

: In recent years, the three-level T-Type inverter has been considered the best choice for many low and medium power applications. Nevertheless, this topology is known as a buck converter. Therefore, in this paper, a new topology incorporating the dc-link type quasi-switched boost network with the traditional three-level T-type inverter is proposed to overcome the limit of traditional three-level T-Type inverter. The space vector pulse width modulation scheme is considered to control this topology, which provides some beneﬁts such as enhancing modulation index and reducing the magnitude of common-mode voltage. For this scheme, the zero, medium, and large vectors are utilized to generate the output voltage. The shoot-through state which is adopted by turning on all power switches of inverter leg is inserted into zero vector to boost the dc-link voltage. As a result, there is no distortion at the output waveform. The control signal of intermediate network power switches is also detailed to improve the boost factor and voltage gain. As a result, the voltage stress on power devices like capacitors, diodes, and switches is decreased signiﬁcantly. To demonstrate the outstanding of proposed structure and its control strategy, some comparisons between the proposed method and other ones are performed. Simulation and experimental prototype results are conducted to verify the accuracy of the theory and e ﬀ ectiveness of the inverter.


Introduction
Recently, the multilevel inverters (MIs) have been widely used for industrial applications due to their advantages such as better output voltage quality, smaller low-pass filter size requirement, and the lower voltage stress on switching devices compared to the two-level inverters [1,2]. There are three basic topologies of MIs which are neutral point clamped (NPC) inverter, cascade, and flying capacitor (FC) inverter. Nevertheless, these topologies use plenty passive components such as diodes for NPC structure, capacitors for FC configuration, or isolate dc input sources for cascade form of the inverter. Thus, these configurations produce high system size, cost, and power loss, which are not suitable for low and medium voltage applications [1][2][3]. For that reason, the three-level T-type inverter (3L-T 2 I) was explored to replace conventional MIs to provide superior in low and medium voltage applications [1][2][3]. These topologies have both particular advantages and disadvantages, but the same drawback of these is inability to operate under shoot-through (ST) condition which is generated when all switches in any phase leg are triggered on simultaneously. Besides, traditional topologies behave as a buck converter which produce output voltage where the peak-peak value is smaller than the dc-link voltage.
In [33,34], a new topology of the qSB network known as the dc-link type of the qSB (DqSB) was discussed. This topology with the modified PWM control method reduced the stress on the capacitor as well as enhancing the voltage gain. As a result, the stress on power devices of the intermediate network was decreased significantly. Similar to [28][29][30][31][32], in [33,34], two coefficients were used to control the boost factor of the converter. Therefore, this topology is also flexible to control and enables operation under a large input voltage range.
In this paper, a combination of the DqSB network with 3L-T 2 I is introduced. The PWM strategy is based on the SVP which uses zero vector, medium vectors, and large vectors to generate a reference vector that provides CMV reduction capability. The operation principle and theory analysis are also detailed in this paper. The advantages of this configuration are demonstrated by comparing it to other topologies and schemes. The simulation and experimental results are shown to validate the effectiveness of the proposed structure. The advantages of the proposed three-level DC-link type quasi switch boost T-type inverter (3L-DqSBT 2 I) scheme over the conventional three-level quasi switch boost T-type inverter (3L-qSBT 2 I) scheme are as follows: The boost factor and voltage gain are improved compared to the conventional 3L-qSBT 2 I. The modulation index is increased by adopting SVP technique. The voltage stress on power devices like capacitors, diodes, and switches is decreased significantly. The magnitude of CMV is reduced compared to the conventional 3L-qSBT 2 I.
The rest of this paper is divided into four parts. Section 2 shows the introduced topology with its PWM control strategy. Section 3 presents the comparison of the proposed structure to others to demonstrate the effectiveness of introduced topology. Section 4 presents the simulation and experimental results to verify the accuracy of the introduced structure. Section 5 shows the summary of this paper.

Three-Level DC-Link Type Quasi-Switched Boost T-Type Inverter Topology
The 3L-DqSBT 2 I topology consists of an intermediate network and an inverter leg. The DqSB network is used to connect the input voltage with the 3L-T 2 I structure to boost the dc-link voltage, as illustrated in Figure 1. The input power supply is split into two equal sources. Each source feeds to an identical DqSB network, which consists of one inductor, one capacitor, two diodes, and one active switch. The 3L-T 2 I topology is the same as conventional MIs topology which can generate a three-level voltage at output terminal which are +V PN /2, zero, and −V PN /2 which correspond to "P" state, "O" state, and "N" state, respectively, where V PN is the dc-link voltage of the inverter. The output of the inverter feeds to the three-phase resistor load through a three-phase low pass filter (LC filter) to improve the quality of output load voltage as well as the output load current.
Energies 2020, 13, x FOR PEER REVIEW 3 of 20 as well as enhancing the voltage gain. As a result, the stress on power devices of the intermediate network was decreased significantly. Similar to [28][29][30][31][32], in [33,34], two coefficients were used to control the boost factor of the converter. Therefore, this topology is also flexible to control and enables operation under a large input voltage range. In this paper, a combination of the DqSB network with 3L-T 2 I is introduced. The PWM strategy is based on the SVP which uses zero vector, medium vectors, and large vectors to generate a reference vector that provides CMV reduction capability. The operation principle and theory analysis are also detailed in this paper. The advantages of this configuration are demonstrated by comparing it to other topologies and schemes. The simulation and experimental results are shown to validate the effectiveness of the proposed structure. The advantages of the proposed three-level DC-link type quasi switch boost T-type inverter (3L-DqSBT 2 I) scheme over the conventional three-level quasi switch boost T-type inverter (3L-qSBT 2 I) scheme are as follows:


The boost factor and voltage gain are improved compared to the conventional 3L-qSBT 2 I.  The modulation index is increased by adopting SVP technique.  The voltage stress on power devices like capacitors, diodes, and switches is decreased significantly.  The magnitude of CMV is reduced compared to the conventional 3L-qSBT 2 I.
The rest of this paper is divided into four parts. Section 2 shows the introduced topology with its PWM control strategy. Section 3 presents the comparison of the proposed structure to others to demonstrate the effectiveness of introduced topology. Section 4 presents the simulation and experimental results to verify the accuracy of the introduced structure. Section 5 shows the summary of this paper.

Three-Level DC-Link Type Quasi-Switched Boost T-Type Inverter Topology
The 3L-DqSBT 2 I topology consists of an intermediate network and an inverter leg. The DqSB network is used to connect the input voltage with the 3L-T 2 I structure to boost the dc-link voltage, as illustrated in Figure 1. The input power supply is split into two equal sources. Each source feeds to an identical DqSB network, which consists of one inductor, one capacitor, two diodes, and one active switch. The 3L-T 2 I topology is the same as conventional MIs topology which can generate a threelevel voltage at output terminal which are +VPN/2, zero, and −VPN/2 which correspond to "P" state, "O" state, and "N" state, respectively, where VPN is the dc-link voltage of the inverter. The output of the inverter feeds to the three-phase resistor load through a three-phase low pass filter (LC filter) to improve the quality of output load voltage as well as the output load current.

Operating Principles
Similar to other single-state inverter topologies, this structure also operates under two main modes which are NST and ST modes. In NST mode, the 3L-T 2 I circuit can produce a three-level voltage at the output terminal by triggering corresponding switches as shown in Table 1. When S x1 is switched on, the output voltage is achieved +V PN /2 which is the half of dc-link voltage generated by the DqSB network. While the output voltage obtains −V PN /2 when S x3 is turned on. The zero value is produced at output voltage when S x2 is triggered on. The NST mode consists of two sub-modes which are NST 1 and NST 2, as presented in Figure 2. The ST mode is achieved when all switches in the inverter leg are triggered on, as a result, the output load voltage in this time interval is zero. Therefore, in order to decrease the waveform distortion at the output, the ST signal is inserted within the time interval when the output voltage is zero. Table 1. Switching states of 3L-DqSBT 2 I (x = a, b, c).

Mode ON Switches ON Diodes
Energies 2020, 13, x FOR PEER REVIEW 4 of 20

Operating Principles
Similar to other single-state inverter topologies, this structure also operates under two main modes which are NST and ST modes. In NST mode, the 3L-T 2 I circuit can produce a three-level voltage at the output terminal by triggering corresponding switches as shown in Table 1. When Sx1 is switched on, the output voltage is achieved +VPN/2 which is the half of dc-link voltage generated by the DqSB network. While the output voltage obtains -VPN/2 when Sx3 is turned on. The zero value is produced at output voltage when Sx2 is triggered on. The NST mode consists of two sub-modes which are NST 1 and NST 2, as presented in Figure 2. The ST mode is achieved when all switches in the inverter leg are triggered on, as a result, the output load voltage in this time interval is zero. Therefore, in order to decrease the waveform distortion at the output, the ST signal is inserted within the time interval when the output voltage is zero.  In NST 1 as shown in Figure 2b, the switches SP and SN are triggered on. Therefore, the diode D1P and D1N are reversed bias whereas diode D2P and D2N are forward bias. The inductors LP and LN are short circuit by active switches and diodes D2P and D2N of the DqSB network. As a result, the current through two inductors is kept constant. The voltages across two inductors are expressed as: In NST 2 as shown in Figure 2c, the switches SP and SN are triggered off, all diodes of the intermediate network are forward bias. As a result, the capacitors CP and CN are charged from LP and LN, respectively. The voltages of these inductors are calculated as: In NST 1 as shown in Figure 2b, the switches S P and S N are triggered on. Therefore, the diode D 1P and D 1N are reversed bias whereas diode D 2P and D 2N are forward bias. The inductors L P and L N are short circuit by active switches and diodes D 2P and D 2N of the DqSB network. As a result, the current through two inductors is kept constant. The voltages across two inductors are expressed as: In NST 2 as shown in Figure 2c, the switches S P and S N are triggered off, all diodes of the intermediate network are forward bias. As a result, the capacitors C P and C N are charged from L P and L N , respectively. The voltages of these inductors are calculated as: In ST mode, all switches of 3L-T 2 I are turned on, simultaneously. As a result, the diodes D 1P and D 1N are forward bias whereas diodes D 2P and D 2N are reversed bias. The inductors L P and L N store energy from the input power source. The voltages of two inductors are expressed as:

SVP Scheme to Reduce CMV
In [2,30,32] the authors figured out that the CMV causes some problems in power systems such as electromagnetic interference or bearing current and shaft voltage, etc. Thus, CMV reduction is necessary to enhance the reliability of the system. The CMV generated by the inverter is identified as: where V AO , V BO , and V CO are three-phase output pole voltage. Based on Equation (4), the magnitude of CMV can be limited from −V PN /6 to +V PN /6 by using only zero vector, medium vectors, and large vectors to synthesize the reference vector during operation of the inverter [2,32]. Thus, the space vector diagram of the three-level inverter is divided into 12 sectors to analyze the operation of the converter, as shown in Figure 3. In ST mode, all switches of 3L-T 2 I are turned on, simultaneously. As a result, the diodes D1P and D1N are forward bias whereas diodes D2P and D2N are reversed bias. The inductors LP and LN store energy from the input power source. The voltages of two inductors are expressed as:

SVP Scheme to Reduce CMV
In [2,30,32] the authors figured out that the CMV causes some problems in power systems such as electromagnetic interference or bearing current and shaft voltage, etc. Thus, CMV reduction is necessary to enhance the reliability of the system. The CMV generated by the inverter is identified as: where VAO, VBO, and VCO are three-phase output pole voltage. Based on Equation (4), the magnitude of CMV can be limited from -VPN/6 to +VPN/6 by using only zero vector, medium vectors, and large vectors to synthesize the reference vector during operation of the inverter [2,32]. Thus, the space vector diagram of the three-level inverter is divided into 12 sectors to analyze the operation of the converter, as shown in Figure 3.
[PNN] [  In general, assuming that the reference vector ( ) is located in sector 1 or sector 2, the is synthesized as follows: Case 1: When the is located in sector 1, the , , and are adopted to generate the . Thus, the relationship between these vectors can be expressed as: where, , , -zero vector, large vector, and medium vector, respectively,  In general, assuming that the reference vector ( → V re f ) is located in sector 1 or sector 2, the → V re f is synthesized as follows: Thus, the relationship between these vectors can be expressed as: where, → V re f -reference vector, Similar to [2], the drew-time of each vector can be expressed as: Case 2: Similar to sector 1, for sector 2, the → V re f can be expressed as: The drew-time of can be identified as [2]: Not similar to the study of [2] which only used the ST signal to boost the dc-link voltage, this topology also uses the active switches of the DqSB network to enhance the dc source. Thus, the switching sequence for sector 1 and sector 2, the ST insertion, and the control signal of DqSB's switches are reselected, as shown in Figure 4. Similar to [2], the drew-time of each vector can be expressed as: Case 2: Similar to sector 1, for sector 2, the can be expressed as: The drew-time of , , and can be identified as [2]: Not similar to the study of [2] which only used the ST signal to boost the dc-link voltage, this topology also uses the active switches of the DqSB network to enhance the dc source. Thus, the switching sequence for sector 1 and sector 2, the ST insertion, and the control signal of DqSB's switches are reselected, as shown in Figure 4.
By applying this way to other sectors, the drew-time of each vector as well as the switching sequence can be easily identified.

Steady-State Analysis
In  By applying this way to other sectors, the drew-time of each vector as well as the switching sequence can be easily identified.

Steady-State Analysis
In one period of switching (T), the time interval of ST state is (D ST ·T), while (D 0 ·T) is the time interval of NST 1. Therefore, the value (1 − D ST − D 0 )T is the time interval of NST 2. Applying the volt-second balance for two inductors L P and L N with the note that (V CP = V CN = V C ), the voltages across these capacitors can be calculated as: The inductor current ripple is calculated as: where, (1) ∆I LP , ∆I LN -inductor current ripples of L P and L N , respectively, (2) f -switching frequency of the inverter, (3) D ST -ST duty ratio, (4) D 0 -duty cycle of S P and S N .
The peak value of dc-link voltage (V PN ) is the sum of two capacitors voltage and the dc input source, which is identified as: Based on Equation (11) the boost factor (B) can be calculated as: The peak value of first harmonic of output phase voltage (V x,peak ) can be identified as: The voltage gain (G) of the converter is expressed as: The relationship between modulation index, the ST duty ratio, and the duty cycle of DqSB's switches are illustrated as:

Comparison to Other Configurations
To validate the accuracy of the proposed topology and its PWM control method, some investigations about boost factor, voltage gain, and voltage stress on power devices are conducted for the ZS inverter (ZSI) proposed in [8], the qZS inverter (qZSI) introduced in [2,19], the qSB inverter (qSBI) with two sources and two inductors proposed in [35], the qSBI with reducing number of sources and inductors in [36], and the proposed 3L-DqSBT 2 I. Table 2 presents the overall comparison between 3L-DqSBT 2 I and other topologies. It can be seen that the qZSI uses the largest number of passive components (four inductors and four capacitors), while the ZSI, the qSBI in [35], and the 3L-DqSBT 2 I save two inductors and two capacitors compared to the qZSI. The qSB in [36] uses the smallest number of passive components for the intermediate network which just has one inductor and two capacitors. While, the diode and active switch of the qSBI and the 3L-DqSBT 2 I are used more than the ZSI and qZSI. Two active switches and four diodes are used for both the qSBI and the 3L-DqSBT 2 I, while the ZSI and qZSI just use two diodes, as shown in Table 2. Table 2. Comparison between 3L-DqSBT 2 I with other configurations and PWM methods.
ZSI in [8] qZSI with PWM in [19] qZSI with PWM in [2] qSBI with PWM in [34] qSBI with PWM in [35] Proposed 3L-DqSBT 2 I Switch voltage stress,  Figure 5 shows the investigations about boost factor versus ST duty ratio and the voltage gain versus modulation index for these topologies and PWM methods, and it is noted that the modulation index is set to (1 − D ST ) to achieve the highest voltage gain for each scheme. As illustrated in Figure 5a, the boost factor of the 3L-DqSBT 2 I depends on two coefficients which are the duty cycle of the DqSB network's active switches (D 0 ) and the ST duty ratio (D ST ). With the increase of D 0 , the boost factor of the 3L-DqSBT 2 I is increased, whereas the boost factor of other topologies is just up to the D ST . When the value 0.5 is applied to D 0 , the 3L-DqSBT 2 I produces the same boost factor to the other configurations. However, by applying the SVP method, the voltage gain of the ZSI in [8], and the qZSI in [2], the 3L-DqSBT 2 I has the larger voltage gain which is 2/ √ 3 times larger than the others, as illustrated in Figure 5b. Similar to the boost factor versus the ST duty ratio, the 3L-DqSBT 2 I just provides superior in voltage gain when D 0 > 0.5. For that reason, in this paper, the value 0.6 was selected for coefficient D 0 as an example to analyze the effectiveness of the proposed topology.   [19] qZSI with PWM in [2] qSBI with PWM in [34] qSBI with PWM in [35] Proposed 3L-  Figure 5 shows the investigations about boost factor versus ST duty ratio and the voltage gain versus modulation index for these topologies and PWM methods, and it is noted that the modulation index is set to (1 − DST) to achieve the highest voltage gain for each scheme. As illustrated in Figure  5a, the boost factor of the 3L-DqSBT 2 I depends on two coefficients which are the duty cycle of the DqSB network's active switches (D0) and the ST duty ratio (DST). With the increase of D0, the boost factor of the 3L-DqSBT 2 I is increased, whereas the boost factor of other topologies is just up to the DST. When the value 0.5 is applied to D0, the 3L-DqSBT 2 I produces the same boost factor to the other configurations. However, by applying the SVP method, the voltage gain of the ZSI in [8], and the qZSI in [2], the 3L-DqSBT 2 I has the larger voltage gain which is 2/√3 times larger than the others, as illustrated in Figure 5b. Similar to the boost factor versus the ST duty ratio, the 3L-DqSBT 2 I just provides superior in voltage gain when D0 > 0.5. For that reason, in this paper, the value 0.6 was selected for coefficient D0 as an example to analyze the effectiveness of the proposed topology.  Figure 6 shows the investigations of voltage stress on power components such as capacitor voltage stress, diode voltage stress, and switch voltage stress with the note that there are four capacitors in the qZSI with unequal voltage stress on their, as shown in Table 2. Thus, this comparison was conducted for each capacitor of the qZSI. Furthermore, the diode voltage stress of each diode of the qSBI and 3L-DqSBT 2 I is also not equal to each other. Therefore, the investigation was also carried  Figure 6 shows the investigations of voltage stress on power components such as capacitor voltage stress, diode voltage stress, and switch voltage stress with the note that there are four capacitors in the qZSI with unequal voltage stress on their, as shown in Table 2. Thus, this comparison was conducted for each capacitor of the qZSI. Furthermore, the diode voltage stress of each diode of the qSBI and 3L-DqSBT 2 I is also not equal to each other. Therefore, the investigation was also carried out for each diode. As presented in Figure 6a, the qZSI is superior in capacitor voltage stress for both methods in [2,19], while the qSBI produces higher voltage stress on the capacitor than the ZSI. In general, the proposed 3L-DqSBT 2 I is better than the ZSI and qSBI. Moreover, in the range of low voltage gain, the 3L-DqSBT 2 I is also better than the qZSI. Furthermore, all diodes of 3L-DqSBT 2 I have less voltage stress compared to other configurations, as shown in Figure 6b. This figure also points out that the qZSI is better than ZSI about voltage stress on diodes with the same voltage gain value. As the impedance-source networks in [2,8,19] do not have any active switches, the ZSI and qZSI are not considered to investigate for switch voltage stress which is shown in Figure 6c. As the voltage stress of the active switch is equal to the capacitor voltage, the 3L-DqSBT 2 I has less voltage stress on the switch than the qSBI.
Energies 2020, 13, x FOR PEER REVIEW 9 of 20 out for each diode. As presented in Figure 6a, the qZSI is superior in capacitor voltage stress for both methods in [2,19], while the qSBI produces higher voltage stress on the capacitor than the ZSI. In general, the proposed 3L-DqSBT 2 I is better than the ZSI and qSBI. Moreover, in the range of low voltage gain, the 3L-DqSBT 2 I is also better than the qZSI. Furthermore, all diodes of 3L-DqSBT 2 I have less voltage stress compared to other configurations, as shown in Figure 6b. This figure also points out that the qZSI is better than ZSI about voltage stress on diodes with the same voltage gain value.
As the impedance-source networks in [2,8,19] do not have any active switches, the ZSI and qZSI are not considered to investigate for switch voltage stress which is shown in Figure 6c. As the voltage stress of the active switch is equal to the capacitor voltage, the 3L-DqSBT 2 I has less voltage stress on the switch than the qSBI.

Simulation Results
The accuracy of the proposed inverter was validated by simulation results with the help of PSIM software. The parameters used for simulation are listed in Table 3. Before feeding to three-phase resistor load, the three-phase low pass filter was used to mitigate the magnitude of high-frequency harmonics. To produce a root mean square (RMS) output phase voltage of 110 V from the input

Simulation Results
The accuracy of the proposed inverter was validated by simulation results with the help of PSIM software. The parameters used for simulation are listed in Table 3. Before feeding to three-phase resistor load, the three-phase low pass filter was used to mitigate the magnitude of high-frequency harmonics. To produce a root mean square (RMS) output phase voltage of 110 V from the input voltage of 200 V, the modulation index was 0.85. Thus, from Equation (15) the ST duty cycle must be 0.15.   Table 3, the capacitor voltages (V CP and V CN ) are boosted to 60 V from 200 V of the dc input source, as illustrated in Figure 7. Therefore, the peak value of dc-link voltage can be identified as 320 V by summing the capacitor voltages and the input voltage. The peak-peak value of output pole voltage is equal to the dc-link voltage which has three levels: 160 V (+V PN /2), zero, and −160 V (−V PN /2), as shown in Figure 7. The output phase voltage has seven levels and its peak-peak value is varied from −2/3V PN to +2/3V PN , as shown in Figure 7. By using the modulation index of 0.85, the peak value of the first order harmonic of output phase voltage is 156 V, approximately, as presented in Figure 7. The THD value of output phase voltage is 54.59%, which is measured by using the harmonic spectrum in Figure 7.    Figure 8 from top to bottom presents the simulation results for dc-link voltage, line-line voltage, and CMV. By using the full ST insertion, the dc-link voltage is varied from zero to the peak-value of dc-link voltage which is 320 V achieved in NST mode. The peak value of output line-line voltage is equal to dc-link voltage, so the top part of V AB is varied from zero to 320 V, as illustrated in Figure 8. The old sectors of space vector diagram produce CMV varying from 0 to −V PN /6, whereas the even sectors produce the CMV which varies from 0 to +V PN /6. Therefore, when applying the introduced method, the CMV frequency is three times larger than the output voltage, and the peak-peak value of it is equal to V PN /3 which varies from −V PN /6 to +V PN /6. The RMS value of CMV is 32.7 V RMS .  Figure 8 from top to bottom presents the simulation results for dc-link voltage, line-line voltage, and CMV. By using the full ST insertion, the dc-link voltage is varied from zero to the peak-value of dc-link voltage which is 320 V achieved in NST mode. The peak value of output line-line voltage is equal to dc-link voltage, so the top part of VAB is varied from zero to 320 V, as illustrated in Figure 8. The old sectors of space vector diagram produce CMV varying from 0 to −VPN/6, whereas the even sectors produce the CMV which varies from 0 to +VPN/6. Therefore, when applying the introduced method, the CMV frequency is three times larger than the output voltage, and the peak-peak value of it is equal to VPN/3 which varies from −VPN/6 to +VPN/6. The RMS value of CMV is 32.7 VRMS.   Figure 9 from top to bottom shows the simulation results of the inductor current, three-phase output load voltage, and three-phase output load current. The inductor currents of two inductors are equal to each other. The average value of inductor currents is 11.7 and 11.6 A for I LP and I LN , respectively. Due to applying the low-pass filter before the resistor load, the output load voltage, as well as the output load current, have a good quality. The THD value of these waveforms is 2.38% for both voltage and current waveforms. The RMS value of output load voltage and output load current are 111 V RMS and 2.78 A RMS .
Energies 2020, 13, x FOR PEER REVIEW 12 of 20 Figure 9 from top to bottom shows the simulation results of the inductor current, three-phase output load voltage, and three-phase output load current. The inductor currents of two inductors are equal to each other. The average value of inductor currents is 11.7 and 11.6 A for ILP and ILN, respectively. Due to applying the low-pass filter before the resistor load, the output load voltage, as well as the output load current, have a good quality. The THD value of these waveforms is 2.38% for both voltage and current waveforms. The RMS value of output load voltage and output load current are 111 VRMS and 2.78 ARMS.  Figure 10 shows the simulation results of dc-link voltage, inductor current, DqSB network's active switch voltage stress, diode voltage stress. The inductor LP stores energy in ST mode which appeared when the diode D2P is reserved bias, as illustrated in Figure 10. In this time interval, the current through LP linearly increases. The inductor current ripples are measured as 1.5 and 1.44 A for LP and LN, respectively. The inductor current is kept constant when SP is turned on and the diode D1P  Figure 10 shows the simulation results of dc-link voltage, inductor current, DqSB network's active switch voltage stress, diode voltage stress. The inductor L P stores energy in ST mode which appeared when the diode D 2P is reserved bias, as illustrated in Figure 10. In this time interval, the current through L P linearly increases. The inductor current ripples are measured as 1.5 and 1.44 A for L P and L N , respectively. The inductor current is kept constant when S P is turned on and the diode D 1P is reserved bias, as shown in Figure 10. As all switches of the inverter branch are triggered on, the DC-link voltage is zero in ST mode, whereas it achieves maximum value in NST mode, as presented in Figure 10.  Figure 11 shows the investigation about voltage gain versus THD value of VAG and voltage gain versus CMV. When the voltage gain increases, the modulation index decreases, which is demonstrated in Section 3. Thus, the THD value of output phase voltage increases with the increase of voltage gain. With all value of voltage gain, the 3L-DqSBT 2 I method always produces a smaller value of THD value of VAG than that of the SinPWM method in [35], as presented in Figure 11a. Moreover, the RMS value of CMV produced by the 3L-DqSBT 2 I method is superior to that of the SinPWM method in [35], as illustrated in Figure 11b.

Experimental Results
The performance of the proposed inverter was further validated through the experiment. A 1 kW prototype was carried out in a laboratory with the parameters listed in Table 3, which is the same  Figure 11 shows the investigation about voltage gain versus THD value of V AG and voltage gain versus CMV. When the voltage gain increases, the modulation index decreases, which is demonstrated in Section 3. Thus, the THD value of output phase voltage increases with the increase of voltage gain. With all value of voltage gain, the 3L-DqSBT 2 I method always produces a smaller value of THD value of V AG than that of the SinPWM method in [35], as presented in Figure 11a. Moreover, the RMS value of CMV produced by the 3L-DqSBT 2 I method is superior to that of the SinPWM method in [35], as illustrated in Figure 11b.  Figure 11 shows the investigation about voltage gain versus THD value of VAG and voltage gain versus CMV. When the voltage gain increases, the modulation index decreases, which is demonstrated in Section 3. Thus, the THD value of output phase voltage increases with the increase of voltage gain. With all value of voltage gain, the 3L-DqSBT 2 I method always produces a smaller value of THD value of VAG than that of the SinPWM method in [35], as presented in Figure 11a. Moreover, the RMS value of CMV produced by the 3L-DqSBT 2 I method is superior to that of the SinPWM method in [35], as illustrated in Figure 11b.

Experimental Results
The performance of the proposed inverter was further validated through the experiment. A 1 kW prototype was carried out in a laboratory with the parameters listed in Table 3, which is the same as the simulation. This prototype was controlled by a DSP F28335 microcontroller and FPGA Cyclone

Experimental Results
The performance of the proposed inverter was further validated through the experiment. A 1 kW prototype was carried out in a laboratory with the parameters listed in Table 3, which is the same as the simulation. This prototype was controlled by a DSP F28335 microcontroller and FPGA Cyclone II EP2C5T144C8. The gate-drive was based on TLP250, which fed to IGBT FGL40N150D, which are low-side and high-side switches of 3L-T 2 I branch, while IGBT FGL40N120D and MOSFET 6R045A were installed for bidirectional switches and DqSB network's switches, respectively. The three-phase resistive load was considered to verify the proposed methods, which was fed through three-phase LC filter with the cut-off frequency of approximately 1 kHz by applying 3 mH and 10 µF for inductor value and capacitor value, respectively. The photo of experiment prototype is illustrated in Figure 12.
The experimental results are shown in Figure 13. were installed for bidirectional switches and DqSB network's switches, respectively. The three-phase resistive load was considered to verify the proposed methods, which was fed through three-phase LC filter with the cut-off frequency of approximately 1 kHz by applying 3 mH and 10 μF for inductor value and capacitor value, respectively. The photo of experiment prototype is illustrated in Figure  12. The experimental results are shown in Figure 13.   Figure 13c. Therefore, the peak-value of dc-link voltage is 304 V which is the sum of capacitor voltage and dc input power supply, as presented in Figure 13c. The variation of top part of output line-line voltage is from zero to dc-link voltage. The output phase voltage has seven-level voltage which varies from −2/3V PN to +2/3V PN . The form of output load voltage and output load current are sinewave which are achieved by applying LC filter before feeding to the load, as illustrated in Figure 13b. Their RMS values are 104 V RMS and 2.5 A RMS , respectively. The simulated values are nearly the calculated values, whereas the calculated values are higher than the measured values. This is because the SVP method is used to obtain a high voltage gain, and the voltage drops across the devices, caused by high currents, are dominant. The CMV generated by proposed topology when applying introduced method varies from −V PN /6 to +V PN /6, as shown in Figure 13a. The RMS value of CMV is 32.6 V RMS . Figure 13c shows that the inductor current is linearly increased when the dc-link voltage achieves zero value while the diode D 2P is reserved bias which represents ST state. While, the constant value of inductor current is obtained when NST mode 1 is achieved, which is represented by reserving bias the diode D 1P .
Figure 13e,f shows the harmonic spectrum of V AG and I A . It can be seen that the peak-value of the harmonic spectrum of output phase voltage is 104 V RMS at the first-order harmonic of 50 Hz. By using a low-pass LC filter, the magnitude of high-frequency harmonics of V AG is reduced and approximately equal to zero. The magnitude of the first harmonic of the load current, I A is around 2.5 A RMS as illustrated in Figure 13f. Based on the harmonic spectrum analysis, the THD values of output voltage and current can be calculated as 62.4% and 2.77%, respectively.

Conclusions
This paper proposed the 3L DqSBT 2 I configuration which combines all advantages of the 3LT 2 I and the DqSB network. This configuration is controlled by the SVP technique with some benefits such as enhancing modulation index and reducing the magnitude as well as the slew-rate of CMV. In this scheme, the zero vector, medium vectors, and large vectors were utilized to generate the output voltage. The control signal of intermediate network power switches was also detailed to provide the high boost factor and voltage gain. As a result, the voltage stress on power devices like capacitors, diodes, and switches were decreased significantly. To validate the performance of the proposed method, the PSIM simulation and the laboratory prototype experiment were conducted. Furthermore, the comparisons between the proposed method and other conventional schemes were carried out to confirm the effectiveness of the proposed technique. Due to all benefits mentioned above, this configuration is suitable for low and medium voltage applications like photovoltaic systems or motor drives.