AC “Back to Back” Switching Device in Industrial Application †

: In industrial applications, among several varieties of semiconductor devices available, a silicon-controlled rectiﬁer (SCR) is often used in managing and protecting various systems with di ﬀ erent applications. Hence, it is of the utmost importance to design a control system which can operate over a range of electrical loads without any modiﬁcations in its hardware and / or software. This paper analyzes and investigates in detail the power circuit e ﬀ ects on conduction delay and SCR functioning. Moreover, two di ﬀ erent commonly used driving systems for SCR application have been introduced, discussed


Introduction
In industrial applications, the silicon-controlled rectifier (SCR) (power electronics-based switch and breaker) is a widely-used semi-controlled device due to its controllability and flexibility over diodes (uncontrolled switches) and its reliability and affordable prices with respect to fully-controlled power electronic switches [1][2][3][4]. Moreover, in diverse industrial fields, among several varieties of semiconductor devices available, SCRs are a preferred choice in managing and protecting various systems with different applications, especially in the field of industrial control systems [5][6][7] where it is mandatory to consider the peak value of current and its duration. As examples, in magnetic applications (where the magnets are sensitive to the peak current) and electric protection devices, it is of importance to take into account the peak current value, its shape and its time duration, else it might result in the damage of the system [8] and/or the protected load. SCR due to its characteristics (controllability, reliability, and affordable price) is the first choice in several other industrial applications as well [4]. Controllability refers to the ability to move the system

An Overview on SCR and Its Application
SCR is a semiconductor device widely used as a power switch. Its usage over the years increased due to its characteristics of fast switching current, during switch on and sometimes during switch off, in comparison to the more traditional and historically used electromechanical breaker.
The switching on of the device can be controlled with a gate signal by means of well-defined biasing conditions. Through this, the electrical parameters of the load voltage, current, and average absorbed power by load can be controlled.
The SCR device is typically manufactured by four layers of P and N type semiconductor materials placed one after another in alternating fashion. The operation of the SCR can be explained by a pair of tightly coupled bipolar junction transistors, arranged in such a way to cause a selflatching action as depicted in Figure 1. Here, two transistors are shown, namely PNP and an NPN devices. When the VGATE is positive with respect to the cathode, the SCR operates in its forward characteristics. Figure 2 graphically reports SCR's forward characteristics. In Figure 2, three I-V curves are plotted in order to show gate current (designated as IG) effects on SCR's forward voltage (reported on abscissa axis) and the forward current (reported on the ordinate axis). In particular it represents three curves covering IG = 0, relatively low gate current (IG1) and slightly higher gate current (IG2). It can be noticed that I-V cures follow a similar shape unless the breakover point occurs sooner with higher IG. In Figure 3, the qualitative variation of Forward Breakdown Voltage (VB0) vs. Gate Current (IG) is shown. It puts in evidence that the correct way to turn on a SCR, is to apply a fast current pulse with suitable amplitude to the gate terminal when a positive voltage is provided between anode and cathode in order to reduce the breakover voltage of the device. When the V GATE is positive with respect to the cathode, the SCR operates in its forward characteristics. Figure 2 graphically reports SCR's forward characteristics. In Figure 2, three I-V curves are plotted in order to show gate current (designated as I G ) effects on SCR's forward voltage (reported on abscissa axis) and the forward current (reported on the ordinate axis). In particular it represents three curves covering I G = 0, relatively low gate current (I G1 ) and slightly higher gate current (I G2 ). It can be noticed that I-V cures follow a similar shape unless the breakover point occurs sooner with higher I G .

An Overview on SCR and Its Application
SCR is a semiconductor device widely used as a power switch. Its usage over the years increased due to its characteristics of fast switching current, during switch on and sometimes during switch off, in comparison to the more traditional and historically used electromechanical breaker.
The switching on of the device can be controlled with a gate signal by means of well-defined biasing conditions. Through this, the electrical parameters of the load voltage, current, and average absorbed power by load can be controlled.
The SCR device is typically manufactured by four layers of P and N type semiconductor materials placed one after another in alternating fashion. The operation of the SCR can be explained by a pair of tightly coupled bipolar junction transistors, arranged in such a way to cause a selflatching action as depicted in Figure 1. Here, two transistors are shown, namely PNP and an NPN devices. When the VGATE is positive with respect to the cathode, the SCR operates in its forward characteristics. Figure 2 graphically reports SCR's forward characteristics. In Figure 2, three I-V curves are plotted in order to show gate current (designated as IG) effects on SCR's forward voltage (reported on abscissa axis) and the forward current (reported on the ordinate axis). In particular it represents three curves covering IG = 0, relatively low gate current (IG1) and slightly higher gate current (IG2). It can be noticed that I-V cures follow a similar shape unless the breakover point occurs sooner with higher IG. In Figure 3, the qualitative variation of Forward Breakdown Voltage (VB0) vs. Gate Current (IG) is shown. It puts in evidence that the correct way to turn on a SCR, is to apply a fast current pulse with suitable amplitude to the gate terminal when a positive voltage is provided between anode and cathode in order to reduce the breakover voltage of the device. In Figure 3, the qualitative variation of Forward Breakdown Voltage (V B0 ) vs. Gate Current (I G ) is shown. It puts in evidence that the correct way to turn on a SCR, is to apply a fast current pulse with suitable amplitude to the gate terminal when a positive voltage is provided between anode and cathode in order to reduce the breakover voltage of the device. Therefore, the gate current is usually made high enough to ensure that the SCR is switched to the ON state at the proper time and it is usually necessary for just an instant because a constant gate current is not required to trigger the SCR and it would only cause more power losses that needs to be dissipated within the device. Therefore, once the device has been switched-on by the gate terminal, it remains latched in the ON state and it does not need a continuous supply of gate current in order to maintain the conduction. This is true only if the anode current has exceeded the latching current (denoted by IL in Figure 2).
As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (denote as IH) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (tQ).
To have right SCR gate triggering, following conditions need to be provided: an appropriate gate to cathode voltage (VGATE) is needed to turn on the device while the SCR is forward biased; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; while the device is in reverse biased conditions, no VGATE signal should be applied; when the device is in-off state, negative VGATE should be applied to improve the performance of the under-test device.
Taking into account the above considerations and noticing that the pulses must occur periodically (considering the network frequency), it is evident that the gate is triggered by means of a pulsed waveform applied across the gate terminals and will be able to work correctly for all the power switch applications and with any load conditions. Therefore, it is very important to know the availability of SCR topologies in the market. Based on the manufacturing technology used, three different topologies of SCR can be realized-they are listed below and are described in more detail in the literature, e.g., in [25]:  Planar type: Typically used for low current devices because the junctions are obtained by diffusion and come to the same surface on the cathode side. The ratio silicon/ampere is typically high;  Mesa type: It is used for high current devices but low di/dt ratio. Power SCRs are typically manufactured by this process; : the correct way to turn on a SCR device is to apply a fast current pulse with suitable amplitude on the gate terminal when a positive voltage is applied between anode and cathode to reduce the Breakover Voltage of the device.
Therefore, the gate current is usually made high enough to ensure that the SCR is switched to the ON state at the proper time and it is usually necessary for just an instant because a constant gate current is not required to trigger the SCR and it would only cause more power losses that needs to be dissipated within the device. Therefore, once the device has been switched-on by the gate terminal, it remains latched in the ON state and it does not need a continuous supply of gate current in order to maintain the conduction. This is true only if the anode current has exceeded the latching current (denoted by I L in Figure 2).
As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (denote as I H ) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (t Q ).
To have right SCR gate triggering, following conditions need to be provided: Therefore, the gate current is usually made high enough to ensure that the SCR is switched to the ON state at the proper time and it is usually necessary for just an instant because a constant gate current is not required to trigger the SCR and it would only cause more power losses that needs to be dissipated within the device. Therefore, once the device has been switched-on by the gate terminal, it remains latched in the ON state and it does not need a continuous supply of gate current in order to maintain the conduction. This is true only if the anode current has exceeded the latching current (denoted by IL in Figure 2).
As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (denote as IH) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (tQ).
To have right SCR gate triggering, following conditions need to be provided: an appropriate gate to cathode voltage (VGATE) is needed to turn on the device while the SCR is forward biased; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; while the device is in reverse biased conditions, no VGATE signal should be applied; when the device is in-off state, negative VGATE should be applied to improve the performance of the under-test device.
Taking into account the above considerations and noticing that the pulses must occur periodically (considering the network frequency), it is evident that the gate is triggered by means of a pulsed waveform applied across the gate terminals and will be able to work correctly for all the power switch applications and with any load conditions. Therefore, it is very important to know the availability of SCR topologies in the market. Based on the manufacturing technology used, three different topologies of SCR can be realized-they are listed below and are described in more detail in the literature, e.g., in [25]: Therefore, the gate current is usually made high enough to ensure that the SCR is switched to the ON state at the proper time and it is usually necessary for just an instant because a constant gate current is not required to trigger the SCR and it would only cause more power losses that needs to be dissipated within the device. Therefore, once the device has been switched-on by the gate terminal, it remains latched in the ON state and it does not need a continuous supply of gate current in order to maintain the conduction. This is true only if the anode current has exceeded the latching current (denoted by IL in Figure 2).
As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (denote as IH) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (tQ).
To have right SCR gate triggering, following conditions need to be provided: an appropriate gate to cathode voltage (VGATE) is needed to turn on the device while the SCR is forward biased; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; while the device is in reverse biased conditions, no VGATE signal should be applied; when the device is in-off state, negative VGATE should be applied to improve the performance of the under-test device.
Taking into account the above considerations and noticing that the pulses must occur periodically (considering the network frequency), it is evident that the gate is triggered by means of a pulsed waveform applied across the gate terminals and will be able to work correctly for all the power switch applications and with any load conditions. Therefore, it is very important to know the availability of SCR topologies in the market. Based on the manufacturing technology used, three different topologies of SCR can be realized-they are listed below and are described in more detail in the literature, e.g., in [25]:  Planar type: Typically used for low current devices because the junctions are obtained by diffusion and come to the same surface on the cathode side. The ratio silicon/ampere is typically high;  Mesa type: It is used for high current devices but low di/dt ratio. Power SCRs are typically manufactured by this process; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; Energies 2020, 13, x FOR PEER REVIEW 4 of 20 Therefore, the gate current is usually made high enough to ensure that the SCR is switched to the ON state at the proper time and it is usually necessary for just an instant because a constant gate current is not required to trigger the SCR and it would only cause more power losses that needs to be dissipated within the device. Therefore, once the device has been switched-on by the gate terminal, it remains latched in the ON state and it does not need a continuous supply of gate current in order to maintain the conduction. This is true only if the anode current has exceeded the latching current (denoted by IL in Figure 2).
As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (denote as IH) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (tQ).
To have right SCR gate triggering, following conditions need to be provided: an appropriate gate to cathode voltage (VGATE) is needed to turn on the device while the SCR is forward biased; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; while the device is in reverse biased conditions, no VGATE signal should be applied; when the device is in-off state, negative VGATE should be applied to improve the performance of the under-test device.
Taking into account the above considerations and noticing that the pulses must occur periodically (considering the network frequency), it is evident that the gate is triggered by means of a pulsed waveform applied across the gate terminals and will be able to work correctly for all the power switch applications and with any load conditions. Therefore, it is very important to know the availability of SCR topologies in the market. Based on the manufacturing technology used, three different topologies of SCR can be realized-they are listed below and are described in more detail in the literature, e.g., in [25]:  Planar type: Typically used for low current devices because the junctions are obtained by diffusion and come to the same surface on the cathode side. The ratio silicon/ampere is typically high; while the device is in reverse biased conditions, no V GATE signal should be applied; Therefore, the gate current is usually made high enough to ensure that the SCR is switched to the ON state at the proper time and it is usually necessary for just an instant because a constant gate current is not required to trigger the SCR and it would only cause more power losses that needs to be dissipated within the device. Therefore, once the device has been switched-on by the gate terminal, it remains latched in the ON state and it does not need a continuous supply of gate current in order to maintain the conduction. This is true only if the anode current has exceeded the latching current (denoted by IL in Figure 2).
As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (denote as IH) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (tQ).
To have right SCR gate triggering, following conditions need to be provided: an appropriate gate to cathode voltage (VGATE) is needed to turn on the device while the SCR is forward biased; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; while the device is in reverse biased conditions, no VGATE signal should be applied; when the device is in-off state, negative VGATE should be applied to improve the performance of the under-test device.
Taking into account the above considerations and noticing that the pulses must occur periodically (considering the network frequency), it is evident that the gate is triggered by means of a pulsed waveform applied across the gate terminals and will be able to work correctly for all the power switch applications and with any load conditions. Therefore, it is very important to know the availability of SCR topologies in the market. Based on the manufacturing technology used, three different topologies of SCR can be realized-they are listed below and are described in more detail in the literature, e.g., in [25]:  Planar type: Typically used for low current devices because the junctions are obtained by diffusion and come to the same surface on the cathode side. The ratio silicon/ampere is typically when the device is in-off state, negative V GATE should be applied to improve the performance of the under-test device.
Taking into account the above considerations and noticing that the pulses must occur periodically (considering the network frequency), it is evident that the gate is triggered by means of a pulsed waveform applied across the gate terminals and will be able to work correctly for all the power switch applications and with any load conditions. Therefore, it is very important to know the availability of SCR topologies in the market. Based on the manufacturing technology used, three different topologies of SCR can be realized-they are listed below and are described in more detail in the literature, e.g., in [25]:  Therefore, the gate current is usually made high enough to ensure that the SCR is switched to the ON state at the proper time and it is usually necessary for just an instant because a constant gate current is not required to trigger the SCR and it would only cause more power losses that needs to be dissipated within the device. Therefore, once the device has been switched-on by the gate terminal, it remains latched in the ON state and it does not need a continuous supply of gate current in order to maintain the conduction. This is true only if the anode current has exceeded the latching current (denoted by IL in Figure 2).
As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (denote as IH) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (tQ).
To have right SCR gate triggering, following conditions need to be provided: an appropriate gate to cathode voltage (VGATE) is needed to turn on the device while the SCR is forward biased; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; while the device is in reverse biased conditions, no VGATE signal should be applied; when the device is in-off state, negative VGATE should be applied to improve the performance of the under-test device.
Planar type: Typically used for low current devices because the junctions are obtained by diffusion and come to the same surface on the cathode side. The ratio silicon/ampere is typically high; falls below the holding current (denote as IH) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (tQ).
To have right SCR gate triggering, following conditions need to be provided: an appropriate gate to cathode voltage (VGATE) is needed to turn on the device while the SCR is forward biased; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; while the device is in reverse biased conditions, no VGATE signal should be applied; when the device is in-off state, negative VGATE should be applied to improve the performance of the under-test device.
Taking into account the above considerations and noticing that the pulses must occur periodically (considering the network frequency), it is evident that the gate is triggered by means of a pulsed waveform applied across the gate terminals and will be able to work correctly for all the power switch applications and with any load conditions. Therefore, it is very important to know the availability of SCR topologies in the market. Based on the manufacturing technology used, three different topologies of SCR can be realized-they are listed below and are described in more detail in the literature, e.g., in [25]:  Planar type: Typically used for low current devices because the junctions are obtained by diffusion and come to the same surface on the cathode side. The ratio silicon/ampere is typically high;  Mesa type: It is used for high current devices but low di/dt ratio. Power SCRs are typically manufactured by this process;  Press pack type: Widely used in applications where it is necessary to have SCR with center gate and large value of di/dt. Mesa type: It is used for high current devices but low di/dt ratio. Power SCRs are typically manufactured by this process; (denoted by IL in Figure 2). As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (denote as IH) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (tQ).
To have right SCR gate triggering, following conditions need to be provided: an appropriate gate to cathode voltage (VGATE) is needed to turn on the device while the SCR is forward biased; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; while the device is in reverse biased conditions, no VGATE signal should be applied; when the device is in-off state, negative VGATE should be applied to improve the performance of the under-test device.
Taking into account the above considerations and noticing that the pulses must occur periodically (considering the network frequency), it is evident that the gate is triggered by means of a pulsed waveform applied across the gate terminals and will be able to work correctly for all the power switch applications and with any load conditions. Therefore, it is very important to know the availability of SCR topologies in the market. Based on the manufacturing technology used, three different topologies of SCR can be realized-they are listed below and are described in more detail in the literature, e.g., in [25]:  Planar type: Typically used for low current devices because the junctions are obtained by diffusion and come to the same surface on the cathode side. The ratio silicon/ampere is typically high;  Mesa type: It is used for high current devices but low di/dt ratio. Power SCRs are typically manufactured by this process;  Press pack type: Widely used in applications where it is necessary to have SCR with center gate and large value of di/dt.
Press pack type: Widely used in applications where it is necessary to have SCR with center gate and large value of di/dt.
Usually, power SCRs use a Mesa process for manufacturing. It is important to note that the device is prevalently used in "back to back" mode in AC circuit configurations, see Figure 4 where the device is turned off automatically, hence load current is cutoff every zero crossing of the signal. For the DC applications, an ad hoc circuit is necessary for the use of SCR, this is important to force the device into turn off state. However, the SCR application in DC systems is not further developed in this paper as it focuses only on AC applications. Usually, power SCRs use a Mesa process for manufacturing. It is important to note that the device is prevalently used in "back to back" mode in AC circuit configurations, see Figure 4 where the device is turned off automatically, hence load current is cutoff every zero crossing of the signal. For the DC applications, an ad hoc circuit is necessary for the use of SCR, this is important to force the device into turn off state. However, the SCR application in DC systems is not further developed in this paper as it focuses only on AC applications. As it can be seen from Table 1, different commercial devices available have different latching currents IL (in Table 1 the holding currents IH are also reported), therefore, it is very important to evaluate the minimum pulse time duration to be given to an SCR for its ignition. This duration is fundamental to using SCRs as switching devices in different industrial applications, because having knowledge only on latching currents (IL) is not sufficient to assure proper operation of SCR in all conditions.

Device
Manufacturer Semikron Indeed, the minimum value of IL depends on the adopted delay angle control α, load impedance and on the RMS value of the applied voltage. Considering these points, in most of industrial solutions, the driving pulses length are oversized in time. Hence, the triggering pulse width is much longer than the actual width needed to guarantee the device turning on with a driving signal and to achieve the desired control function. The aim of the paper is to investigate and propose an optimum solution, which can improve overall system efficiency and functionality and can be adopted in wide range of applications.
Here, it is also worth understanding a very important aspect in certain industrial applications. The conduction angle (sometimes also denoted as ignition angle) is very important as it depends on the value of the consequent current's peak value. In some applications, for example in the case of permanent magnet systems, the state of magnetization of the system depends precisely on the peak value of the magnetizing current. To increase this peak value, with the same system, it is possible to act on the ignition angle, making it small. Therefore, the possibility of having a system that as a whole (hardware and software) is able to turn on the SCR at low conduction angles is certainly an As it can be seen from Table 1, different commercial devices available have different latching currents I L (in Table 1 the holding currents I H are also reported), therefore, it is very important to evaluate the minimum pulse time duration to be given to an SCR for its ignition. This duration is fundamental to using SCRs as switching devices in different industrial applications, because having knowledge only on latching currents (I L ) is not sufficient to assure proper operation of SCR in all conditions. Table 1. Examples of SCR characteristics.

Device
Manufacturer Semikron Indeed, the minimum value of I L depends on the adopted delay angle control α, load impedance and on the RMS value of the applied voltage. Considering these points, in most of industrial solutions, the driving pulses length are oversized in time. Hence, the triggering pulse width is much longer than the actual width needed to guarantee the device turning on with a driving signal and to achieve the desired control function. The aim of the paper is to investigate and propose an optimum solution, which can improve overall system efficiency and functionality and can be adopted in wide range of applications.
Here, it is also worth understanding a very important aspect in certain industrial applications. The conduction angle (sometimes also denoted as ignition angle) is very important as it depends on the value of the consequent current's peak value. In some applications, for example in the case of permanent magnet systems, the state of magnetization of the system depends precisely on the peak Energies 2020, 13, 3539 6 of 20 value of the magnetizing current. To increase this peak value, with the same system, it is possible to act on the ignition angle, making it small. Therefore, the possibility of having a system that as a whole (hardware and software) is able to turn on the SCR at low conduction angles is certainly an advantage. The advantages are multiple: in terms of ampere-turns, it is therefore possible to either obtain more from the same system or to decrease ampere-turns, obtaining an undeniable advantage in economic terms by saving on material and dimensions. All of these are obviously of completely general validity even if, in the aforementioned application, it appears to be of fundamental importance to influence the competitiveness or otherwise of the adopted solution.
The obtained results could be also influenced by the type of application, the type of driver circuit, the adopted control method and, obviously, by the characteristics of the SCR used (and with this the presence and also the importance of the above discussion).
Finally, the importance of the considerations and evaluations (numerical and experimental) that are discussed in the following sections (Sections 3 and 4) are very evident.

General Discusion
The equivalent circuit, in Figure 5, shows the typical representation of the SCR application, where two SCRs in back to back configuration are connected to an ohmic-inductive (R-L) load.
Energies 2020, 13, x FOR PEER REVIEW 6 of 20 in economic terms by saving on material and dimensions. All of these are obviously of completely general validity even if, in the aforementioned application, it appears to be of fundamental importance to influence the competitiveness or otherwise of the adopted solution.
The obtained results could be also influenced by the type of application, the type of driver circuit, the adopted control method and, obviously, by the characteristics of the SCR used (and with this the presence and also the importance of the above discussion).
Finally, the importance of the considerations and evaluations (numerical and experimental) that are discussed in the following sections (Sections 3 and 4) are very evident.

General Discusion
The equivalent circuit, in Figure 5, shows the typical representation of the SCR application, where two SCRs in back to back configuration are connected to an ohmic-inductive (R-L) load. The lagging load angle, φ, is the phase displacement between load voltage and current, and its expression is given by: where X is the reactance and R is the resistance of the load. The second Kirchhoff law permits to write the expression illustrate below: where L is the inductive part of the load. Note that, in many applications, the last term of Equation (2) can be discarded because it represents the dependency of the inductance to the time variation, which it is either very low in magnitude or very slow (different time domain) comparing to electrical current's dynamic. Ignoring the last term and solving the previous equation, the current expression can be obtained: where:  i(t) is the sum of a regimen term (first term) and a transient one (second term), which depends on time constant τ equal to L/R;  V is the rms voltage value applied by the voltage source, v(t);  Z is the load impedance;  α is the control phase angle evaluated starting from the voltage zero crossing and it can be managed by the gate driver circuit often triggered through a supervisory microcontroller. The lagging load angle, ϕ, is the phase displacement between load voltage and current, and its expression is given by: where X is the reactance and R is the resistance of the load. The second Kirchhoff law permits to write the expression illustrate below: where L is the inductive part of the load. Note that, in many applications, the last term of Equation (2) can be discarded because it represents the dependency of the inductance to the time variation, which it is either very low in magnitude or very slow (different time domain) comparing to electrical current's dynamic. Ignoring the last term and solving the previous equation, the current expression can be obtained: where: Energies 2020, 13, x FOR PEER REVIEW 4 of 20 Therefore, the gate current is usually made high enough to ensure that the SCR is switched to the ON state at the proper time and it is usually necessary for just an instant because a constant gate current is not required to trigger the SCR and it would only cause more power losses that needs to be dissipated within the device. Therefore, once the device has been switched-on by the gate terminal, it remains latched in the ON state and it does not need a continuous supply of gate current in order to maintain the conduction. This is true only if the anode current has exceeded the latching current (denoted by IL in Figure 2).
As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (denote as IH) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (tQ).
To have right SCR gate triggering, following conditions need to be provided: an appropriate gate to cathode voltage (VGATE) is needed to turn on the device while the SCR is forward biased; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; while the device is in reverse biased conditions, no VGATE signal should be applied; when the device is in-off state, negative VGATE should be applied to improve the performance of the under-test device.
i(t) is the sum of a regimen term (first term) and a transient one (second term), which depends on time constant τ equal to L/R; falls below the holding current (denote as IH) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (tQ).
To have right SCR gate triggering, following conditions need to be provided: an appropriate gate to cathode voltage (VGATE) is needed to turn on the device while the SCR is forward biased; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; while the device is in reverse biased conditions, no VGATE signal should be applied; when the device is in-off state, negative VGATE should be applied to improve the performance of the under-test device.
Taking into account the above considerations and noticing that the pulses must occur periodically (considering the network frequency), it is evident that the gate is triggered by means of a pulsed waveform applied across the gate terminals and will be able to work correctly for all the power switch applications and with any load conditions. Therefore, it is very important to know the availability of SCR topologies in the market. Based on the manufacturing technology used, three different topologies of SCR can be realized-they are listed below and are described in more detail in the literature, e.g., in [25]:  Planar type: Typically used for low current devices because the junctions are obtained by diffusion and come to the same surface on the cathode side. The ratio silicon/ampere is typically high;  Mesa type: It is used for high current devices but low di/dt ratio. Power SCRs are typically manufactured by this process;  Press pack type: Widely used in applications where it is necessary to have SCR with center gate and large value of di/dt. V is the rms voltage value applied by the voltage source, v(t); As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (denote as IH) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (tQ).
To have right SCR gate triggering, following conditions need to be provided: an appropriate gate to cathode voltage (VGATE) is needed to turn on the device while the SCR is forward biased; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; while the device is in reverse biased conditions, no VGATE signal should be applied; when the device is in-off state, negative VGATE should be applied to improve the performance of the under-test device.
Taking into account the above considerations and noticing that the pulses must occur periodically (considering the network frequency), it is evident that the gate is triggered by means of a pulsed waveform applied across the gate terminals and will be able to work correctly for all the power switch applications and with any load conditions. Therefore, it is very important to know the availability of SCR topologies in the market. Based on the manufacturing technology used, three different topologies of SCR can be realized-they are listed below and are described in more detail in the literature, e.g., in [25]:  Planar type: Typically used for low current devices because the junctions are obtained by diffusion and come to the same surface on the cathode side. The ratio silicon/ampere is typically high;  Mesa type: It is used for high current devices but low di/dt ratio. Power SCRs are typically manufactured by this process;  Press pack type: Widely used in applications where it is necessary to have SCR with center gate and large value of di/dt. Z is the load impedance; (denoted by IL in Figure 2). As long as the anode remains positively biased, it cannot be switched off until the anode current falls below the holding current (denote as IH) and so the voltage across the SCR become zero or negative.
After the current has reached natural zero point, a finite amount of time delay is required before initiating another switch on procedure and during this period SCR must retain in off state. This minimum time delay is called turn off time (tQ).
To have right SCR gate triggering, following conditions need to be provided: an appropriate gate to cathode voltage (VGATE) is needed to turn on the device while the SCR is forward biased; gate signal shall be removed after the device under test is turned on in order to reduce the losses and avoid higher junction temperature; while the device is in reverse biased conditions, no VGATE signal should be applied; when the device is in-off state, negative VGATE should be applied to improve the performance of the under-test device.
Taking into account the above considerations and noticing that the pulses must occur periodically (considering the network frequency), it is evident that the gate is triggered by means of a pulsed waveform applied across the gate terminals and will be able to work correctly for all the power switch applications and with any load conditions. Therefore, it is very important to know the availability of SCR topologies in the market. Based on the manufacturing technology used, three different topologies of SCR can be realized-they are listed below and are described in more detail in the literature, e.g., in [25]:  Planar type: Typically used for low current devices because the junctions are obtained by diffusion and come to the same surface on the cathode side. The ratio silicon/ampere is typically high;  Mesa type: It is used for high current devices but low di/dt ratio. Power SCRs are typically manufactured by this process;  Press pack type: Widely used in applications where it is necessary to have SCR with center gate and large value of di/dt. α is the control phase angle evaluated starting from the voltage zero crossing and it can be managed by the gate driver circuit often triggered through a supervisory microcontroller. Figure 6 decomposes the current expression in (3). Here, it is possible to observe both the initial transient component and the regime (steady-state) components of the current. During the first instants, the two components have close values, but considering the negative polarity of the transient component in (3), the results of the Equation (3) are about null at starting point, which can be in the range of the driver pulse duration. In this situation, the SCR ignition can be very difficult, and it is possible not to reach required I L and fail to gain the control of SCR.  (3), the results of the Equation (3) are about null at starting point, which can be in the range of the driver pulse duration. In this situation, the SCR ignition can be very difficult, and it is possible not to reach required IL and fail to gain the control of SCR.
It can be seen that when the conduction starts, the element − − ⁄ can be simplified by the first two elements of the MacLaurin series, while the term ( • − ) can be simplified, by the first element of the MacLaurin series, only when the value of it is close to zero.
Considering only the first elements of the MacLaurin series and using a time shift of α (t' = t-⁄ ), the following simple expression of the current reported in (5) is obtained.
Expression (5) provides the possibility to evaluate the time t', which is the time required to reach a specified current i(t'). Simply replacing i(t) equal to latching current IL it is possible to obtain the time required by the system to reach IL current and it will result in Expression (6): It is to be noted that expression (6) is applicable only when the conduction starts close to the point where the elements ( • − ) is close to zero. In the case where this element value is far from zero, it is necessary to adopt a different approach to compute the desired time value. In this study, in order to obtain this time value, Expression (3) is simulated in a dedicated simulation software and corresponding time required to reach the latching current (IL) is extracted.
In order to represent the proposed approach, the values of delay angle α is varied between 0 and 10 ms considering a load with R = 10 Ω, L = 55 mH (typical values for the considered application), V = 230 V, f = 50 Hz (standard industrial values for Europe), and IL = 0.4 A (typical value for high current Considering this problem, it should be possible to evaluate the necessary time (t α+ ) for the current to reach the latching current I L by inversing (3). Given the complexity and nonlinearity of the Equation (3), it is necessary to simplify it to obtain the desired result. In particular simplified expressions of the elements e − t− α ω τ and sen(ω·t − ϕ) as reported in the following expressions (obtained from the MacLaurin series expansion).
It can be seen that when the conduction starts, the element e − t− α ω τ can be simplified by the first two elements of the MacLaurin series, while the term sen(ω·t − ϕ) can be simplified, by the first element of the MacLaurin series, only when the value of it is close to zero.
Considering only the first elements of the MacLaurin series and using a time shift of α (t = t-α ω ), the following simple expression of the current reported in (5) is obtained.
Expression (5) provides the possibility to evaluate the time t , which is the time required to reach a specified current i(t ). Simply replacing i(t) equal to latching current I L it is possible to obtain the time required by the system to reach I L current and it will result in Expression (6): It is to be noted that expression (6) is applicable only when the conduction starts close to the point where the elements sen(ω·t − ϕ) is close to zero. In the case where this element value is far from zero, it is necessary to adopt a different approach to compute the desired time value. In this study, in order to obtain this time value, Expression (3) is simulated in a dedicated simulation software and corresponding time required to reach the latching current (I L ) is extracted.
In order to represent the proposed approach, the values of delay angle α is varied between 0 and 10 ms considering a load with R = 10 Ω, L = 55 mH (typical values for the considered application), V = 230 V, f = 50 Hz (standard industrial values for Europe), and I L = 0.4 A (typical value for high current SCR devices, as described in Table 2), in order to evaluate the minimum theoretical gate pulse duration as reported in Table 2. It can be noticed that, for an example pulse duration of 200 µs, in some cases denoted with "/" the strategy works and the pulse duration is enough to ignite the SCR however in some other cases denoted by "X" the pulse duration of 200 µs is not enough to ignite the SCR. If similar analysis is applied to different load configurations, it is easy to identify critical situations as reported in Figure 7 where, the load value highly influence the minimum value of the necessary gate pulse and in particular when it has correspondence with the zero of the voltage. It is also clear that high voltage values allow the current to quickly gain to the latching current of the SCR. For the same situation, a lower value of the voltage leads to opposite effects.
Energies 2020, 13, x FOR PEER REVIEW 8 of 20 SCR devices, as described in Table 2), in order to evaluate the minimum theoretical gate pulse duration as reported in Table 2. It can be noticed that, for an example pulse duration of 200 μs, in some cases denoted with "/" the strategy works and the pulse duration is enough to ignite the SCR however in some other cases denoted by "X" the pulse duration of 200 μs is not enough to ignite the SCR. If similar analysis is applied to different load configurations, it is easy to identify critical situations as reported in Figure 7 where, the load value highly influence the minimum value of the necessary gate pulse and in particular when it has correspondence with the zero of the voltage. It is also clear that high voltage values allow the current to quickly gain to the latching current of the SCR. For the same situation, a lower value of the voltage leads to opposite effects.

Detail and Practical Discussions
In order to optimally design an SCR control system, it is necessary to size the control system to operate on different applications without a change in its hardware topology and/or software paradigm. To achieve this, it is fundamental to know the application and corresponding load

Detail and Practical Discussions
In order to optimally design an SCR control system, it is necessary to size the control system to operate on different applications without a change in its hardware topology and/or software paradigm. To achieve this, it is fundamental to know the application and corresponding load characteristics.
In some cases, especially when the load current needs to be unidirectional, as happens in electromagnetic applications, the control phase angle α can be higher or lower compared to the load angle ϕ, as in the example of Figure 6. Meanwhile, in other cases, such as for AC protection systems, the control phase angle α can only take values higher than that of the load angle ϕ.
Moreover, in some applications, there is a strong variation of the inductance during the activation/deactivation cycles. This situation is common in applications where the load changes its magnetic state. An example of aforementioned situation occurs in electrical motor during the startup, where the current rise to a very high value and reaches the steady state in the end. Many such cases of the described situation can be also found in equipment with permanent magnets. Many different applications which uses permanent magnets are found in the literature, in particular concerning the permanent magnet motors and related applications [26][27][28][29][30][31][32][33].
An interesting load, where it is possible to find both the previously mentioned problems is the electro permanent magnet (EPM). An EPM is a device realized by permanent magnets that can be switched -on or -off by a small amount of unidirectional current applying to its internal winding coil. The main applications of the EPMs are in handling of heavy ferromagnetic loads, such as iron bars and steel plates for manipulations over extended period of time, and for fixing the position of different mechanisms. In this application, the driving current is necessary only for few seconds during the activation (EPM is magnetized starting from an initial state of demagnetization) and deactivation cycles (initially magnetized EPM needs to be demagnetized). Thanks to this functionality, EPM can be considered as a system with zero electrical energy losses during working phases as described in [34].
As described, EPM needs unidirectional current, and during the activation/deactivation cycles the inductance value widely changes due to the variable nature of the magnets and the ferromagnetic circuit (function of the locked ferromagnetic load).
This phenomenon leads to a variation in current patterns, pulse after pulse, with particular regard to the transient current. In these cases, the theory and the results as described above, could be no longer adequate to define the phenomenon (due to L variation). In particular, in some cases, where it is possible to predict strong variations in the value of the inductance (L), the current may vanish, or in some cases, during the initial stage of conduction of the device, a very strange and/or unexpected shape of the current can be found. This may lead to a failure of the ignition strategy of the SCR control system. Even though a very strong variation of inductance is not so common and important in many other applications, in the loads described here, this aspect is a very important element. Normally there can be also a huge variation of the load resistance due to the very high temperature variation (around 125 • C) and it can vary the resistance up to 50% of its nominal value.
In order to understand the impact on minimum pulse time duration due to several factors involved in the problem definition, in the following the sensitivity analysis results based on the procedure described in (3)-(6) has been performed with a dedicated simulation software. The presented aspects in this section are mainly general and applicable to wide range applications (at least theoretically).
According to the analytical procedure (3)-(6), four factors have an impact on minimum pulse duration time. These are applied voltage RMS value V, load impedance Z, load power angle ϕ and control pulse angle α.
In particular, the nominal voltage V = 230 V, impedance Z and power angle ϕ equal to 10 Ω and 0.64 radiant (R = 8 Ω, L = 19 mH) respectively, are considered. The analysis is performed varying one element, around its rated value, while the other elements are fixed to the nominal ones. In this analysis the value of alpha is fixed and is equal to 12.5 µs. This value is considered as reference for all the tests because the value of alpha doesn't affect the direction of the variation trend but only the value of the minimum pulse duration time. The effect of impedance variation is evaluated considering impedance as one concrete parameter (varying amplitude and phase) and then its resistance (R) and inductance (L) are varied independently. In this way, the dependency of the minimum pulse time duration for SCR correct conduction is studied. The obtained results are reported in Figure 8 and they show that: a.
Supply voltage variation: applied voltage magnitude has linear effect on minimum pulse duration. For standard European voltage of 230 V RMS, this dependency is shown in Figure 8a with ±10% variation around nominal value in compliance with the international standard IEC 50160. It can be noticed that voltage variation has minor effect on minimum pulse time duration; b.
Impedance variation: Figure 8b shows the load impedance variation on the minimum pulse time duration with constant ϕ and V. The variation range is ±50%. An increase in Z means a lower current and a decrease in Z means a higher current. Therefore, it can be seen that, by increasing the load, the minimum pulse time duration required will increase, and with lower load current, wider pulses are required to guarantee the conduction; c.
Load power angle variation: with fixed Z and V, effect of load power angle variation has been studied. Figure 8c shows the effect of this variation on minimum pulse duration while the load changes from more resistive to more inductive absorbing the same RMS current. The variation range also in this case is ±50%. It can be seen that increasing the load power angle will cause increase in minimum pulse duration time. More inductive load needs pulses with longer width or in other word, with more resistive load the required pulse width for conduction become shorter; d.
Resistance variation: Figure 8d shows the effect of varying load resistance variation on minimum pulse time (t) required, with constants L and V. The variation range also in this case is ±50%. It can be noticed that increasing or decreasing the load resistance does not significantly influence the pulse duration. Therefore, it can be seen from Figure 8d that the variation in resistance doesn't have a major influence on the required pulse duration; e.
Inductance variation: Figure 8e shows the effect of varying load inductance on minimum required pulse time (t), with R and V as constant values. The variation range is once again ±50%.
Increasing the load inductance results in lower load current and vice versa. Hence, it can be noticed that by increasing the load inductance the minimum pulse duration needed will also increase. An aspect to note is that the variation in inductance is of very important with respect to the other parameters considered.
As it can be seen from the aforementioned analysis, the variation in resistance has no practical influence on the pulse duration, while variation in both the inductance and the applied voltage must be considered as dominant factors.
Starting from this point of view, in order to make the adopted control technique more efficient, pulse width to be considered in the gate signal should be at least equal to the sum of both variations of the inductance and voltage foreseen to the circuit under the test.
As has been observed, the problem in the choice of the ignition instant can be critical in order to obtain the desired operation and the maximization of the duration of the control pulse could introduce additional losses into the device.
When we consider the testbed consisting of the SCR circuit described in Figure 5, we arrive to the practical problem of conduction delay, which is always present. When the SCR is turned off the load is not powered by the source voltage v(t). Despite fast turn-on and turn-off characteristics, due to the inherent nature, this application introduces a short conduction delay at each voltage/current zero crossing which can be considered as distortion on load supply voltage. An example of this conduction delay is shown in Figure 9 for a resistive load.
The conduction delay can have different side effects, it affects the performance of the power circuit, interfere electromagnetically with broadband over power lines (BPL) communication devices and also deteriorates control performance of the power electronic based system [35]. Conduction delay principally depends on two main aspects concerning power circuit and SCR driver circuit. Due to the intrinsic nature, the SCR require a natural time to properly turn on, in addition to this, when the driver circuit introduces a time delay, it should be considered. If the power circuit aspect is kept unchanged, the time delay introduced by driver circuit can be analyzed in detail.
influence the pulse duration. Therefore, it can be seen from Figure 8d that the variation in resistance doesn't have a major influence on the required pulse duration; e. Inductance variation: Figure 8e shows the effect of varying load inductance on minimum required pulse time (t), with R and V as constant values. The variation range is once again ±50%. Increasing the load inductance results in lower load current and vice versa. Hence, it can be noticed that by increasing the load inductance the minimum pulse duration needed will also increase. An aspect to note is that the variation in inductance is of very important with respect to the other parameters considered. As it can be seen from the aforementioned analysis, the variation in resistance has no practical influence on the pulse duration, while variation in both the inductance and the applied voltage must be considered as dominant factors.
Starting from this point of view, in order to make the adopted control technique more efficient, pulse width to be considered in the gate signal should be at least equal to the sum of both variations of the inductance and voltage foreseen to the circuit under the test.
As has been observed, the problem in the choice of the ignition instant can be critical in order to obtain the desired operation and the maximization of the duration of the control pulse could introduce additional losses into the device.
When we consider the testbed consisting of the SCR circuit described in Figure 5, we arrive to the practical problem of conduction delay, which is always present. When the SCR is turned off the load is not powered by the source voltage v(t). Despite fast turn-on and turn-off characteristics, due to the inherent nature, this application introduces a short conduction delay at each voltage/current zero crossing which can be considered as distortion on load supply voltage. An example of this conduction delay is shown in Figure 9 for a resistive load. The conduction delay can have different side effects, it affects the performance of the power circuit, interfere electromagnetically with broadband over power lines (BPL) communication devices and also deteriorates control performance of the power electronic based system [35]. Conduction delay principally depends on two main aspects concerning power circuit and SCR driver circuit. Due to the intrinsic nature, the SCR require a natural time to properly turn on, in addition to this, when the driver circuit introduces a time delay, it should be considered. If the power circuit aspect is kept unchanged, the time delay introduced by driver circuit can be analyzed in detail.

SCR Driver Circuits, Simulation and Experimental Results
In order to run an SCR properly, a gate signal needs to be applied for sufficient time to allow the device to latch. In a practical application, this is achieved through a driver circuit to manage the gate signal. The driver circuit can be realized either by digital microcontroller or by an analog circuit.
Two main circuit topologies to control an SCR device have been considered in this study. Both of the considered driving circuits are applied for a constant system with an SCR switch unchanged

SCR Driver Circuits, Simulation and Experimental Results
In order to run an SCR properly, a gate signal needs to be applied for sufficient time to allow the device to latch. In a practical application, this is achieved through a driver circuit to manage the gate signal. The driver circuit can be realized either by digital microcontroller or by an analog circuit.
Two main circuit topologies to control an SCR device have been considered in this study. Both of the considered driving circuits are applied for a constant system with an SCR switch unchanged over the tests in order to compare their performance. Moreover, to compare the experimental results, both driving systems are supplied with the same voltage (equal to 15 V) and they have been controlled with the same microcontroller-based board.

Driver Circuit 1
In Figure 10, the first driver circuit is shown. In this configuration, an impulse transformer is required to control the SCR. The input (V1) has to be a high frequency pulse in order to permit the impulse transformer to work correctly with a variable signal.

Driver Circuit 1
In Figure 10, the first driver circuit is shown. In this configuration, an impulse transformer is required to control the SCR. The input (V1) has to be a high frequency pulse in order to permit the impulse transformer to work correctly with a variable signal. It is important also to note that the pulse width duration cannot be too short, because with short pulse width, the minimum value of the latching current IL cannot be guaranteed for wide range of given load (see Table 1) and cannot be too long either because the impulse transformer works properly only with variable signals.
In general, to satisfy every load condition, it is very common to control the circuit by a series of pulses (pulse train). In this case, it is mandatory to have a minimum delay time between two successive pulses in order to de-energize the impulse transformer properly. Considering the pulses shown in Figure 11, with a pulse command of 200 μs, it is possible to observe in Figure 11a that only the first pulse can energize the impulse transformer (it can manage the ignition of the SCR). While the second and third pulses cannot reach their peak value (those cannot manage the ignition of the SCR correctly) because the pulses are too close to each other (switching frequency about 3 kHz). Considering Figure 10b, all the pulses with the same pulse command of 200 μs can energize the impulse transformer and consequently can run the SCR (switching frequency about 1.5 kHz).
(a) (b) Figure 11. Impulses with a frequency of (a) around 3 kHz-problems on the second and third pulses (b) around 1.5 kHz-both pulses represented has similar behavior.
In this work, pulses of 200 μs width with a frequency of 1.5 kHz is used to supply Driver Circuit 1 and control the SCR module.
A digital microcontroller is required to generate the pulses for Driver Circuit 1, in certain cases analog circuits can be used, but in general this topology can generate only a series of pulses due to the difficulty in generating the pulses at the desired moment constrained by the limitation of the impulse transformer. It is important also to note that the pulse width duration cannot be too short, because with short pulse width, the minimum value of the latching current I L cannot be guaranteed for wide range of given load (see Table 1) and cannot be too long either because the impulse transformer works properly only with variable signals.
In general, to satisfy every load condition, it is very common to control the circuit by a series of pulses (pulse train). In this case, it is mandatory to have a minimum delay time between two successive pulses in order to de-energize the impulse transformer properly. Considering the pulses shown in Figure 11, with a pulse command of 200 µs, it is possible to observe in Figure 11a that only the first pulse can energize the impulse transformer (it can manage the ignition of the SCR). While the second and third pulses cannot reach their peak value (those cannot manage the ignition of the SCR correctly) because the pulses are too close to each other (switching frequency about 3 kHz). Considering Figure 10b, all the pulses with the same pulse command of 200 µs can energize the impulse transformer and consequently can run the SCR (switching frequency about 1.5 kHz).

Driver Circuit 1
In Figure 10, the first driver circuit is shown. In this configuration, an impulse transformer is required to control the SCR. The input (V1) has to be a high frequency pulse in order to permit the impulse transformer to work correctly with a variable signal. It is important also to note that the pulse width duration cannot be too short, because with short pulse width, the minimum value of the latching current IL cannot be guaranteed for wide range of given load (see Table 1) and cannot be too long either because the impulse transformer works properly only with variable signals.
In general, to satisfy every load condition, it is very common to control the circuit by a series of pulses (pulse train). In this case, it is mandatory to have a minimum delay time between two successive pulses in order to de-energize the impulse transformer properly. Considering the pulses shown in Figure 11, with a pulse command of 200 μs, it is possible to observe in Figure 11a that only the first pulse can energize the impulse transformer (it can manage the ignition of the SCR). While the second and third pulses cannot reach their peak value (those cannot manage the ignition of the SCR correctly) because the pulses are too close to each other (switching frequency about 3 kHz). Considering Figure 10b, all the pulses with the same pulse command of 200 μs can energize the impulse transformer and consequently can run the SCR (switching frequency about 1.5 kHz).
(a) (b) Figure 11. Impulses with a frequency of (a) around 3 kHz-problems on the second and third pulses (b) around 1.5 kHz-both pulses represented has similar behavior.
In this work, pulses of 200 μs width with a frequency of 1.5 kHz is used to supply Driver Circuit 1 and control the SCR module.
A digital microcontroller is required to generate the pulses for Driver Circuit 1, in certain cases analog circuits can be used, but in general this topology can generate only a series of pulses due to the difficulty in generating the pulses at the desired moment constrained by the limitation of the impulse transformer. Figure 11. Impulses with a frequency of (a) around 3 kHz-problems on the second and third pulses (b) around 1.5 kHz-both pulses represented has similar behavior.
In this work, pulses of 200 µs width with a frequency of 1.5 kHz is used to supply Driver Circuit 1 and control the SCR module.
A digital microcontroller is required to generate the pulses for Driver Circuit 1, in certain cases analog circuits can be used, but in general this topology can generate only a series of pulses due to the difficulty in generating the pulses at the desired moment constrained by the limitation of the impulse transformer.

Driver Circuit 2
The second driver circuit considered in this study adopts an opto-isolator to generate the pulses and manage the necessary gate current to control the SCR properly. The circuit schema is shown in Figure 12. The main difference between the Driver Circuit 2 and Driver Circuit 1, is in the gate current control philosophy. As there is no pulse transformer, it is not necessary to provide a pulse or a series of pulses. This also enables to use a constant DC voltage to ignite the SCR. The simplicity of this driving system is one of the main advantages of this topology. With this, a simple driving circuit (as simple as a push button) can be used to run the circuit. Moreover, the amount of power required to energize the circuit is quite low and hence normally the power loss is reduced.

Driver Circuit 2
The second driver circuit considered in this study adopts an opto-isolator to generate the pulses and manage the necessary gate current to control the SCR properly. The circuit schema is shown in Figure 12. The main difference between the Driver Circuit 2 and Driver Circuit 1, is in the gate current control philosophy. As there is no pulse transformer, it is not necessary to provide a pulse or a series of pulses. This also enables to use a constant DC voltage to ignite the SCR. The simplicity of this driving system is one of the main advantages of this topology. With this, a simple driving circuit (as simple as a push button) can be used to run the circuit. Moreover, the amount of power required to energize the circuit is quite low and hence normally the power loss is reduced.

Driver Circuit Losses Comparison
To evaluate the power losses of the driver circuits, the absorbed current ic from the control power source has to be measured in both circuits. A simple test circuit, as shown in Figure 5, is used in order to evaluate the performance of the two driver circuits. The grid voltage v(t) is 230 V at 50 Hz. The load is 1 kVA R-L load. Here, the aim is to evaluate the losses of the driver circuits. The power circuit is kept the same during both driver topology tests (to relax any possible effect), and the driver circuits are supplied with 15 V ( ) voltage source.
The absorbed current from voltage source (ic) has been measured in both circuits in order to evaluate the absorbed power to manage the driver circuits. In order to measure this current, a small resistance is inserted in series to the driver circuit. This inserted resistance poses no change in the main circuit behavior. The measured voltage across the resistor (given that the ohmic value is known) represents the current in the driver circuit.
Considering that there is an impulse transformer in SCR Driver 1, the current value follows the pulses and has raising and falling edges. In order to evaluate the power for this driver circuit, the mean value of supply voltage VDC multiplied with this current (ic) is considered (7).
In (7) T is the effective average period and ic is the current absorbed from the voltage source VDC.
In case of SCR Driver 2, there is no need to supply the driver circuit with pulses, instead constant VDC = 15 V has been used. Therefore, the current can be a constant DC value. However, in order to avoid the effect of measurement noises in the evaluation of absorbed power, same analysis as in the previous case has been followed. Table 3 reports the losses for the two driver circuits under test. As it can be noticed, SCR Driver 2 has about 25% fewer losses with respect to SCR Driver 1, because the SCR Driver circuit 2 needs a very low amount of current ic. Moreover, considering the low peak current value absorbed by SCR Driver 2 with respect to the SCR Driver 1, the components size in Driver 2 can be reduced and the overall driver circuit size can be decreased. This can also lead to more efficient and cheaper industrial design of the final product. As the opto isolator can work with very low voltage (5 V instead of 15 V)

Driver Circuit Losses Comparison
To evaluate the power losses of the driver circuits, the absorbed current i c from the control power source has to be measured in both circuits. A simple test circuit, as shown in Figure 5, is used in order to evaluate the performance of the two driver circuits. The grid voltage v(t) is 230 V at 50 Hz. The load is 1 kVA R-L load. Here, the aim is to evaluate the losses of the driver circuits. The power circuit is kept the same during both driver topology tests (to relax any possible effect), and the driver circuits are supplied with 15 V (V DC ) voltage source.
The absorbed current from voltage source (i c ) has been measured in both circuits in order to evaluate the absorbed power to manage the driver circuits. In order to measure this current, a small resistance is inserted in series to the driver circuit. This inserted resistance poses no change in the main circuit behavior. The measured voltage across the resistor (given that the ohmic value is known) represents the current in the driver circuit.
Considering that there is an impulse transformer in SCR Driver 1, the current value follows the pulses and has raising and falling edges. In order to evaluate the power for this driver circuit, the mean value of supply voltage V DC multiplied with this current (i c ) is considered (7).
In (7) T is the effective average period and i c is the current absorbed from the voltage source V DC . In case of SCR Driver 2, there is no need to supply the driver circuit with pulses, instead constant V DC = 15 V has been used. Therefore, the current can be a constant DC value. However, in order to avoid the effect of measurement noises in the evaluation of absorbed power, same analysis as in the previous case has been followed. Table 3 reports the losses for the two driver circuits under test. As it can be noticed, SCR Driver 2 has about 25% fewer losses with respect to SCR Driver 1, because the SCR Driver circuit 2 needs a very low amount of current i c . Moreover, considering the low peak current value absorbed by SCR Driver 2 with respect to the SCR Driver 1, the components size in Driver 2 can be reduced and the overall driver circuit size can be decreased. This can also lead to more efficient and cheaper industrial design of the Energies 2020, 13, 3539 14 of 20 final product. As the opto isolator can work with very low voltage (5 V instead of 15 V) the losses of the SCR Driver 2 can be further decreased by adopting the same pulses strategy necessary for Driver 1.

Driver Conduction Delay Comparison
The conduction delay depends on control circuit, control technique, SCR topology, supply voltage RMS V, load power angle ϕ, (resistive, inductive or capacitive or any mix of these types), load impedance magnitude Z, and control pulse angle α. To compare the different control system, the same SCR switch for both driver circuits (so the contribution of the SCR on conduction delay is kept constant around 50 µs in both cases), and the same power circuit, as shown in Figure 5, are used. Moreover, both driving systems are supplied by the same voltage, equal to 15 V as mentioned previously, and managed with the same microcontroller board.
Here, the total conduction delays for the two different driver systems and the three different control strategies are analyzed. These different solutions can be classified according to the type of power supply: These classifications are not completely independent because, as it has been discussed, it is advisable to couple a) with I) or II), and b) with III). Only in some cases is a combination of b) and I) adopted, while the combination of a) and III) cannot work.
When the gate pulse strategy (and in particular for SCR Driver 1) is adopted, the conduction delay could be more higher than the natural time delay of the SCR, especially in an EPM application that needs a unidirectional current for its proper operation and they are controlled with a control phase angle α less than the load power angle ϕ and very close to zero. This can happen due to the variable nature of the load as described in the Table 4, where a load with resistance R = 1 Ω, inductance L = 50 mH, mains voltage of V = 230 V, f = 50 Hz and an SCR with I L = 0.4 A, has been considered. Cases denoted with "/" mean that the strategy works and the pulse duration is enough to ignite the SCR however in other cases denoted by "X" the pulse duration of 200 µs is not enough to ignite the SCR.
Following the theory analyzed before, the results show that the resistance variation has no practical influence on the necessary pulse duration while both the inductance variation and the applied voltage have to be considered as dominant factors. Starting from this point of view, in order to make this control technique efficient, it is mandatory to supply the gate circuit for a time at least equal to the sum of the contributions due to the variation in both the inductance and the voltage.
Therefore, in some cases, the gate pulse has to be wide enough to correctly manage the SCR, and hence this strategy can be adopted only with SCR Driver 2 and cannot be adopted by SCR Driver 1, because the impulse transformer, present in the control circuit can be saturated.
The series gate pulses strategy is used for SCR Driver 1 only, in order to increase the probability to turn-on the SCR. In some cases, the pulses are automatically generated by an analog circuit when a microcontroller is not present to manage the system. In this case, the conduction delay could be higher than the natural delay time of the SCR especially in applications such as EPM that needs unidirectional current and the control phase angle α should stay close to the zero as mentioned.
As in the previous method described, when SCR Driver 1 is driven by a series of pulses, the conduction delay is not constant, and it shows a periodic behavior. This is due to the fact that the pulse signal, which is able to set the SCR in conduction state, cannot always occur at the same moment. Therefore, the conduction delay time varies between the minimum conduction delay (few µs which depends on SCR) and the maximum one (as a function of the delay time used to correctly manage the SCR Driver 1, usually cannot be less than 700 µs). This time can increase for some load typologies, when the starting current is very close to zero and the SCR cannot be switched-on with the first pulse. So in the worst case scenario, a time delay between the two pulses can be necessary (so the delay will reach around 1.4 ms), as example a practical test is reported in Figure 13, where the distance between two pulses has been fixed higher than 700 µs, equal to 1120 µs, in order to eliminate any saturation problems of the impulse transformer. Following the theory analyzed before, the results show that the resistance variation has no practical influence on the necessary pulse duration while both the inductance variation and the applied voltage have to be considered as dominant factors. Starting from this point of view, in order to make this control technique efficient, it is mandatory to supply the gate circuit for a time at least equal to the sum of the contributions due to the variation in both the inductance and the voltage.
Therefore, in some cases, the gate pulse has to be wide enough to correctly manage the SCR, and hence this strategy can be adopted only with SCR Driver 2 and cannot be adopted by SCR Driver 1, because the impulse transformer, present in the control circuit can be saturated.
The series gate pulses strategy is used for SCR Driver 1 only, in order to increase the probability to turn-on the SCR. In some cases, the pulses are automatically generated by an analog circuit when a microcontroller is not present to manage the system. In this case, the conduction delay could be higher than the natural delay time of the SCR especially in applications such as EPM that needs unidirectional current and the control phase angle α should stay close to the zero as mentioned.
As in the previous method described, when SCR Driver 1 is driven by a series of pulses, the conduction delay is not constant, and it shows a periodic behavior. This is due to the fact that the pulse signal, which is able to set the SCR in conduction state, cannot always occur at the same moment. Therefore, the conduction delay time varies between the minimum conduction delay (few µ s which depends on SCR) and the maximum one (as a function of the delay time used to correctly manage the SCR Driver 1, usually cannot be less than 700 μs). This time can increase for some load typologies, when the starting current is very close to zero and the SCR cannot be switched-on with the first pulse. So in the worst case scenario, a time delay between the two pulses can be necessary (so the delay will reach around 1.4 ms), as example a practical test is reported in Figure 13, where the distance between two pulses has been fixed higher than 700 μs, equal to 1120 μs, in order to eliminate any saturation problems of the impulse transformer. Thus, applying this strategy to SCR Driver 1, the conduction delay will be variable, and this can produce unexpected (and unwanted) effects on other parts of the power circuit (reducing performance of the connected power electronic devices, compromising power quality level and it can Thus, applying this strategy to SCR Driver 1, the conduction delay will be variable, and this can produce unexpected (and unwanted) effects on other parts of the power circuit (reducing performance of the connected power electronic devices, compromising power quality level and it can also affect other electronic boards and control systems). Moreover, the variable nature of load and mains voltage may increase the uncertainties in the behavior of the SCR turn-on.
The above-mentioned conduction delay can contribute to load voltage as well as in current distortion and it can contribute to power quality issues at their connection point. Figure 14 shows an example of the distorted load voltage used for total harmonic distortion (THD) analysis and the load current in the case of a 1 kVA load with a power factor equal to 0.6 managed by a SCR in AC back to back configuration controlled by a delay of around 200 µs.
Energies 2020, 13, x FOR PEER REVIEW 16 of 20 also affect other electronic boards and control systems). Moreover, the variable nature of load and mains voltage may increase the uncertainties in the behavior of the SCR turn-on. The above-mentioned conduction delay can contribute to load voltage as well as in current distortion and it can contribute to power quality issues at their connection point. Figure 14 shows an example of the distorted load voltage used for total harmonic distortion (THD) analysis and the load current in the case of a 1 kVA load with a power factor equal to 0.6 managed by a SCR in AC back to back configuration controlled by a delay of around 200 μs. It is worth to mention that, in an ideal system, the interruptions in the voltage is expected to appears as sharp steps (shown by dashed light blue lines in the Figure 14). However, in terms of practical application, there should be a snubber circuit to limit dv/dt on SCR. The simulation results in Figure 14 are obtained using datasheet values of commercial snubber circuit SKRC 440.
Considering the complexity in evaluating the voltage and current distortions in the load, signal data analysis is made in dedicated software to extract the THD values for one case considering SCR Driver 1.
The load connected as mentioned previously is of 1 kVA and its power factor can be varied from 1 to 0.4. The signal data has been elaborated to find the THD of the load voltage. Performing the FFT analysis, the THD value has been evaluated. The voltage THD varies between the range 1.56-4.04% as expected (the minimum value can be considered the contribution of the SCR on conduction (ignition) delay that is equal to 50 μs). These values are as reported in Table 5. Considering this strategy and Driver 1, it can be noticed that the THD is varying and, moreover, cannot be predicted. Even though the power quality indices are small and their contribution always stays within standard [36,37]. However, these are simulation results and considers only SCR effects, in a real system this distortion may be higher. The harmonic propagation will deteriorate the overall system performance which occurred as a consequence of variable conduction delay in the case of Driver 1.
Unlike SCR Driver 1, SCR Driver 2 can be managed by constant command, hence, the total conduction delay is constant and proportional to the contribution of the SCR only. In this topology, a constant DC signal can be adopted as input signal for the SCR gate signal. For the adopted SCR, this conduction delay has been recorded by laboratory test (for resistive load) and as it is reported in Figure 15. The conduction delay is constant, invariable, and equal to 50 µ s (which is the time required by the SCR). To evaluate THD results, similar to previous case, simulations are performed for loads with different power factors and Table 6 reports the obtained THD results. It is worth to mention that, in an ideal system, the interruptions in the voltage is expected to appears as sharp steps (shown by dashed light blue lines in the Figure 14). However, in terms of practical application, there should be a snubber circuit to limit dv/dt on SCR. The simulation results in Figure 14 are obtained using datasheet values of commercial snubber circuit SKRC 440.
Considering the complexity in evaluating the voltage and current distortions in the load, signal data analysis is made in dedicated software to extract the THD values for one case considering SCR Driver 1.
The load connected as mentioned previously is of 1 kVA and its power factor can be varied from 1 to 0.4. The signal data has been elaborated to find the THD of the load voltage. Performing the FFT analysis, the THD value has been evaluated. The voltage THD varies between the range 1.56-4.04% as expected (the minimum value can be considered the contribution of the SCR on conduction (ignition) delay that is equal to 50 µs). These values are as reported in Table 5. Considering this strategy and Driver 1, it can be noticed that the THD is varying and, moreover, cannot be predicted. Even though the power quality indices are small and their contribution always stays within standard [36,37]. However, these are simulation results and considers only SCR effects, in a real system this distortion may be higher. The harmonic propagation will deteriorate the overall system performance which occurred as a consequence of variable conduction delay in the case of Driver 1.
Unlike SCR Driver 1, SCR Driver 2 can be managed by constant command, hence, the total conduction delay is constant and proportional to the contribution of the SCR only. In this topology, a constant DC signal can be adopted as input signal for the SCR gate signal. For the adopted SCR, this conduction delay has been recorded by laboratory test (for resistive load) and as it is reported in Figure 15. The conduction delay is constant, invariable, and equal to 50 µs (which is the time required by the SCR). To evaluate THD results, similar to previous case, simulations are performed for loads with different power factors and Table 6 reports the obtained THD results. Figure 15. Driver 2 example of practical conduction delay response for ohmic load. For the used SCR, this conduction delay has been recorded by laboratory test assuming a resistive load. Red circles show the distortion at the zero-cross of the voltage. Comparing the two different circuit topologies, SCR Driver 1 and gate pulse or series of gate pulses strategy leads to variable conduction delay. This can cause a problem with respect to control of the power, cause issues in power quality, and can also diversely interfere in the performance and operation of other systems. SCR Driver 2 with constant gate signal has a constant conduction delay which depends only on the adopted SCR. Hence, this SCR Driver 2 does not have a power control problem and also helps in reducing power quality issues.

Conclusions
The aim of the paper is to analyze and investigate in detail the parameters that influence the conduction delay of an SCR used in an AC back to back controlling device in order to find a novel and generic solution enhancing the control capability of an SCR for its use in a wide range of loads in industrial applications.
The paper shows that the conduction delay depends on supply voltage magnitude V, load power angle φ, load impedance magnitude Z, and obviously control pulse angle α. In particular, it has been demonstrated that control phase angle α and load inductance L, and supply voltage are very important with respect to the other parameters on minimum pulse duration to get correct conduction of SCR. Therefore, these aspects are considered in applications such as an electro permanent magnet (EPM) that need a unidirectional current in which the control phase angle α can be close to zero and the inductance undergoes considerable variation.
Moreover, the paper introduces, evaluates, and compares two different commonly used driver circuits for SCR application through simulation and practical laboratory tests (SCR Driver 1-realized adopting an impulse transformer and SCR Driver 2 is built using an opto-isolator). Three different and widely used control strategies for these two driver topologies are presented, which include: gate pulse, series of gate pulses, and constant gate signal strategies respectively.
For comparison between the two driver circuits, three aspects are considered: driver system losses, conduction delay on load voltage due to the adopted control circuit strategy and power quality indices. SCR Driver 1 has higher losses and needs a much more complex driving signal which can be generated by digital microcontroller or by a complex analog circuit. However, SCR Driver 2 has lower operational losses, which can be realized and run by much more simple driving system.
From conduction delay point of view, SCR Driver 1 leads to a long and a variable conduction delay, while SCR Driver 2 has a short and constant conduction delay.  Comparing the two different circuit topologies, SCR Driver 1 and gate pulse or series of gate pulses strategy leads to variable conduction delay. This can cause a problem with respect to control of the power, cause issues in power quality, and can also diversely interfere in the performance and operation of other systems. SCR Driver 2 with constant gate signal has a constant conduction delay which depends only on the adopted SCR. Hence, this SCR Driver 2 does not have a power control problem and also helps in reducing power quality issues.

Conclusions
The aim of the paper is to analyze and investigate in detail the parameters that influence the conduction delay of an SCR used in an AC back to back controlling device in order to find a novel and generic solution enhancing the control capability of an SCR for its use in a wide range of loads in industrial applications.
The paper shows that the conduction delay depends on supply voltage magnitude V, load power angle ϕ, load impedance magnitude Z, and obviously control pulse angle α. In particular, it has been demonstrated that control phase angle α and load inductance L, and supply voltage are very important with respect to the other parameters on minimum pulse duration to get correct conduction of SCR. Therefore, these aspects are considered in applications such as an electro permanent magnet (EPM) that need a unidirectional current in which the control phase angle α can be close to zero and the inductance undergoes considerable variation.
Moreover, the paper introduces, evaluates, and compares two different commonly used driver circuits for SCR application through simulation and practical laboratory tests (SCR Driver 1-realized adopting an impulse transformer and SCR Driver 2 is built using an opto-isolator). Three different and widely used control strategies for these two driver topologies are presented, which include: gate pulse, series of gate pulses, and constant gate signal strategies respectively.
For comparison between the two driver circuits, three aspects are considered: driver system losses, conduction delay on load voltage due to the adopted control circuit strategy and power quality indices. SCR Driver 1 has higher losses and needs a much more complex driving signal which can be generated by digital microcontroller or by a complex analog circuit. However, SCR Driver 2 has lower operational losses, which can be realized and run by much more simple driving system. From conduction delay point of view, SCR Driver 1 leads to a long and a variable conduction delay, while SCR Driver 2 has a short and constant conduction delay.
From power quality point of view, the system with SCR Driver 1 leads to variable THD on the load voltage with consideration of the variable nature of load. Instead, with SCR Driver 2, the THD value is almost constant. In both these cases, the THD value always lies within required value specified by the standards and the difference between these two configurations is very small.
In conclusion, we can state that SCR Driver 2, which is based on opto-isolator, shows better performance with respect to SCR Driver 1, which is based on impulse transformer. Hence, SCR Driver 2 can be recommended, since its control and performance do not depend on its control circuit.
We also recall what was previously discussed regarding the importance of minimizing the conduction angle, as minimization of the conduction angle leads to incredible advantages in all those applications in which the final effect (which is also appreciable in terms of better overall performance) is a function of the magnetizing current peak value, which is controlled by the SCR device.
These considerations reported are fully general and applicable, in all applications controlled by SCR, at least in the theoretical aspects.
To address the future research, considering at a higher level, the range of applications for an SCR can be divided into four broad fields, namely AC-AC systems (mostly the topics covered in this paper), AC-DC systems where the solutions offered in this paper should operate with no or minor changes, DC-AC systems, and DC-DC systems. In DC-AC and DC-DC systems, the application of SCR and the solutions proposed in this paper will need further investigation and research. Moreover, the novel driver circuit could be investigated. Those topics are left open for future studies.