State Switched Discrete-Time Model and Digital Predictive Voltage Programmed Control for Buck Converters

: Switched mode power converters are nonlinear systems, and it is a constant challenge to improve their modeling accuracy and control performance. In this paper, a State Switched Discrete-time Model (SSDM) is proposed, which achieves a higher accuracy at a high frequency than that of conventional state averaged models. Instead of averaging the converter states for approximation, the states within each switching cycle are considered in the modeling. Based on total di ﬀ erential equations of switching-ON and switching-OFF durations, the inductor current and output voltage within a cycle are accurately calculated, which derives the SSDM. Furthermore, a Digital Predictive Voltage Programmed (DPVP) control strategy is derived through the SSDM. Through voltage prediction, a suitable duty ratio is calculated that regulates the output voltage to its reference value in the minimum switching cycles. In this way, the converter achieves a very fast load / line transient response and reference tracking speed, and it exhibits a high stability under deviated inductance. Finally, the accuracy of SSDM and the system stability are proved by frequency response analyses and experiments.


Introduction
Switched mode power converters are widely used in industrial applications. They can operate in Continuous Conduction Mode (CCM), Discontinuous Conduction Mode (DCM), and Critical Conduction Mode (CRM). It is usually hard to optimize the transient response with the CCM operation owing to the inductor current lag. To improve the transient performance, both analog and digital control strategies have been explored in the literature. For example, compared to analog approaches, digital controllers provide advantages of programmability, robustness to noise, a compact size, and flexible control algorithm, etc. In [1][2][3], digital circuits are used to carry out current ramp estimation, which solves the ripple oscillation issue in the well-known V 2 control. In [4,5], digital charge balance controllers are proposed to achieve a time-optimal transient response. In terms of non-linear approaches, digital sliding mode controls are preferable strategies for optimizing large signal transients [6][7][8][9][10].
For many digital control strategies, a great challenge that limits the bandwidth is the intrinsic delays in computation and analog-to-digital conversion. In order to address this issue, digital predictive and deadbeat techniques calculate state variables ahead of time, allowing earlier action to stabilize the power converter. In [11], digital predictive current programmed control is proposed with various modes, i.e., peak, valley, and average current modes. With various current sampling rates, predictive average current control can be flexibly realized with different complexities and performances [12]. Other studies have focused on the sensorless realization of predictive current controls, where conventional current sensors are substituted by current observers [13,14]. For example, through current observation, digital dead-beat current controllers can minimize the current error in one control cycle [15,16].
For predictive and many other control strategies, the accuracy of the converter model is a determinant issue that affects the control performance. To facilitate digital controller design and analysis, discrete-time models have been intensely studied [17,18], and a widely accepted modeling approach is state averaging. Although state averaged discrete-time models can be directly derived through standard Z-transform, the transform error leads to a degraded accuracy [19]. In [20], discrete-time models for different converters are derived with a consideration of leading-edge and trailing-edge modulations, and approximate expressions are acquired in the frequency domain. In [21], a geometric state-averaged model and a centric control strategy are proposed to achieve reliable and predictable large-signal transient responses. In [22], a geometric tuning method is proposed for a buck converter with digital current mode control under continuous conduction mode. Using phase-plane geometry, the controller gain is tuned to achieve a proximate time optimal transient response of the output voltage. In [23], a discrete-time hybrid model is derived for a boost converter, and an enumeration-based Model Predictive Control (MPC) strategy improves the transient response in both continuous and discontinuous conduction modes.
Due to the nonlinear nature of switched mode converters, their modeling and control design have always been a great challenge. Accurate converter modeling can benefit high-performance converter design and analysis. However, without a consideration of switching actions and dynamics within a switching cycle, the conventional state-averaging method has a limited accuracy at a high frequency. A recent review on small-signal modeling methods indicates that the conventional averaged models have a low accuracy at high frequencies [24]. When these models are used for optimization, the degraded accuracy can lead to unreliable controller design and stability analysis, especially when a very fast response speed is required.
In this paper, a State Switched Discrete-time Model (SSDM) is proposed, which achieves a higher accuracy at a high frequency than conventional state averaged models. Instead of averaging the converter states for approximation, the dynamic states within each switching cycle are considered in the modeling process. Based on exact differential equations of switching-ON and switching-OFF durations, the inductor current and output voltage within a cycle are accurately calculated. This improves the modeling accuracy, and the discretized result forms the SSDM. Furthermore, a Digital Predictive Voltage Programmed (DPVP) control law is derived through SSDM. Through voltage prediction, a suitable duty ratio is calculated, which regulates the output voltage to its reference value in the minimum switching cycles. Finally, with additional integral compensation and saturation limits, a practical DPVP control strategy is derived. This strategy exhibits a high stability under deviated inductance, and achieves very fast large-signal transient responses. The effectiveness of the proposed strategy is verified by detailed simulations and experiments.
The paper is organized as follows. In Section 2, the state equation of SSDM is derived through total differential equations of switching-ON and switching-OFF durations. In Section 3, the DPVP control law is given, which is designed to regulate the output voltage to its reference value in the minimum switching cycles. Additionally, a practical DPVP control strategy is proposed with an integral compensation and saturation limit for Digital Pulse Width Modulation (DPWM). Section 4 proves the accuracy of SSDM and the stability under DPVP control by open-loop and closed-loop frequency response analyses. Finally, experimental results are given in Section 5 to verify the improved transient response and the robustness to inductance variation. A brief conclusion is given in Section 6.

State Switched Discrete-Time Model
In deriving the proposed SSDM, the inductor current and output voltage are calculated during switching-ON and switching-OFF durations, respectively. Under DPWM, the durations are given switching-ON and switching-OFF durations, respectively. Under DPWM, the durations are given by TON = dT and TOFF = (1 − d)T, where d is the duty ratio and T is the switching period. With a consideration of current and voltage transients within a switching cycle, a buck converter scheme and the state variables are given in Figure 1.
In Figure 1a, L is the power inductance, R is the load resistance, C is the output capacitance, vin is the input voltage, vout is the output voltage, and iL denotes the inductor current. In each switching cycle (Figure 1b)  With a fixed switching cycle, it is obvious that xe is a function of in ,, Since xe in one switching cycle is xs of the next switching cycle, i.e., 1 se x x z   , the discrete-time state space model of the converter is given by Furthermore, the modeling accuracy is determined by the function at the right side of Equations (1) and (2), which will be derived by total differential equations of switching-ON and switching-OFF durations. First, state variables and their derivative values at switching transients are given as constrains to solve the differential equations. Second, differential equations of the inductor current and output voltage are solved for the switching-ON duration, which derive the relationship between xs and xm. Furthermore, differential equations for the switching-OFF duration are solved, which derive the relationship between xm and xe. Finally, the relationship between xs and xe is derived.

State Variables and Their Derivative Values at Switching Transients
For the buck converter, the state variables and their derivative values at switching transients are given in Figure 2, where the inductor current and output voltage at t = 0 are given by (3) In Figure 1a, L is the power inductance, R is the load resistance, C is the output capacitance, v in is the input voltage, v out is the output voltage, and i L denotes the inductor current. In each switching cycle (Figure 1b), the state variables begin with the initial state x s = [i L,s , v out,s ] T , and achieve the transition state With a fixed switching cycle, it is obvious that x e is a function of < x s , d, v in >: Since x e in one switching cycle is x s of the next switching cycle, i.e., x s = x e z −1 , the discrete-time state space model of the converter is given by Furthermore, the modeling accuracy is determined by the function at the right side of Equations (1) and (2), which will be derived by total differential equations of switching-ON and switching-OFF durations. First, state variables and their derivative values at switching transients are given as constrains to solve the differential equations. Second, differential equations of the inductor current and output voltage are solved for the switching-ON duration, which derive the relationship between x s and x m . Furthermore, differential equations for the switching-OFF duration are solved, which derive the relationship between x m and x e . Finally, the relationship between x s and x e is derived.

State Variables and Their Derivative Values at Switching Transients
For the buck converter, the state variables and their derivative values at switching transients are given in Figure 2, where the inductor current and output voltage at t = 0 are given by Additionally, first-order derivatives of these parameters are determined by the instant voltage on the inductor and current through the capacitor. Therefore, at t = 0 + , the derivative values '(0 ) At t = TON, by continuity of the voltage and current signals, it is possible to write The aforementioned values will be used to solve differential equations of the inductor current and output voltage during switching-ON and switching-OFF, respectively.

Inductor Current and Output Voltage during Switching-ON
During switching-ON, the equivalent circuit scheme of the buck converter is as given in Figure  3. Since the voltage on the inductor and current across the capacitor are in out () v v t  and , respectively, derivatives of the current and voltage are given by Equation (7). Additionally, first-order derivatives of these parameters are determined by the instant voltage on the inductor and current through the capacitor. Therefore, at t = 0 + , the derivative values i L (0 + ) and v out (0 + ) are given by At t = T ON , by continuity of the voltage and current signals, it is possible to write At t = T ON + , the instant voltage on the inductor and current through the capacitor are −v out,m and i L,m − v out,m /R, respectively. Therefore, derivatives of the current and voltage are given by The aforementioned values will be used to solve differential equations of the inductor current and output voltage during switching-ON and switching-OFF, respectively.

Inductor Current and Output Voltage during Switching-ON
During switching-ON, the equivalent circuit scheme of the buck converter is as given in Figure 3. Since the voltage on the inductor and current across the capacitor are v in − v out (t) and i L (t) − v out (t)/R, respectively, derivatives of the current and voltage are given by Equation (7).
Using circuit laws and Equation (7), differential equations of i L (t) and v out (t) are given by Using circuit laws and Equation (7), differential equations of () These second-order differential equations have the same characteristic roots, which are Taking Equations (3) and (4) This equation reveals the relationship between xs and xm, which is affected by ON T dT  . These second-order differential equations have the same characteristic roots, which are Furthermore, explicit values of i L (t) and v out (t) are solved as Taking Equations (3) and (4) into Equation (10) yields Finally, substituting t = T ON into Equation (10) gives x m = [i L,m , v out,m ] T , as shown in Equation (12).
This equation reveals the relationship between x s and x m , which is affected by T ON = dT.

Inductor Current and Output Voltage during Switching-OFF
During switching-OFF, the equivalent circuit scheme of the buck converter is as given in Figure 4. Since the voltage on the inductor and current across the capacitor are respectively, derivatives of the current and voltage are given by Equation (13).
Based on Equation (13), differential equations of i L (t − T ON ) and v out (t − T ON ) are given by Energies 2020, 13, 3451 6 of 20

Inductor Current and Output Voltage during Switching-OFF
During switching-OFF, the equivalent circuit scheme of the buck converter is as given in Figure  4. Since the voltage on the inductor and current across the capacitor are , respectively, derivatives of the current and voltage are given by Equation (13).
Based on Equation (13), differential equations of Obviously, Equation (14) has the same characteristic roots as Equation (8), and explicit values of () Taking Equations (5) and (6) into Equation (15)    Obviously, Equation (14) has the same characteristic roots as Equation (8), and explicit values of i L (t) and v out (t) are solved as Taking Equations (5) and (6) into Equation (15) gives Furthermore, substituting t = T ON + T OFF into Equation (15) gives x e = [i L,e , v out,e ] T , as shown in the following: Combining Equation (12) and Equation (17), the relationship between x s and x e is derived as Equation (18): where g 1 (d) and g 2 (d) are given in Equation (19). Furthermore, the variables in Equation (18) are listed in Table 1.
Finally, since x s = x e z −1 is always valid, the state equation of the proposed SSDM is given by This model achieves a higher accuracy than that of conventional state-averaged models, which will be proved by the simulations in Section 4. Furthermore, the SSDM is used to derive the DPVP control strategy.  (18).

Variable
Title Expression

Digital Predictive Voltage Programmed Control
The scheme of the buck converter under DPVP control is given in Figure 5. The DPVP controller needs three Analog to Digital Converters (ADCs) ADCs to sample the input voltage, output voltage, and inductor current. The sampled values are used to calculate g 2 (d) with Equation (20). Furthermore, a look-up-table of g 2 −1 (d) is used to acquire the duty ratio from g 2 (d). Finally, the duty ratio is modulated through DPWM to control the buck converter.
is always valid, the state equation of the proposed SSDM is given by This model achieves a higher accuracy than that of conventional state-averaged models, which will be proved by the simulations in Section 4. Furthermore, the SSDM is used to derive the DPVP control strategy.

Digital Predictive Voltage Programmed Control
The scheme of the buck converter under DPVP control is given in Figure 5. The DPVP controller needs three Analog to Digital Converters (ADCs) ADCs to sample the input voltage, output voltage, and inductor current. The sampled values are used to calculate g2(d) with Equation (20). Furthermore, a look-up-table of is used to acquire the duty ratio from g2(d). Finally, the duty ratio is modulated through DPWM to control the buck converter.   With DPVP control, v out,s should be regulated to v REF in one switching cycle, and the bandwidth of the controller is maximized. The DPVP control law, stability, and saturation issues are analyzed in the following.

DPVP Control Law
The DPVP controller calculates a suitable g 2 (d) and d to shape the output voltage. In an ideal condition, the output voltage can be regulated to track its reference in one switching cycle, as shown in Figure 6a. In the kth switching cycle, v out, is valid, and the converter operates at a steady state. In the k + 1th switching cycle, the reference voltage steps up, which induces a positive voltage error. Furthermore, to eliminate the error, the duty ratio is increased, which ensures v out,s [k Finally, the output voltage re-stabilizes in the k + 2th switching cycle. In this way, v out, In a practical condition, with a consideration of parasitics, the output voltage tracks its reference value in three switching cycles, as shown in Figure 6b. The results are exported from a Matlab-Simulink simulation.
The DPVP control law is derived from the SSDM model. Based on Equation (20), the relationship between < i L,s , v in , v out,s > and g 2 (d) is given by Energies 2020, 13, 3451 8 of 20 Substituting the control object v out,s = v REF z −1 into Equation (21) gives The DPVP controller calculates a suitable g2(d) and d to shape the output voltage. In an ideal condition, the output voltage can be regulated to track its reference in one switching cycle, as shown in Figure 6a. In the kth switching cycle, out, is valid, and the converter operates at a steady state. In the k + 1th switching cycle, the reference voltage steps up, which induces a positive voltage error. Furthermore, to eliminate the error, the duty ratio is increased, which ensures out, out, REF Finally, the output voltage re-stabilizes in the k + 2th switching cycle. In this way, vout,s tracks vREF in one switching cycle, i.e., vout,s = vREFz −1 .
In a practical condition, with a consideration of parasitics, the output voltage tracks its reference value in three switching cycles, as shown in Figure 6b. The results are exported from a Matlab-Simulink simulation.  The DPVP control law is derived from the SSDM model. Based on Equation (20), the relationship between Substituting the control object Furthermore, an inverse function 1 2 () gd  is used to derive the duty ratio, which regulates out ,s v to REF v in one switching cycle.

Stability Analysis and Compensation for a DPVP Controlled Buck Converter
Based on Equation (22), the output voltage can be regulated to vREF in just one switching cycle. In this way, the control loop bandwidth is maximized. However, as a nonlinear control approach, the DPVP control law lacks integral items. This induces steady state error between vout,s and vREF. Besides, an extremely high bandwidth can degrade the robustness to parameter deviations. In order to Furthermore, an inverse function g 2 −1 (d) is used to derive the duty ratio, which regulates v out,s to v REF in one switching cycle.

Stability Analysis and Compensation for a DPVP Controlled Buck Converter
Based on Equation (22), the output voltage can be regulated to v REF in just one switching cycle. In this way, the control loop bandwidth is maximized. However, as a nonlinear control approach, the DPVP control law lacks integral items. This induces steady state error between v out,s and v REF .
Besides, an extremely high bandwidth can degrade the robustness to parameter deviations. In order to eliminate the steady state error and improve the stability, an integral compensator IT/(z − 1) is used to reduce the bandwidth, which forms the control scheme in Figure 7a.  Furthermore, the closed-loop equivalent model is given in Figure 7b, and the closed-loop transfer function from vREF to vout,s is given by Equation (23)   Furthermore, the closed-loop equivalent model is given in Figure 7b, and the closed-loop transfer function from v REF to v out,s is given by Equation (23) has two poles located at (1 ± √ 1 − 4IT)/2. When IT varies from 0 to 1, the variations of the poles are as given in Figure 8. When IT < 1/4, both poles are real, and the bandwidth is degraded by the lower pole. When IT ≥ 1/4, the poles become conjugated to the real axis. As IT increases, the poles move toward the unit cycle, leading to a degraded stability. In order to improve the bandwidth while maintaining the stability, IT should be near to 0.35 when the damping factor is 0.7 and the closed-loop bandwidth is 0.25π/T. The achieved bandwidth is relatively high for DC-DC converters operating in CCM. Furthermore, the closed-loop equivalent model is given in Figure 7b, and the closed-loop transfer function from vREF to vout,s is given by Equation (23) has two poles located at (1 1 4 )/2


. When IT varies from 0 to 1, the variations of the poles are as given in Figure 8. When IT < 1/4, both poles are real, and the bandwidth is degraded by the lower pole. When IT ≥ 1/4, the poles become conjugated to the real axis. As IT increases, the poles move toward the unit cycle, leading to a degraded stability. In order to improve the bandwidth while maintaining the stability, IT should be near to 0.35 when the damping factor is 0.7 and the closed-loop bandwidth is 0.25π/T. The achieved bandwidth is relatively high for DC-DC converters operating in CCM.

Saturation of DPWM
Switched mode power converters are nonlinear systems, where the large-signal performance is limited by DPWM saturation. With DPVP control, the output of g 2 −1 (d) might be greater than unity or lower than zero, which leads to the saturation of DPWM. The saturation issue limits the physical-achievable slew rate of the output voltage and leads to potential instability. Therefore, the input of the integral compensator is limited to eliminate the DPWM saturation, which derives the practical control scheme in Figure 9.

Saturation of DPWM
Switched mode power converters are nonlinear systems, where the large-signal performance is limited by DPWM saturation. With DPVP control, the output of 1 2 () gd  might be greater than unity or lower than zero, which leads to the saturation of DPWM. The saturation issue limits the physicalachievable slew rate of the output voltage and leads to potential instability. Therefore, the input of the integral compensator is limited to eliminate the DPWM saturation, which derives the practical control scheme in Figure 9. Since the achievable duty ratio is between zero and unity, the output voltage of the converter has a limited slew rate. For the buck converter, the output voltage increases along the duty ratio. The variation of the output voltage in one switching cycle reaches its maximum value when d = 1 and reaches its minimum value when d = 0. Therefore, the output voltage slew rate is limited by either d = 1 or d = 0, as shown in Figure 10. Since the achievable duty ratio is between zero and unity, the output voltage of the converter has a limited slew rate. For the buck converter, the output voltage increases along the duty ratio. The variation of the output voltage in one switching cycle reaches its maximum value when d = 1 and reaches its minimum value when d = 0. Therefore, the output voltage slew rate is limited by either d = 1 or d = 0, as shown in Figure 10. Since the achievable duty ratio is between zero and unity, the output voltage of the converter has a limited slew rate. For the buck converter, the output voltage increases along the duty ratio. The variation of the output voltage in one switching cycle reaches its maximum value when d = 1 and reaches its minimum value when d = 0. Therefore, the output voltage slew rate is limited by either d = 1 or d = 0, as shown in Figure 10.  Based on Equation (20), the initial voltage of the next switching cycle is given by v out,s z = a 21 i L,s + a 22 v out,s Therefore, the variation of v out,s in one switching cycle is The magnitude reaches its maximum value when d = 1 and reaches its minimum value when d = 0, as shown in Equation (26).
Therefore, the output voltage slew rate is limited between ∆v out,s_min and ∆v out,s_max , as shown in the following: ∆v out,s_min ≤ ∆v out,s ≤ ∆v out,s_max .
To avoid potential oscillation, this physical saturation should be avoided in the controller design. Since the slew rate is limited by the input of the integral compensator, Equation (28) is applied to the controller.
∆v out,s_min In this way, physical saturation of DPWM is avoided, which eliminates potential oscillations.

Simulations
Simulations were carried out in Matlab to verify the proposed SSDM and DPVP control strategy. The main specifications of the buck converter were the same as presented in Section 5. In the following, the accuracy of SSDM is proved by comparisons to a circuit model and a State Averaged Discrete-time Model (SADM). Additionally, the converter stability under DPVP control is verified through frequency response analyses.

Accuracy of SSDM
In order to verify the accuracy of the proposed SSDM, frequency response analyses were carried out for the SSDM, SADM, and circuit model. The SADM was derived by the Tustin method, which has a higher accuracy than forward and backward methods. The circuit model was constructed by circuit elements, and was used as a reference model. The analyses are given for output voltage responses from the duty ratio, input voltage, and load resistance.
As shown in Figure 11, for the frequency response from d to v out,s , the SADM deviates from the circuit model at a medium and high frequency. The phase error is relatively large, especially at a high frequency, which results in degraded controller design and low-accuracy stability analysis. When 30k ≤ ω < 100k rad/s, the phase error varies from 3.5 to 11 degrees. When ω ≥ 100k rad/s, the phase error is even larger. For SSDM, both the magnitude and phase highly match those of the circuit model.  Figure 12, for the frequency response from vin to vout,s, the SADM also deviates from the circuit model at a medium and high frequency. When 30k ≤ ω < 100k rad/s, the phase error varies from 6 to 21 degrees. When ω ≥ 100k rad/s, the phase error is even larger. For SSDM, both the magnitude and phase highly match those of the circuit model.  As shown in Figure 12, for the frequency response from v in to v out,s , the SADM also deviates from the circuit model at a medium and high frequency. When 30 k ≤ ω < 100 k rad/s, the phase error varies from 6 to 21 degrees. When ω ≥ 100 k rad/s, the phase error is even larger. For SSDM, both the magnitude and phase highly match those of the circuit model.

As shown in
As shown in Figure 13, for the frequency response from R to v out,s , the SADM deviates from the circuit model at a medium frequency. When 30 k ≤ ω < 100 k rad/s, the phase error varies from 2 to 2.5 degrees, which is relatively small. For SSDM, both the magnitude and phase highly match those of the circuit model. Figure 12, for the frequency response from vin to vout,s, the SADM also deviates from the circuit model at a medium and high frequency. When 30k ≤ ω < 100k rad/s, the phase error varies from 6 to 21 degrees. When ω ≥ 100k rad/s, the phase error is even larger. For SSDM, both the magnitude and phase highly match those of the circuit model. As shown in Figure 13, for the frequency response from R to vout,s, the SADM deviates from the circuit model at a medium frequency. When 30 k ≤ ω < 100 k rad/s, the phase error varies from 2 to 2.5 degrees, which is relatively small. For SSDM, both the magnitude and phase highly match those of the circuit model.

Stability under DPVP Control
According to the analyses in Section 3, the DPVP controller regulates the output voltage to the reference voltage in one switching cycle, i.e.,

Stability under DPVP Control
According to the analyses in Section 3, the DPVP controller regulates the output voltage to the reference voltage in one switching cycle, i.e., v out,s = v REF z −1 . Additionally, an integral compensator is used to compensate for the loop, which improves the stability and eliminates the steady state error of the output voltage. In order to validate the performance under DPVP control, frequency responses were investigated for the circuit model and the equivalent model, respectively.
Open-loop frequency analyses were conducted for v REF − > v out,s transients, and the results were compared to verify if v out,s tracks v REF in one switching cycle. As shown in Figure 14a, the frequency response of the circuit model highly matches that of the equivalent model. Without integral compensation, the output voltage under DPVP control tracks v REF in one switching cycle.
In order to eliminate the steady state error and improve the stability, an integral compensator was used to reduce the bandwidth. The closed-loop analyses are given in Figure 14b, where the integral parameter is set as I = 0.35/T. It is obvious that the frequency response of the equivalent model highly matches that of the circuit model. Additionally, no frequency spike is found in the plot, which proves the closed-loop stability under DPVP control.

Stability Regarding Deviated Inductance
Furthermore, the stability was proven in terms of deviated inductance. Suppose that the actual inductance in the converter is L a , while the controller is set with an inductance of L. When L a changes from 0.9 to 1.6 L, the closed-loop frequency analyses for the v REF − > v out,s , v in − > v out,s , and R− > v out,s transients are as plotted in Figures 15-17, respectively.
According to Figure 15, all plots have a decreasing magnitude in a low-frequency range. The near derivative responses indicate zero DC gain, so the output voltage DC value is immune to the load. When L a = 0.9 L, high-frequency oscillation occurs, since a frequency spike is found near π/T. As L a increases, the magnitude decreases at a high frequency and increases around ω = 10 5 rad/s. This indicates a degraded medium frequency performance, while high-frequency oscillation is eliminated. In order to eliminate the steady state error and improve the stability, an integral compensator was used to reduce the bandwidth. The closed-loop analyses are given in Figure 14b, where the integral parameter is set as I = 0.35/T. It is obvious that the frequency response of the equivalent model highly matches that of the circuit model. Additionally, no frequency spike is found in the plot, which proves the closed-loop stability under DPVP control.

Stability Regarding Deviated Inductance
Furthermore, the stability was proven in terms of deviated inductance. Suppose that the actual inductance in the converter is La, while the controller is set with an inductance of L. When La changes from 0.9 to 1.6 L, the closed-loop frequency analyses for the REF Rv  transients are as plotted in Figures 15-17, respectively.
According to Figure 15, all plots have a decreasing magnitude in a low-frequency range. The near derivative responses indicate zero DC gain, so the output voltage DC value is immune to the load. When La = 0.9 L, high-frequency oscillation occurs, since a frequency spike is found near π/T. As La increases, the magnitude decreases at a high frequency and increases around ω = 10 5 rad/s. This indicates a degraded medium frequency performance, while high-frequency oscillation is eliminated.  Figure 16 indicates that the output voltage exhibits little change when the input voltage varies, since all of the magnitudes are very small. Moreover, all plots are derivative in a low-frequency range. Therefore, the output voltage DC value is immune to the input voltage. However, high-frequency oscillation might occur when La is smaller than L, as indicated by the frequency spike at π/T. When La = L, the response has the lowest magnitude and it is near-derivative in all frequency ranges. As La increases, the magnitude of the response increases, which indicates larger deviation during the transient. As shown in Figure 17, the bandwidth of the converter increases along La. Furthermore, highfrequency oscillation occurs when La = 0.9 L, since a frequency spike is found near π/T.
All simulations indicate that potential high-frequency oscillation might occur when La = 0.9 L, while the performance is slightly degraded when La is larger than L. To avoid potential highfrequency oscillations, a practical solution is to design the controller under La = (1.1-1.2) L.  As shown in Figure 17, the bandwidth of the converter increases along La. Furthermore, highfrequency oscillation occurs when La = 0.9 L, since a frequency spike is found near π/T.
All simulations indicate that potential high-frequency oscillation might occur when La = 0.9 L, while the performance is slightly degraded when La is larger than L. To avoid potential highfrequency oscillations, a practical solution is to design the controller under La = (1.1-1.   Figure 16 indicates that the output voltage exhibits little change when the input voltage varies, since all of the magnitudes are very small. Moreover, all plots are derivative in a low-frequency range. Therefore, the output voltage DC value is immune to the input voltage. However, high-frequency oscillation might occur when L a is smaller than L, as indicated by the frequency spike at π/T. When L a = L, the response has the lowest magnitude and it is near-derivative in all frequency ranges. As L a increases, the magnitude of the response increases, which indicates larger deviation during the transient.
As shown in Figure 17, the bandwidth of the converter increases along L a . Furthermore, high-frequency oscillation occurs when L a = 0.9 L, since a frequency spike is found near π/T.
All simulations indicate that potential high-frequency oscillation might occur when L a = 0.9 L, while the performance is slightly degraded when L a is larger than L. To avoid potential high-frequency oscillations, a practical solution is to design the controller under L a = (1.1-1.2) L.

Experiments
Experimental results are given to verify the effectiveness of the proposed DPVP controller. The main specifications of the buck converter are shown in Table 2. The specifications are designed to achieve a typical power rate of 5 W, a current ripple rate of ±0.35, and an output voltage ripple rate Energies 2020, 13, 3451 15 of 20 below 1%. The input/output voltages are selected for point-of-load applications, USB chargers, and an embedded system power supply, etc. A photograph of the prototype is given in Figure 18. An FPGA (Cyclone IV) control board is used to carry out digital control algorithms. The output and input voltages are sampled by ADC (LTC2314-14) modules. A main switch MOSFET (FDS86540) and a diode (NRVTSA4100E) are used as switching components. The output capacitor adopts two 10 µF capacitors (KRM55QR71J106KH01K) connected in parallel. The core material of the inductor is NPH107060, which is adequate for a switching frequency below 200 kHz.

Experiments
Experimental results are given to verify the effectiveness of the proposed DPVP controller. The main specifications of the buck converter are shown in Table 2. The specifications are designed to achieve a typical power rate of 5 W, a current ripple rate of ±0.35, and an output voltage ripple rate below 1%. The input/output voltages are selected for point-of-load applications, USB chargers, and an embedded system power supply, etc.  47  20  5  5  12  10 A photograph of the prototype is given in Figure 18. An FPGA (Cyclone IV) control board is used to carry out digital control algorithms. The output and input voltages are sampled by ADC (LTC2314-14) modules. A main switch MOSFET (FDS86540) and a diode (NRVTSA4100E) are used as switching components. The output capacitor adopts two 10 µ F capacitors (KRM55QR71J106KH01K) connected in parallel. The core material of the inductor is NPH107060, which is adequate for a switching frequency below 200 kHz. The output voltage was measured under disturbances of load, input voltage, and reference voltage. The results under DPVP control were compared with those of a digital current mode controller with Proportional Integral Derivative (PID) PID compensation in the outer loop. For the digital current mode controller, the PID compensator was optimized through the PID tuner toolbox in Matlab. It was designed with a phase margin of 75 degrees and the cross-over frequency was 30k rad/s. Furthermore, the robustness of the system under DPVP control was verified under deviated inductance.

Output Voltage Transient Responses
As shown in Figure 19a, when the load resistance steps from 10 to 5 Ω, the output voltage deviates by −0.6 V and re-stabilizes in 130 μs under digital current mode control with PID compensation. According to the analyses in Section 4, the closed-loop frequency response of the load transient is near-derivative in a low-frequency range and near-integrative in a high-frequency range. The response approximates a typical second-order system with a nature frequency of 70k rad/s. Therefore, with a damping factor of 0.7, the output voltage should re-stabilize in 36 μs. As shown in Figure 19b, the experimental results match with those of the analysis. The output voltage deviates by −0.3 V and re-stabilizes in 40 μs. The output voltage was measured under disturbances of load, input voltage, and reference voltage. The results under DPVP control were compared with those of a digital current mode controller with Proportional Integral Derivative (PID) PID compensation in the outer loop. For the digital current mode controller, the PID compensator was optimized through the PID tuner toolbox in Matlab. It was designed with a phase margin of 75 degrees and the cross-over frequency was 30k rad/s. Furthermore, the robustness of the system under DPVP control was verified under deviated inductance.

Output Voltage Transient Responses
As shown in Figure 19a, when the load resistance steps from 10 to 5 Ω, the output voltage deviates by −0.6 V and re-stabilizes in 130 µs under digital current mode control with PID compensation. According to the analyses in Section 4, the closed-loop frequency response of the load transient is near-derivative in a low-frequency range and near-integrative in a high-frequency range. The response approximates a typical second-order system with a nature frequency of 70 k rad/s. Therefore, with a damping factor of 0.7, the output voltage should re-stabilize in 36 µs. As shown in Figure 19b, the experimental results match with those of the analysis. The output voltage deviates by −0.3 V and re-stabilizes in 40 µs.
As shown in Figure 20a, when the input voltage steps from 12 to 9.5 V, the output voltage drops by 0.8 V and re-stabilizes in 200 µs under digital current mode control with PID compensation. According to Figure 16, the frequency response under DPVP control is near-derivative in all frequency ranges and the magnitude is very low. This indicates a strong rejection to input voltage disturbance. As shown in Figure 20b, the experimental result matches that of the analysis. When the input voltage steps from 12 to 9.5 V, the output voltage deviates by −0.2-0.15 V and re-stabilizes in 60 µs. As shown in Figure 20a, when the input voltage steps from 12 to 9.5 V, the output voltage drops by 0.8 V and re-stabilizes in 200 μs under digital current mode control with PID compensation. According to Figure 16, the frequency response under DPVP control is near-derivative in all frequency ranges and the magnitude is very low. This indicates a strong rejection to input voltage disturbance. As shown in Figure 20b, the experimental result matches that of the analysis. When the input voltage steps from 12 to 9.5 V, the output voltage deviates by −0.2-0.15 V and re-stabilizes in 60 μs. When the reference voltage steps from 5 to 6 V, the output voltage tracks it in 150 μs under digital current mode control with PID compensation. According to the analyses in Section 4, the bandwidth of the closed-loop system is about 65k rad/s. Therefore, with a damping factor of 0.7, the output voltage should reach the reference value in 38 μs. The experimental result matches that of the analysis, as shown in Figure 21b. The output voltage reaches the reference voltage in 30 μs, which is five times faster than that of digital current mode control. As shown in Figure 20a, when the input voltage steps from 12 to 9.5 V, the output voltage drops by 0.8 V and re-stabilizes in 200 μs under digital current mode control with PID compensation. According to Figure 16, the frequency response under DPVP control is near-derivative in all frequency ranges and the magnitude is very low. This indicates a strong rejection to input voltage disturbance. As shown in Figure 20b, the experimental result matches that of the analysis. When the input voltage steps from 12 to 9.5 V, the output voltage deviates by −0.2-0.15 V and re-stabilizes in 60 μs.  When the reference voltage steps from 5 to 6 V, the output voltage tracks it in 150 μs under digital current mode control with PID compensation. According to the analyses in Section 4, the bandwidth of the closed-loop system is about 65k rad/s. Therefore, with a damping factor of 0.7, the output voltage should reach the reference value in 38 μs. The experimental result matches that of the analysis, as shown in Figure 21b. The output voltage reaches the reference voltage in 30 μs, which is five times faster than that of digital current mode control. When the reference voltage steps from 5 to 6 V, the output voltage tracks it in 150 µs under digital current mode control with PID compensation. According to the analyses in Section 4, the bandwidth of the closed-loop system is about 65 k rad/s. Therefore, with a damping factor of 0.7, the output voltage should reach the reference value in 38 µs. The experimental result matches that of the analysis, as shown in Figure 21b. The output voltage reaches the reference voltage in 30 µs, which is five times faster than that of digital current mode control.

The Robustness to Deviated Inductance
According to the closed-loop analyses in Section 4, the converter remains stable when La deviates from 0.9 to 1.6 L. However, high-frequency oscillation might occur when La is smaller than L. When La is larger than L, although the performance is slightly degraded, the high-frequency oscillation is eliminated. Therefore, La can be set a little higher than L to improve the robustness to deviated

The Robustness to Deviated Inductance
According to the closed-loop analyses in Section 4, the converter remains stable when L a deviates from 0.9 to 1.6 L. However, high-frequency oscillation might occur when L a is smaller than L. When L a is larger than L, although the performance is slightly degraded, the high-frequency oscillation is eliminated. Therefore, L a can be set a little higher than L to improve the robustness to deviated inductance. In the following, experimental results are given when L a deviates to 1.3 and 1.6 L, respectively.
When the load resistance steps from 5 to 10 Ω, the output voltage transients are as given in Figure 22. With L a = 1.3 L and L a = 1.6 L, the output voltage suffers from a degraded transient performance. The response time increases to 60 and 70 µs, respectively. When the input voltage steps from 12 to 9.5 V, the output voltage transients are as given in Figure 23. The transient response time increases to 70 and 90 µs, respectively. When the reference voltage steps from 5 to 6 V, the output voltage transients are as given in Figure 24. The output reaches the reference voltage and stabilizes in 50 and 100 µs, respectively. Although the transient responses are degraded with a deviated inductance, the output voltage is still stable when L a = 1.6 L. The results indicate a high robustness of DPVP control to inductance deviation.

The Robustness to Deviated Inductance
According to the closed-loop analyses in Section 4, the converter remains stable when La deviates from 0.9 to 1.6 L. However, high-frequency oscillation might occur when La is smaller than L. When La is larger than L, although the performance is slightly degraded, the high-frequency oscillation is eliminated. Therefore, La can be set a little higher than L to improve the robustness to deviated inductance. In the following, experimental results are given when La deviates to 1.3 and 1.6 L, respectively.
When the load resistance steps from 5 to 10 Ω, the output voltage transients are as given in Figure 22. With La = 1.3 L and La = 1.6 L, the output voltage suffers from a degraded transient performance. The response time increases to 60 and 70 μs, respectively. When the input voltage steps from 12 to 9.5 V, the output voltage transients are as given in Figure 23. The transient response time increases to 70 and 90 μs, respectively. When the reference voltage steps from 5 to 6 V, the output voltage transients are as given in Figure 24. The output reaches the reference voltage and stabilizes in 50 and 100 μs, respectively. Although the transient responses are degraded with a deviated inductance, the output voltage is still stable when La = 1.6 L. The results indicate a high robustness of DPVP control to inductance deviation.   All results match those of the analyses and simulations, and prove the effectiveness of the proposed DPVP control strategy. All results match those of the analyses and simulations, and prove the effectiveness of the proposed DPVP control strategy.

Conclusions
This paper proposes a State Switched Discrete-time Model and Digital Predictive Voltage Programmed controller for a buck converter operating in continuous conduction mode. Compared with the conventional state-averaged modeling method, the SSDM considers the variation of states within a switching cycle, and it achieves a higher accuracy at a medium and high frequency. Furthermore, based on SSDM, a DPVP control law is proposed that regulates the output voltage to its reference value in one switching cycle. Finally, with an integral compensation and saturation limit for DPWM, a practical DPVP control strategy exhibits a high stability and achieves very fast transient responses.
The accuracy of SSDM has been proven by simulations, which were compared with the conventional state averaged discrete-time model and the circuit model. The stability and robustness under DPVP control was proven by open-loop and closed-loop frequency analyses. Finally, the effectiveness of the DPVP controller and the robustness to deviated inductance were verified through experiments.

Conclusions
This paper proposes a State Switched Discrete-time Model and Digital Predictive Voltage Programmed controller for a buck converter operating in continuous conduction mode. Compared with the conventional state-averaged modeling method, the SSDM considers the variation of states within a switching cycle, and it achieves a higher accuracy at a medium and high frequency. Furthermore, based on SSDM, a DPVP control law is proposed that regulates the output voltage to its reference value in one switching cycle. Finally, with an integral compensation and saturation limit for DPWM, a practical DPVP control strategy exhibits a high stability and achieves very fast transient responses.
The accuracy of SSDM has been proven by simulations, which were compared with the conventional state averaged discrete-time model and the circuit model. The stability and robustness under DPVP control was proven by open-loop and closed-loop frequency analyses. Finally, the effectiveness of the DPVP controller and the robustness to deviated inductance were verified through experiments.