Wide-Supply-Voltage-Range CMOS Bandgap Reference for In Vivo Wireless Power Telemetry

: The robustness of the reference circuit in a wide range of supply voltages is crucial in implanted devices. Conventional reference circuits have demonstrated a weak performance over wide supply ranges. Channel-length modulation in the transistors causes the circuit to be sensitive to power supply variation. To solve this inherent problem, this paper proposes a new output-voltage-line-regulation controller circuit. When a variation occurs in the power supply, the controller promptly responds to the supply deviation and removes unwanted current in the output path of the reference circuit. The proposed circuit was implemented in a 0.35- µ m SK Hynix CMOS standard process. The experimental results demonstrated that the proposed reference circuit could generate a reference voltage of 0.895 V under a power supply voltage of 3.3 V, line regulation of 1.85 mV / V in the supply range of 2.3 to 5 V, maximum power supply rejection ratio (PSRR) of − 54 dB, and temperature coe ﬃ cient of 11.9 ppm / ◦ C in the temperature range of 25 to 100 ◦ C.


Introduction
Implantable medical devices (IMDs) are highly demanded in many clinical applications to treat disorders, restore sound, monitor biological parameters of the human body, or restore vision, such as with retinal prosthetics [1,2]. Power to the IMDs must be supplied in vivo from the external world. At the early stage of the IMDs, a wire connection passing through the skin is employed to directly provide power to the implants without a power transfer loss [3,4]. However, the transcutaneous wire connection causes an infection on the skin and soft tissue [5], resulting in the wire no longer being useful. An infrared (IR) technique has been harnessed to wirelessly transfer power to high-density IMDs, i.e., retinal prosthetics [6]. Although the photovoltaic (PV)-powered stimulation chip can partially elicit responses from ganglion cells, the generated power under IR light is too low to drive other functional blocks in the retinal chip, such as a high-density stimulation array, its digital control logic, and back telemetry, which requires high power consumption. Moreover, the IR-based power telemetry has a critical shortcoming in that it is sensitive to the alignment between the light source and implanted chip. The misalignment frequently caused by an eye movement leads to degradation in the power supply. Therefore, the IR-based power telemetry is not suitable for high-density IMDs. 2 of 14 To date, the power telemetry system based on inductively coupled coils is the most popular method to wirelessly transfer high amounts of power to implants in the body [7][8][9][10]. Figure 1 shows the typical architecture of a single-band wireless power telemetry system, in which data signals are modulated on a power carrier [11][12][13]. This near-field inductive link system is composed of a power amplifier (PA), resonance tanks in the transmitting (L 1 and C 1 ) and receiving (L 2 and C 2 ) sides, a rectifier (D 1 and C 3 ), a bandgap voltage reference (BGR) circuit, and a low-voltage drop regulator (LDO). The coil L 1 captures the AC signal from the power amplifier. The amplified radio frequency (RF) signal is transmitted to L 2 at the desired resonance frequency. The received AC voltage is converted to a rough direct current (DC) voltage with a ripple passing through the rectifier, which is then regulated by the LDO to provide sufficient supply voltages for the digital and analog circuits in the IMD.
Energies 2020, 13, x FOR PEER REVIEW 2 of 14 in the power supply. Therefore, the IR-based power telemetry is not suitable for high-density IMDs.
To date, the power telemetry system based on inductively coupled coils is the most popular method to wirelessly transfer high amounts of power to implants in the body [7][8][9][10]. Figure 1 shows the typical architecture of a single-band wireless power telemetry system, in which data signals are modulated on a power carrier [11][12][13]. This near-field inductive link system is composed of a power amplifier (PA), resonance tanks in the transmitting (L1 and C1) and receiving (L2 and C2) sides, a rectifier (D1 and C3), a bandgap voltage reference (BGR) circuit, and a low-voltage drop regulator (LDO). The coil L1 captures the AC signal from the power amplifier. The amplified radio frequency (RF) signal is transmitted to L2 at the desired resonance frequency. The received AC voltage is converted to a rough direct current (DC) voltage with a ripple passing through the rectifier, which is then regulated by the LDO to provide sufficient supply voltages for the digital and analog circuits in the IMD. For this power telemetry system using inductively coupled coils, achieving a high power transfer efficiency is essential to minimize the power loss that results in secondary heating effects on the tissue [14]. However, the movement of a patient with the implantable device in his or her body sometimes causes misalignment between coils, thereby degrading the coupling coefficient. This results in variation in the amplitude of the receiving signal, which leads to inefficient rectification. Therefore, the rectified DC signal from the variation in the received power signal should be constantly regulated, and a wide range of input voltages should be provided for other circuits, such as the stimulation array and its digital controllers.
A BGR circuit has a critical function in generating a constant reference voltage (VREF in Figure 1), which is applied to the voltage regulator circuit. The input signal of the BGR depends on the output of the rectifier, and thus the BGR should be immune to any variation in the rectified signal. In addition, the BGR has been known to be stable regardless of any changes in a device process or temperature [15]. The crucial element in the BGR is a current mirror, in which the current generated at the output stage of the BGR should be exactly matched with the proportional-to-absolutetemperature (PTAT) current. Among the various schemes for the current mirror [15], the cascode current mirror has been widely employed in voltage reference circuits to increase the line regulation and power supply rejection ratio (PSRR) [11][12][13]16]. This is because the cascode structure can suppress the channel-length modulation effect, although minimum-length transistors are adopted in the circuit [15]. The cascode also effectively increases the output resistance of the current mirror circuit. However, the cascode current mirror has two major disadvantages. First, it undergoes a body effect that causes a threshold offset because the source terminals of transistors are different. This disadvantage can be resolved by applying a higher current to the cascode structure circuit. Although this method can significantly decrease the deleterious effect of the threshold offset, it leads to a high power dissipation, which is not suitable for the IMDs operating with low power in the body. Second, the cascode structure requires a high supply voltage to drive all transistors in the saturation region, thus resulting in high power consumption. These two technical challenges become more significant in a nanometer complementary metal-oxide-semiconductor (CMOS) process that operates with low For this power telemetry system using inductively coupled coils, achieving a high power transfer efficiency is essential to minimize the power loss that results in secondary heating effects on the tissue [14]. However, the movement of a patient with the implantable device in his or her body sometimes causes misalignment between coils, thereby degrading the coupling coefficient. This results in variation in the amplitude of the receiving signal, which leads to inefficient rectification. Therefore, the rectified DC signal from the variation in the received power signal should be constantly regulated, and a wide range of input voltages should be provided for other circuits, such as the stimulation array and its digital controllers.
A BGR circuit has a critical function in generating a constant reference voltage (V REF in Figure 1), which is applied to the voltage regulator circuit. The input signal of the BGR depends on the output of the rectifier, and thus the BGR should be immune to any variation in the rectified signal. In addition, the BGR has been known to be stable regardless of any changes in a device process or temperature [15]. The crucial element in the BGR is a current mirror, in which the current generated at the output stage of the BGR should be exactly matched with the proportional-to-absolute-temperature (PTAT) current. Among the various schemes for the current mirror [15], the cascode current mirror has been widely employed in voltage reference circuits to increase the line regulation and power supply rejection ratio (PSRR) [11][12][13]16]. This is because the cascode structure can suppress the channel-length modulation effect, although minimum-length transistors are adopted in the circuit [15]. The cascode also effectively increases the output resistance of the current mirror circuit. However, the cascode current mirror has two major disadvantages. First, it undergoes a body effect that causes a threshold offset because the source terminals of transistors are different. This disadvantage can be resolved by applying a higher current to the cascode structure circuit. Although this method can significantly decrease the deleterious effect of the threshold offset, it leads to a high power dissipation, which is not suitable for the IMDs operating with low power in the body. Second, the cascode structure requires a high supply voltage to drive all transistors in the saturation region, thus resulting in high power consumption. These two technical challenges become more significant in a nanometer complementary metal-oxide-semiconductor (CMOS) process that operates with low voltage [15]. Accordingly, a new method for the current mirror in BGR is required to decrease the deleterious effect due to the channel-length modulation.
In this paper, we propose a novel technique to mitigate this deleterious effect. The proposed BGR circuit was equipped with a line regulation control circuit to decrease the channel-length modulation effect in contrast with the proposed works in [17][18][19][20][21]. A basic current mirror [15] was used in the proposed BGR along with the line regulation control circuit adopted at the output stage. The proposed controller dynamically responded to the supply variation and maintained a constant current in the output path, ensuring a stable reference voltage over a wide supply range. In addition, the deviation in the output voltage due to temperature variation was minimized by employing a curvature-corrected control circuit in the proposed BGR. Diode-connected MOS transistors operating in the sub-threshold region were adopted to generate a high-order temperature coefficient that behaved in a manner opposite to that of the bipolar transistor constructed in the conventional BGRs. A high PSRR was achieved by employing a high-gain amplifier that rejected the variation in the power supply. The proposed BGR circuit was designed and fabricated using a 0.35-µm SK Hynix CMOS standard process.
The paper is organized as follows. Section 2 explains the designed architecture of the conventional and proposed BGRs. The working principles of the conventional and proposed BGRs are discussed. Section 3 outlines the simulation and measurement results. Finally, Section 4 concludes this paper.

Conventional BGR Scheme
The conventional BGR schematic is shown in Figure 2 [15]. The BGR output voltage, V REF , is the summation of a positive-coefficient voltage V PTAT and a negative-coefficient voltage V CTAT , as shown in the top right corner of Figure 2. The conventional BGR is composed of a startup-circuit, PTAT current generator, and complementary-to-absolute temperature voltage (CTAT) generator that is produced by the bipolar junction transistor Q 3 . The high-gain amplifier (AMP) forces the voltage at node V A to be equal to that at node V B . From the relationship between the emitter-based voltages V EB of Q 1 and Q 2 , I PTAT can be derived as follows: where V T is the thermal voltage, and n is the emitter-area ratio of Q 1 and Q 2 . Under the condition that the transistors M P3 and M P2 are identical in size, I PTAT is copied into transistor M P3 from M P2 . The output voltage V REF of the conventional BGR can be expressed as: By selecting appropriate resistances for R 1 and R 2 , we can lower the temperature coefficient of the conventional BGR output voltage. However, the nonlinear voltage of V EB3 means the zero-temperature coefficient is difficult to accomplish.
In practice, I PTAT is not mirrored exactly from M P2 to M P3 because of the channel-length modulation in these transistors. As a result, Equation (2) requires modification. Conventional BGR presented in [15]. Figure 3 depicts the channel-length modulation phenomenon, in which the drain current IDS of an N-metal-oxide semiconductor (NMOS) transistor is illustrated as an example. When the NMOS drain-source voltage VDS increases, the length of the inverted channel region decreases, leaving a gap of non-inverted silicon called a pinch-off region. In the saturation region, IDS is expressed as [15]: where µ is the effective mobility of carriers in the channel; Cox is the oxide thickness; W and L are the transistor width and length, respectively; VGS, VTH, and VDS are the gate-source, threshold, and drainsource voltages of the NMOS transistor, respectively; and λ is the channel-length modulation coefficient of the NMOS transistor that has the range of 0.05 to 0.005 V -1 [22]. The terms λ and VDS that arise from the channel-length modulation result in the mismatch of IPTAT between MP2 and MP3. By considering λ and VDS, Equation (2) can be modified as: Here, λ2 is assumed to become zero because MP2 holds the PTAT current provided in Equation (1). Therefore, Equation (4) can be approximated to: Here, note that VREF is directly proportional to VDD because of a finite λ. This means that a variation in VDD, which indicates the rectified DC voltage (VREC) with a ripple in Figure 1, can deteriorate the BGR output voltage VREF.  Conventional BGR presented in [15]. Figure 3 depicts the channel-length modulation phenomenon, in which the drain current I DS of an N-metal-oxide semiconductor (NMOS) transistor is illustrated as an example. When the NMOS drain-source voltage V DS increases, the length of the inverted channel region decreases, leaving a gap of non-inverted silicon called a pinch-off region. In the saturation region, I DS is expressed as [15]: where µ is the effective mobility of carriers in the channel; C ox is the oxide thickness; W and L are the transistor width and length, respectively; V GS , V TH , and V DS are the gate-source, threshold, and drain-source voltages of the NMOS transistor, respectively; and λ is the channel-length modulation coefficient of the NMOS transistor that has the range of 0.05 to 0.005 V −1 [22]. The terms λ and V DS that arise from the channel-length modulation result in the mismatch of I PTAT between M P2 and M P3 . By considering λ and V DS , Equation (2) can be modified as: Energies 2020, 13, x FOR PEER REVIEW 4 of 14 Figure 2. Conventional BGR presented in [15]. Figure 3 depicts the channel-length modulation phenomenon, in which the drain current IDS of an N-metal-oxide semiconductor (NMOS) transistor is illustrated as an example. When the NMOS drain-source voltage VDS increases, the length of the inverted channel region decreases, leaving a gap of non-inverted silicon called a pinch-off region. In the saturation region, IDS is expressed as [15]: where µ is the effective mobility of carriers in the channel; Cox is the oxide thickness; W and L are the transistor width and length, respectively; VGS, VTH, and VDS are the gate-source, threshold, and drainsource voltages of the NMOS transistor, respectively; and λ is the channel-length modulation coefficient of the NMOS transistor that has the range of 0.05 to 0.005 V -1 [22]. The terms λ and VDS that arise from the channel-length modulation result in the mismatch of IPTAT between MP2 and MP3. By considering λ and VDS, Equation (2) can be modified as: Here, λ2 is assumed to become zero because MP2 holds the PTAT current provided in Equation (1). Therefore, Equation (4) can be approximated to: Here, note that VREF is directly proportional to VDD because of a finite λ. This means that a variation in VDD, which indicates the rectified DC voltage (VREC) with a ripple in Figure 1, can deteriorate the BGR output voltage VREF.  Here, λ 2 is assumed to become zero because M P2 holds the PTAT current provided in Equation (1). Therefore, Equation (4) can be approximated to: Here, note that V REF is directly proportional to V DD because of a finite λ. This means that a variation in V DD , which indicates the rectified DC voltage (V REC ) with a ripple in Figure 1, can deteriorate the BGR output voltage V REF .

Proposed BGR
The proposed BGR concept is depicted in Figure 4, where MOS transistors operating in the sub-threshold region are utilized to generate a high-order temperature coefficient instead of bipolar junction transistors (BJTs). To effectively compensate for the deviation in V REF that arises from inconsistent V DD (= V REC in Figure 1) and temperatures related to V T in Equation (5), we devised a new line regulation controller (LRC) and temperature variation controller (TVC) for the BGR circuit. First, the LRC works to compensate for the variation in V REF , termed ∆V here, which is affected by the change in V DD (= V REC in Figure 1). Specifically, ∆V is subtracted by the LRC output voltage (V LR ) that has the same slope as V REF (Figure 4a). As a result, the proposed BGR can output a constant V REF that is insensitive to variation in V DD (Figure 4c). Second, the TVC performs a function in compensating for temperature variation in BGR, thereby producing a constant V REF . The MOS transistors adopted to configure the proposed BGR in this design generate a positive temperature coefficient between T 1 and T 2 (Figure 4b). This is subtracted by the TVC's non-linear output voltage V NL , which has a shape similar to that of V REF . Thus, the proposed BGR can generate a constant voltage over a wide temperature range ( Figure 4d). Finally, the high-gain amplifier (AMP) adopted in Figure 5 can minimize variation in V REF occurring at high frequencies by continuously tracking the ripples of the unregulated supply voltage.

Proposed BGR
The proposed BGR concept is depicted in Figure 4, where MOS transistors operating in the subthreshold region are utilized to generate a high-order temperature coefficient instead of bipolar junction transistors (BJTs). To effectively compensate for the deviation in VREF that arises from inconsistent VDD (= VREC in Figure 1) and temperatures related to VT in Equation (5), we devised a new line regulation controller (LRC) and temperature variation controller (TVC) for the BGR circuit. First, the LRC works to compensate for the variation in VREF, termed ΔV here, which is affected by the change in VDD (= VREC in Figure 1). Specifically, ΔV is subtracted by the LRC output voltage (VLR) that has the same slope as VREF (Figure 4a). As a result, the proposed BGR can output a constant VREF that is insensitive to variation in VDD (Figure 4c). Second, the TVC performs a function in compensating for temperature variation in BGR, thereby producing a constant VREF. The MOS transistors adopted to configure the proposed BGR in this design generate a positive temperature coefficient between T1 and T2 (Figure 4b). This is subtracted by the TVC's non-linear output voltage VNL, which has a shape similar to that of VREF. Thus, the proposed BGR can generate a constant voltage over a wide temperature range (Figure 4d). Finally, the high-gain amplifier (AMP) adopted in Figure 5 can minimize variation in VREF occurring at high frequencies by continuously tracking the ripples of the unregulated supply voltage.  Figure 5 shows the proposed BGR circuit consisting of a start-up circuit, PTAT current generator, LRC, and TVC. The high-gain amplifier (AMP) in the PTAT generator is realized using a two-stage amplifier with a p-type MOS (PMOS) input differential pair. In the proposed circuit, the transistors Q1 and Q2 in the conventional BGR are replaced with MN1 and MN2, both of which operate in the subthreshold region.  Figure 5 shows the proposed BGR circuit consisting of a start-up circuit, PTAT current generator, LRC, and TVC. The high-gain amplifier (AMP) in the PTAT generator is realized using a two-stage amplifier with a p-type MOS (PMOS) input differential pair. In the proposed circuit, the transistors Q 1 and Q 2 in the conventional BGR are replaced with M N1 and M N2 , both of which operate in the sub-threshold region. As a result, the drain current of MN1 and MN2 in the sub-threshold region is given as: where k is the Boltzmann constant; T is the temperature; q is the electron charge; W and L are the width and length of the transistor, respectively; µ is the effective mobility of carriers in the channel; and C0 is an oxide capacitance. The parameters m and n1 are the process-dependent parameters of the transistor. In the PTAT current generator in Figure 5, VA becomes equal to VB because of the highgain amplifier; therefore: From Equation (7), I1 can be expressed as: By substituting Equation (9) into (8), the expression for I1 is modified as: VREF can be derived from the circuit in Figure 5 as follows: where α is the ratio of the size of MP5 to that of MP2. By substituting Equations (10) into (11) and incorporating the channel-length modulation in MP5, the output voltage reference VREF results in the following form: Equation (12) can be rewritten as: As a result, the drain current of M N1 and M N2 in the sub-threshold region is given as: where k is the Boltzmann constant; T is the temperature; q is the electron charge; W and L are the width and length of the transistor, respectively; µ is the effective mobility of carriers in the channel; and C 0 is an oxide capacitance. The parameters m and n 1 are the process-dependent parameters of the transistor.
In the PTAT current generator in Figure 5, V A becomes equal to V B because of the high-gain amplifier; therefore: From Equation (7), I 1 can be expressed as: where ∆V GS expressed as (derivation of ∆V GS shown in Appendix A): By substituting Equation (9) into (8), the expression for I 1 is modified as: Energies 2020, 13, 2986 7 of 14 V REF can be derived from the circuit in Figure 5 as follows: where α is the ratio of the size of M P5 to that of M P2 . By substituting Equations (10) into (11) and incorporating the channel-length modulation in M P5 , the output voltage reference V REF results in the following form: Equation (12) can be rewritten as: where V REF0 is the voltage reference with no effect of the channel length-modulation, given as: Unlike Equation (5), Equation (13), which arises from the proposed BGR circuit, has additional terms, V REF1 and V LR , which are used to compensate for the variation in V REF . The variation in V REF with respect to V DD can be eliminated when: Note that the source-drain voltage of the PMOS transistor M P9 is constant, and I 5 proportionally changes with V DD because of the gate voltage V Y of M P9 . In contrast, the gate terminal of M P7 , depending on the V REF node, is always constant and the source voltage changes only when variation occurs in V DD . This means that we can obtain a zero-slope V REF in Equation (13) by adjusting I 2 , which is determined by properly selecting the size of M P7 . Therefore, the proposed BGR circuit can generate a constant V REF that is immune to variation in V DD .
The temperature dependency of V REF can be analyzed using Equation (12), which can be rewritten as: We can observe the existence of two terms in Equation (16) contributing to the PTAT voltage, while V GS6 and I 5 R 2 generate the CTAT voltage and second-order curvature correction, respectively, in this scenario. The study in [23] reported that the parameter n 1 in Equation (16) is not constant; consequently, the parabolic shape of ∆V GS was produced due to the variation in n 1 . The output voltage variation due to n 1 is compensated by generating V NL as shown in Equation (16). Referring to Figure 5, M P9 is biased from the CTAT voltage V Y , thereby allowing additional current I 5 to flow through the transistor as the temperature increases. V Y is generated across M N4 , and this can be explained by first considering the PTAT current I 3 , which flows through M P6 . Accordingly, the source voltages of M P6 and M P7 and the gate voltage of M P4 increase proportionally with the temperature. With the fixed voltage of V DD , the drain voltage of M P4 decreases, maintaining M N4 in the triode region. In the proposed design, the low voltage of V Y is produced in the millivolt range such that the gate-source voltage of M P9 is larger than its threshold voltage. Table 1 shows all parameters used for the proposed BGR in Figure 5. Table 1. Parameters for transistors and resistors used for the proposed BGR circuit.

Component
Parameter Component Parameter

Simulation and Experimental Results
The proposed BGR circuit was designed using Cadence IC6.1.5 and Calibre v2014 and then was fabricated in an SK Hynix 0.35-µm CMOS standard process. Figure 6 shows the BGR's microchip photograph and layout that occupied an active area of 112 µm × 60 µm. Common centroid and interdigitated layout techniques were used to decrease the process gradient effects between transistors and resistors.  Figure 7 shows the DC response simulation results of the proposed BGR in which the supply voltage varied from 0 to 5 V. The waveforms in Figure 7 corroborate the important currents and voltages in Equations (11) to (15). As expected, αI1 and I2 (both are indicated in Figure 7a) increased with increasing VDD, while I5 behaved conversely to αI1 and I2. As Equation (13) indicates, VLR was the voltage drop across R2 and was the established voltage resulting from the sum of I2 and I5 in R2. By optimizing I2 in VLR, a nearly zero-slope I4 (I4 = αI1-I2-I5) was produced as VDD varied from 2 to 5 V (Figure 7a). The stable current of I4 satisfied the condition stated in Equation (15); as a result, a supplyinsensitive VREF was generated (Figure 7b).  Figure 7 shows the DC response simulation results of the proposed BGR in which the supply voltage varied from 0 to 5 V. The waveforms in Figure 7 corroborate the important currents and voltages in Equations (11) to (15). As expected, αI 1 and I 2 (both are indicated in Figure 7a) increased with increasing V DD , while I 5 behaved conversely to αI 1 and I 2 . As Equation (13) indicates, V LR was the voltage drop across R 2 and was the established voltage resulting from the sum of I 2 and I 5 in R 2 . By optimizing I 2 in V LR , a nearly zero-slope I 4 (I 4 = αI 1 -I 2 -I 5 ) was produced as V DD varied from 2 to 5 V (Figure 7a). The stable current of I 4 satisfied the condition stated in Equation (15); as a result, a supply-insensitive V REF was generated (Figure 7b).
Using an Agilent parameter analyzer (Model 4156C), we measured V REF and M P7 s source voltage, which are depicted in Figure 8. As a measured result, V REF had a variation of 4.8 mV over the supply voltage ranges that varied from 2.3 to 5 V. This resulted in a static supply dependency of +1.8 mV/V. The mismatch of 11.1% between the measured result of +1.8 mV/V and the simulated one of +1.6 mV/V emanated from random process mismatches [24]. Overall, the graph of V REF shown in Figure 8a  with increasing VDD, while I5 behaved conversely to αI1 and I2. As Equation (13) indicates, VLR was the voltage drop across R2 and was the established voltage resulting from the sum of I2 and I5 in R2. By optimizing I2 in VLR, a nearly zero-slope I4 (I4 = αI1-I2-I5) was produced as VDD varied from 2 to 5 V (Figure 7a). The stable current of I4 satisfied the condition stated in Equation (15); as a result, a supplyinsensitive VREF was generated (Figure 7b). Using an Agilent parameter analyzer (Model 4156C), we measured VREF and MP7′s source voltage, which are depicted in Figure 8. As a measured result, VREF had a variation of 4.8 mV over the supply voltage ranges that varied from 2.3 to 5 V. This resulted in a static supply dependency of +1.8 mV/V. The mismatch of 11.1% between the measured result of +1.8 mV/V and the simulated one of +1.6 mV/V emanated from random process mismatches [24]. Overall, the graph of VREF shown in Figure 8a agreed with the simulated VREF shown in Figure 7b.  Figure 8b shows the non-linear increment of the source voltage of MP7 as VDD increased, which contributed to I2 shown in Figure 5. When VDD increased to 4 V, the slope of the signal became more positive until 5 V. This can be explained by referring to the graph of I5 in Figure 7a. When VDD was 4 V, I5 decreased, causing more current to flow through R2, which produced a higher VREF. Here, MP6 operated in the triode region and acted as an active resistor, thereby increasing the voltage at the source terminal of MP7 to maintain the same current supplied by MP5. MP7 performed the function of sinking as much current as that caused by the increase in the source terminal voltage (Figure 8b), thereby pulling VREF back to its initial voltage level. Figure 9a,b show the measured temperature variation in the proposed BGR and the simulated temperature compensation current I5. In this experiment, we set the operating temperature range to change from 25 to 100 °C under a power supply voltage of 3.3 V, where a maximum variation error of 0.8 mV was observed. The quadratic curve in Figure 9a verified the proposed temperature compensation technique. VNL, which is shown in Equation (16), was the product of I5 and R2. As Figure  9b shows, the simulated I5 increased with the temperature. Accordingly, VNL, shown in Figure 4b, increased and significantly pulled the VREF down at high temperatures. This was because the slope of S1 was higher than that of S2 (Figure 9b). Therefore, MP9 ( Figure 5) operated to significantly decrease the temperature variation in the reference voltage.  Figure 8b shows the non-linear increment of the source voltage of M P7 as V DD increased, which contributed to I 2 shown in Figure 5. When V DD increased to 4 V, the slope of the signal became more positive until 5 V. This can be explained by referring to the graph of I 5 in Figure 7a. When V DD was 4 V, I 5 decreased, causing more current to flow through R 2 , which produced a higher V REF . Here, M P6 operated in the triode region and acted as an active resistor, thereby increasing the voltage at the source terminal of M P7 to maintain the same current supplied by M P5 . M P7 performed the function of sinking as much current as that caused by the increase in the source terminal voltage (Figure 8b), thereby pulling V REF back to its initial voltage level. Figure 9a,b show the measured temperature variation in the proposed BGR and the simulated temperature compensation current I 5 . In this experiment, we set the operating temperature range to change from 25 to 100 • C under a power supply voltage of 3.3 V, where a maximum variation error of 0.8 mV was observed. The quadratic curve in Figure 9a verified the proposed temperature compensation technique. V NL , which is shown in Equation (16), was the product of I 5 and R 2 . As Figure 9b shows, the simulated I 5 increased with the temperature. Accordingly, V NL , shown in Figure 4b, increased and significantly pulled the V REF down at high temperatures. This was because Energies 2020, 13, 2986 10 of 14 the slope of S 1 was higher than that of S 2 (Figure 9b). Therefore, M P9 ( Figure 5) operated to significantly decrease the temperature variation in the reference voltage. temperature compensation current I5. In this experiment, we set the operating temperature range to change from 25 to 100 °C under a power supply voltage of 3.3 V, where a maximum variation error of 0.8 mV was observed. The quadratic curve in Figure 9a verified the proposed temperature compensation technique. VNL, which is shown in Equation (16), was the product of I5 and R2. As Figure  9b shows, the simulated I5 increased with the temperature. Accordingly, VNL, shown in Figure 4b, increased and significantly pulled the VREF down at high temperatures. This was because the slope of S1 was higher than that of S2 (Figure 9b). Therefore, MP9 ( Figure 5) operated to significantly decrease the temperature variation in the reference voltage.  We also measured the power supply rejection ratio of the proposed BGR, where the frequency of a sinusoidal ripple signal swept from 1 Hz to 100 kHz was directly applied to V DD shown in Figure 5 without any off-chip filtering capacitors ( Figure 10). This result indicated that the proposed BGR can achieve a maximum PSRR of 54 dB within a frequency band of 1 kHz. The PSRR would be further improved if we add power capacitors to pass the ripple in the supply rail to the ground. We also measured the power supply rejection ratio of the proposed BGR, where the frequency of a sinusoidal ripple signal swept from 1 Hz to 100 kHz was directly applied to VDD shown in Figure  5 without any off-chip filtering capacitors ( Figure 10). This result indicated that the proposed BGR can achieve a maximum PSRR of 54 dB within a frequency band of 1 kHz. The PSRR would be further improved if we add power capacitors to pass the ripple in the supply rail to the ground. The proposed BGR chip performance was demonstrated using a verification platform of the subretinal implant shown in Figure 11a. The transmitter system is composed of a class-E power amplifier and an amplitude-shift-keying (ASK) modulator circuit that is controlled by a microprocessor unit. The power and data signal are wirelessly delivered to the subretinal prosthesis passing through the inductive link. The receiver architecture consists of a rectifier, a regulator (including the proposed BGR circuit) to generate four different supply voltages of ±1.65 V and ±2.5 V, a demodulator to recover the modulated ASK signal, a digital controller, and a stimulator array. Here, the stimulator works to inject a biphasic current pulse into the bipolar cell inside the eyeball through a microelectrode. The power amplifier transmitted the ASK signal with a data rate of 50 kb/s, peak-to-peak magnitude of 8.6 V, and modulation index of 50%, which was modulated on a power The proposed BGR chip performance was demonstrated using a verification platform of the subretinal implant shown in Figure 11a. The transmitter system is composed of a class-E power amplifier and an amplitude-shift-keying (ASK) modulator circuit that is controlled by a microprocessor unit. The power and data signal are wirelessly delivered to the subretinal prosthesis passing through the inductive link. The receiver architecture consists of a rectifier, a regulator (including the proposed BGR circuit) to generate four different supply voltages of ±1.65 V and ±2.5 V, a demodulator to recover the modulated ASK signal, a digital controller, and a stimulator array. Here, the stimulator works to inject a biphasic current pulse into the bipolar cell inside the eyeball through a microelectrode. The power amplifier transmitted the ASK signal with a data rate of 50 kb/s, peak-to-peak magnitude of 8.6 V, and modulation index of 50%, which was modulated on a power carrier with a clock frequency of 13.56 MHz (zoomed signal in Figure 11b top); the receiver passed through the inductive coils that were placed at the distance of 0.7 cm. The received AC signals (Figure 11b middle) were rectified and fed into the proposed BGR chip. Figure 11b

Conclusions
A novel BGR circuit for wide-supply-voltage-range applications was presented in this paper. The simple implementation of the line regulation and temperature control circuits results in a small active area of the fabricated chip using 0.35-μm SK Hynix CMOS standard process. The overall size of the proposed chip is 0.0067 mm 2 . The experimental results prove that the line regulation control circuit stabilizes the output voltage by sinking out some undesirable current due to the supply variation. The temperature compensation circuit clamps the output voltage regardless of the changes  Table 2 summarizes the overall performance of the proposed BGR at a room temperature of 27 • C along with the bandgap voltage reference circuits in [18,19] for comparison.

Conclusions
A novel BGR circuit for wide-supply-voltage-range applications was presented in this paper. The simple implementation of the line regulation and temperature control circuits results in a small active area of the fabricated chip using 0.35-µm SK Hynix CMOS standard process. The overall size of the proposed chip is 0.0067 mm 2 . The experimental results prove that the line regulation control circuit stabilizes the output voltage by sinking out some undesirable current due to the supply variation. The temperature compensation circuit clamps the output voltage regardless of the changes in the temperature ranges from 25 to 100 • C. Compared to previous research, the line regulation performance was better in a wide supply voltage range with a smaller area of 0.0067 mm 2 . Therefore, we can confirm that the proposed technique in this paper is useful for wide-supply-range applications. For future research, the line regulation performance can be improved by considering the circuit discussed in Appendix B, which is applicable only to high-voltage CMOS processes. In future work, the refined BGR circuit will be fully integrated onto a single chip along with a low-voltage drop circuit, a stimulator array, and its digital controller. Presently, a power management scheme including the proposed BGR circuit is under development in order to supply an average power of 100 mW to a 2000-pixel subretinal prosthetic ASIC, which will be implanted inside the eyeball for blind people. Taking the natural log of both sides results in the following expression, assuming V GS1 = V GS2 : Rearranging Equation (A3) for ∆V GS (V GS1 − V GS2 ) results in: (A4)

Appendix B
The improved BGR scheme shown in Figure A1 can be employed for an extreme environment that requires an unregulated supply above 5 V. The advance in a high-voltage bipolar-CMOS-DMOS (BCD) process allows one to integrate this BGR circuit on a chip. This integrated high-voltage BGR can also be applied for automotive applications operating at a voltage of 40 V in order to provide a reference voltage to data converters and power management blocks. The circuit in Figure A1 disregards its temperature dependency, and the performance of the output voltage regulation can be increased by disconnecting M P9 and shorting the gate terminal of M P6 to ground. The reason for connecting the gate terminal to the ground is to ensure M P6 is always in the triode region. The suggested techniques are for a system implemented using the high-voltage CMOS.
Energies 2020, 13, x FOR PEER REVIEW 13 of 14 Figure A1. Improvement of the bandgap voltage reference circuit.