High Threshold Voltage Normally o ﬀ Ultra-Thin-Barrier GaN MISHEMT with MOCVD-Regrown Ohmics and Si-Rich LPCVD-SiNx Gate Insulator

: A high threshold voltage (V TH ) normally o ﬀ GaN MISHEMTs with a uniform threshold voltage distribution (V TH = 4.25 ± 0.1 V at I DS = 1 µ A / mm) were demonstrated by the selective area ohmic regrowth technique together with an Si-rich LPCVD-SiN x gate insulator. In the conventional GaN MOSFET structure, the carriers were induced by the inversion channel at a high positive gate voltage. However, this design sacriﬁces the channel mobility and reliability because a huge number of carriers are beneath the gate insulator directly during operation. In this study, a 3-nm ultra-thin Al 0.25 Ga 0.75 N barrier was adopted to provide a two-dimensional electron gas (2DEG) channel underneath the gate terminal and selective area MOCVD-regrowth layer to improve the ohmic contact resistivity. An Si-rich LPCVD-SiN x gate insulator was employed to absorb trace oxygen contamination on the GaN surface and to improve the insulator / GaN interface quality. Based on the breakdown voltage, current density, and dynamic R ON measured results, the proposed LPCVD-MISHEMT provides a potential candidate solution for switching power electronics.


Introduction
In recent years, GaN-based normally off high-electron-mobility transistors (HEMTs) have been implemented for switching power electronics due to their wide energy bandgap, high electron mobility, and high current density [1][2][3]. In order to achieve the normally off operation of the GaN HEMT structure, many papers have reported a recessed gate (e.g., fully removed AlGaN barrier beneath the gate region) and metal-insulator-semiconductor (MIS) gate structure process [4][5][6][7]. By controlling the etching depth and profile aspect ratio, a stable positive threshold voltage (V TH ) can thus be obtained. In addition, the MIS gate structure also offers high thermal stability of V TH and a large forward gate-voltage operating range [8]. However, the deep level traps were generated on AlGaN or GaN surfaces by plasma bombardment damages, which caused the serious V TH variation and reliability issue [9]. To overcome the etching damages and V TH uniformity issues of the gate-recess-type normally off GaN HEMT, ultra-thin-barrier (UTB) AlGaN/GaN heterostructures with an MIS gate architecture were also proposed [10][11][12]. All of these previous studies adopted PEALD (plasma-enhanced atomic layer deposition) as the gate insulator to minimize the plasma-induced damage during gate insulator deposition. However, the PEALD-grown Al 2 O 3 is very sensitive to the subsequent process temperature. C. Mizue et al. observed that the as-deposited ALD-Al 2 O 3 thin film performed an amorphous-phase structure and the thin film also achieved a uniform thickness at this stage, owing to its deposition mechanism. During the ohmic contact formation process, the 850-900 • C annealing temperature leads to the formation of a microcrystallized Al 2 O 3 layer, resulting in an obvious increase in the leakage current of the Al 2 O 3 /GaN structure [13,14]. In this study, we proposed an Si-rich SiN gate insulator grown by LPCVD (low-pressure chemical vapor deposition system) to absorb the oxygen atom on the native AlGaN barrier layer surface and thus narrow the oxygen contamination region between SiN x /AlGaN interfaces. To further improve the ohmic contact resistivity, the MOCVE-regrown AlGaN drain/source regions were also adopted to demonstrate a low on-resistance (R ON ) ultra-thin barrier (UTB) GaN MISHEMT with a large positive V TH performance.

Device Fabrication
The devices were fabricated using an AlGaN/GaN heterostructure, grown by metal-organicchemical vapor deposition (MOCVD) on a conductive 6-inch Si (111) p-type substrate. As shown in Figure 1, a 4-µm-thick AlN transition layer and C-doped buffer layer were first grown on an Si substrate for high breakdown voltage consideration. Then, an undoped 300-nm GaN channel layer was deposited on a 50-nm-thick low Al mole fraction (A% = 5%), AlGaN back barrier layer, and a 3-nm-thick undoped Al 0.25 Ga 0.75 N ultra-thin barrier layer were sandwiched into a 1-nm GaN cap layer and GaN channel. The GaN cap was used to suppress the oxidation of the Al 0.25 Ga 0.75 N thin barrier and the cap layer at the regrowth region was removed. As to the device fabrication, the device started with the AlGaN regrowth region formation. Prior to the regrowth process, a 100-nm-thick dense SiO 2 layer was deposited on the GaN wafer as a regrowth mask by PECVD and the regrowth region was patterned using diluted HF wet etching solution. Then, the 1-nm GaN cap layer was removed by low-damage SF6 + BCl 3 mixtures in a dry etching process with a very low DC power condition and the sample was loaded into MOCVD without a queue time. Different from the published regrowth method with ohmic recess [15,16], the additional 20 nm of Al 0.25 Ga 0.75 N was selectively grown on the exposed 3-nm Al 0.25 Ga 0.75 N barrier layer surface. The Al composition of the regrown Al 0.25 Ga 0.75 N layer was also 25% to achieve a high-quality regrowth interface and good contact resistance with the initial barrier layer. This structure exhibited a sheet charge density of 1.05 × 10 13 cm −2 and electron mobility of 1570 cm 2 /V·s at 300 K together with an epitaxial sheet resistance of 420 Ω/ measured by Hall measurement. The first step in determining carrier mobility is to measure the Hall voltage by forcing both a magnetic field perpendicular to the sample and a current through the sample. The resistivity can be determined using either a four-point probe on GaN test samples. The PECVD SiO 2 in the gate region was then selectively removed using diluted HF wet etching. Afterward, the active region was protected by a photoresist and the mesa isolation region was removed in a reactive ion etching (RIE) chamber using BCl 3 + Cl 2 mixed-gas plasma. As to the gate dielectric layer, a 32-nm-thick layer of Si-rich LPCVD-grown SiN x measured by transmission electron microscopy (TEM) was deposited on the 1-nm GaN cap layer. The SiH 2 Cl 2 (dichlorosilane) flow rate was 150 sccm together with the mixture gas flow ratio (SiH 2 Cl 2 : NH 3 ) of 5:1 to reach an Si-rich content in SiN x at 800 • C, 180 m torr environment, and the deposition rate was around 2.2 nm/min. For comparison, the device with a 30-nm PECVD-grown SiN x gate dielectric was also fabricated. The ohmic contacts for the drain and source contacts were deposited by the electron beam evaporation of a multi-layer Ti/Al/Ni/Au (30 nm/125 nm/50 nm/200 nm) sequence, followed by rapid thermal annealing at 550 • C for 20 min in a nitrogen-rich ambient. Finally, the electron-beam evaporated Ni/Au was deposited as gate metal. Compared to the conventional gate recessed-type E-mode HEMT process, the barrier layer in this study eliminated the plasma bombardment by dry etching during the device fabrication process. Figure 1 shows the cross-sectional structure and scanning electron microscope (SEM) images of the fabricated UTB GaN MISHEMT with the device dimension L GS /L G /L GD /L FP of 2/1.5/10/4 µm, respectively. According to the atomic force microscope (AFM) images shown in Figure 2, the root mean square roughness of the GaN/Al 0.25 Ga 0.75 N/GaN heterostructure beneath the gate metal area is 0.37 nm and this value is 0.43 nm of the regrown Al 0.25 Ga 0.75 N ohmic contact area. The ohmic contact resistance measured by the transmission line method (TLM) was improved from 2.2×10 −5 Ω-cm 2 to 1.6 ×10 −6 Ω-cm 2 by adopting the AlGaN-regrown method owing to its totally 23-nm AlGaN barrier-induced high 2-DEG density.
Energies 2020, 13, x FOR PEER REVIEW 3 of 9 resistance measured by the transmission line method (TLM) was improved from 2.2×10 −5 Ω-cm 2 to 1.6 ×10 −6 Ω-cm 2 by adopting the AlGaN-regrown method owing to its totally 23-nm AlGaN barrierinduced high 2-DEG density.   Energies 2020, 13, x FOR PEER REVIEW 3 of 9 resistance measured by the transmission line method (TLM) was improved from 2.2×10 −5 Ω-cm 2 to 1.6 ×10 −6 Ω-cm 2 by adopting the AlGaN-regrown method owing to its totally 23-nm AlGaN barrierinduced high 2-DEG density.   Figure 3 presents the energy dispersive spectrometer (EDS) vertical line scanning analysis for the PECVD-and LPCVD-SiN x passivated UTB MISHEMT. Obviously, a narrow oxygen-contaminated layer was found on the AlGaN surface, which was primarily due to the native AlGaN oxidation compounds with environment moisture. However, with Si-rich LPCVD passivation at high temperature, the oxygen atoms were collected into the SiN layer and the oxygen-contaminated layer for LPCVD-MISHEMT was eliminated [17]. Therefore, Si-rich LPCVD-grown SiN x film passivates the dangling bonds on the Ga(Al)-terminated AlGaN surface, and thus lowers the interface traps in LPCVD-grown SiN x passivated UTB MISHEMTs.

Results and Discussion
Energies 2020, 13, x FOR PEER REVIEW 4 of 9 Figure 3 presents the energy dispersive spectrometer (EDS) vertical line scanning analysis for the PECVD-and LPCVD-SiNx passivated UTB MISHEMT. Obviously, a narrow oxygencontaminated layer was found on the AlGaN surface, which was primarily due to the native AlGaN oxidation compounds with environment moisture. However, with Si-rich LPCVD passivation at high temperature, the oxygen atoms were collected into the SiN layer and the oxygen-contaminated layer for LPCVD-MISHEMT was eliminated [17]. Therefore, Si-rich LPCVD-grown SiNx film passivates the dangling bonds on the Ga(Al)-terminated AlGaN surface, and thus lowers the interface traps in LPCVD-grown SiNx passivated UTB MISHEMTs.  Figure 4a displays the three-terminal off-state breakdown voltages (VBR) of devices with a wide gate-to-drain spacing (10 μm), which was evaluated by the Agilent B1505A measurement system and the Si substrate was grounded bias during the measurement. In this study, VBR is defined as the voltage when the drain leakage current between the source and the drain contacts reaches 1 mA/mm at a VGS of 0 V. The drain (IDS) leakage current of PECVD-MISHEMT increases rapidly with the increase of VDS and its VBR is 680 V. Referring to the gate (IGS) leakage current in Figure 4b, obviously, the IDS leakage current was one order of magnitude high than the IGS leakage current. Thus, the threeterminal leakage current not only contributed by the gate terminal when VDS > 50 V and the surface hopping leakage current also appeared in the breakdown mechanism of PECVD-MISHEMT [7]. The gate leakage current of LPCVD-MISHEMT is negligible and the drain-to-source leakage current dominated the breakdown mechanism in these devices, significantly improving the VBR values to 750 V. Based on the leakage current shown in Figure 4, the Si-rich high-quality LPCVD gate insulator suppressed the surface native oxidation layer and prevented electrons' surface hopping-induced leakage current at a high drain voltage [17].  Figure 4a displays the three-terminal off-state breakdown voltages (V BR ) of devices with a wide gate-to-drain spacing (10 µm), which was evaluated by the Agilent B1505A measurement system and the Si substrate was grounded bias during the measurement. In this study, V BR is defined as the voltage when the drain leakage current between the source and the drain contacts reaches 1 mA/mm at a V GS of 0 V. The drain (I DS ) leakage current of PECVD-MISHEMT increases rapidly with the increase of V DS and its V BR is 680 V. Referring to the gate (I GS ) leakage current in Figure 4b, obviously, the I DS leakage current was one order of magnitude high than the I GS leakage current. Thus, the three-terminal leakage current not only contributed by the gate terminal when V DS > 50 V and the surface hopping leakage current also appeared in the breakdown mechanism of PECVD-MISHEMT [7]. The gate leakage current of LPCVD-MISHEMT is negligible and the drain-to-source leakage current dominated the breakdown mechanism in these devices, significantly improving the V BR values to 750 V. Based on the leakage current shown in Figure 4, the Si-rich high-quality LPCVD gate insulator suppressed the surface native oxidation layer and prevented electrons' surface hopping-induced leakage current at a high drain voltage [17].   .71 mA/mm, respectively. The I Dmax value of the LPCVD-MISHEMT was 30.9% higher than that of the PECVD-MISHEMT because the capability of the gate modulation-induced current was not limited by the gate leakage current, which appeared in PECVD-MISHEMT. Thus, the static R on of the LPCVD-MISHEMT was improved to 19.85 Ω·mm, which corresponds to a specific on-resistance (R on ·A) of 1.98 mΩ·cm 2 at a V GS value of 16 V. These values of the PECVD-MISHEMT were 26.78 Ω·mm and 2.67 mΩ·cm 2 , respectively. For the LPCVD-MISHEMT, the suppression in the off-state I DS leakage current improved the on/off drain current ratio by approximately one order of magnitude and the subthreshold swing slope (S.S.) was improved from 155 to 150 mV/dec compared with that of the LPCVD-MISHEMT. Owing to the good interface between SiNx and the ultra-thin AlGaN barrier of the LPCVD-MISHEMT, contributing to improve the V TH uniformity and controllability. A standard deviation of 0.1 V was obtained by measuring 50 samples across the 6-inch wafer, as shown in the inset of Figure 4b.
The quasi-static C-V characterization was adopted to capture the carrier filling process of the deep interface states at the MIS gate structure interface of both devices, as shown in Figure 6, which was performed on the MIS gate structure of both devices. The second plateau in the C-V characteristics of the MIS diodes depicts the response of the insulator/thin AlGaN interface states. The interface trap density (D it ) values with τe between 10 −6 and 10 −4 s (0.34 < E C − E T < 0.42 eV) from 5.3 × 10 10 cm −2 to 1.2 × 10 11 cm −2 eV −1 for LPCVD-MISHEMT were lower than 6.8 × 10 10 cm −2 to 2.5 × 10 11 cm −2 eV −1 for PECVD-MISHEMT. The quasi-static C-V characterization was adopted to capture the carrier filling process of the deep interface states at the MIS gate structure interface of both devices, as shown in figure 6, which was performed on the MIS gate structure of both devices. The second plateau in the C-V characteristics of the MIS diodes depicts the response of the insulator/thin AlGaN interface states. The interface trap density (Dit) values with τe between 10 −6 and 10 −4 s (0.34 < EC − ET < 0.42 eV) from 5.3 × 10 10 cm −2 to 1.2 × 10 11 cm −2 eV −1 for LPCVD-MISHEMT were lower than 6.8 × 10 10 cm −2 to 2.5 × 10 11 cm −2 eV −1 for PECVD-MISHEMT. To further analyze the trapping/detrapping effect, the dynamic Ron ratio of the PECVD-and LPCVD-MISHEMT was measured using a pulse width of 2 μs and period of 200 μs. In this work, there were five bias conditions, which are pulse voltage (VGS, VDS) and quiescent voltage (VGSQ, VDSQ). However, the drain lag is due to the carriers during switching being trapped near the surface, which is in the SiNx/thin AlGaN interface. Furthermore, the trapping phenomenon also leads to a carrier density reduction and then an increase of the resistance. As the result, the VDSQ for both devices was swept from 0 to 600 V with an increment of 100 V, respectively. Clearly, the LPCVD-MISHEMT To further analyze the trapping/detrapping effect, the dynamic R on ratio of the PECVD-and LPCVD-MISHEMT was measured using a pulse width of 2 µs and period of 200 µs. In this work, there were five bias conditions, which are pulse voltage (V GS , V DS ) and quiescent voltage (V GSQ , V DSQ ). However, the drain lag is due to the carriers during switching being trapped near the surface, which is in the SiN x /thin AlGaN interface. Furthermore, the trapping phenomenon also leads to a carrier density reduction and then an increase of the resistance. As the result, the V DSQ for both devices was swept from 0 to 600 V with an increment of 100 V, respectively. Clearly, the LPCVD-MISHEMT exhibits a superior dynamic R on than the PECVD-MISHEMT because the dynamic R on ratio improved from 2.6 to 1.9 times at V DSQ = 600 V, as indicated in Figure 7. In addition, a higher V DSQ was applied because of a lower trap density in the MIS-gate interface. The oxygen vacancies in the AlGaN/GaN interface can lead to serious trapping behavior during high switching operation [18].

Conclusions
In this work, we developed and investigated the electrical properties of a normally off GaNbased switching device by using a high-temperature Si-rich LPCVD-SiNx gate insulator and selective area ohmic regrowth technique. Based on the EDX analysis, Si-rich LPCVD-SiNx mitigated the native oxygen contamination of the GaN surface, thus the interface Dit was improved. In addition, the selective area ohmic regrowth AlGaN layer improved the 2-DEG density at the access region, thus the device RON was reduced. The low Dit high temperature Si-rich LPCVD-SiNx gate insulator achieved a large positive threshold voltage together with a low leakage current and high ION/IOFF ratio. Moreover, the low dynamic RON also indicated that the proposed device provides great promise in achieving a high-performance normally off GaN power electronics device.

Conclusions
In this work, we developed and investigated the electrical properties of a normally off GaN-based switching device by using a high-temperature Si-rich LPCVD-SiN x gate insulator and selective area ohmic regrowth technique. Based on the EDX analysis, Si-rich LPCVD-SiN x mitigated the native oxygen contamination of the GaN surface, thus the interface D it was improved. In addition, the selective area ohmic regrowth AlGaN layer improved the 2-DEG density at the access region, thus the device R ON was reduced. The low D it high temperature Si-rich LPCVD-SiN x gate insulator achieved a large positive threshold voltage together with a low leakage current and high I ON /I OFF ratio. Moreover, the low dynamic R ON also indicated that the proposed device provides great promise in achieving a high-performance normally off GaN power electronics device.