Fault-Tolerant Control Strategies and Capability without Redundant Sub-Modules in Modular Multilevel Converters

: Sub-module (SM) faults in modular multilevel converters (MMCs) without redundancies result in unbalanced converter output voltages and improper control of modulation due to an unequal number of SMs inserted between the di ﬀ erent phase-legs. The derived mathematics model of the MMC demonstrates the impact of the SM fault in the circulating currents and capacitor voltages. For achieving the SM fault-tolerance, detailed analysis of the MMC’s electrical quantities under SM fault-tolerant algorithms is provided together with two modulation reconﬁguration techniques for maintaining voltage balance. Fault-tolerant abilities of the two modulation algorithms are also discussed and deﬁned. Simulation results from a 21-level converter and experimental work in a three-phase ﬁve-level converter demonstrate the feasibility and performance of the proposed fault-tolerant control strategies.

In order to be applied better in HVDC transmission systems, MMCs need to handle a great diversity of fault conditions including i) AC-side faults [10], ii) unbalanced grid conditions [11,12], iii) DC-link short circuit faults [13,14] and iv) sub-module (SM) faults [15][16][17]. A SM fault represents a typical fault condition [17] and it is better to keep the operation of the MMC until the next scheduled maintenance. Therefore, the key to dealing with the SM failure is to quickly locate and bypass the failed sub-modules while reconfiguring the operation and control of the converter to account for the faulty SMs and avoid further issues [14].
The power semiconductor devices have two fault types: open-circuit fault and short-circuit fault [15]. Although faulty SMs need to be bypassed in both cases, the speed of fault detection differs for the two types of faults. Thus, uninterrupted operation of the converter and the overall system should be ensured for the duration of the fault. Open-circuit faults of an insulated gate bipolar translator (IGBT) for traditional voltage source converters (VSCs) have been extensively studied in the literature [18][19][20]. Fault detection in the MMC using a sliding mode observer was first discussed in [21]. For detecting SM failure, a Kalman filter was utilized in [22]. Reference [17] proposed a strategy for detecting the SM fault by means of state observers. Based on calculated capacitance, a clustering algorithm was applied in [23].
In order to maintain the normal operation of an MMC under SM failure conditions, the methods of redundant SMs are proposed by providing fault-tolerance [24][25][26][27]. The redundant SMs have two modes: 1) Cold-reserve and 2) hot-reserve. Compared to cold-reserve, the hot-reserve methods can shorten the charging time of redundant SMs and recover the normal operation rapidly. However, the two modes increase the cost of the converter and add to the operational complexity. Based on the system without redundant SMs or when the redundant SMs are used up, these methods [24][25][26][27] are invalid. Thus, the SM fault-tolerant methods without redundant SMs are widely discussed in recent papers.
A fault-tolerant control method based on arm energy calculation is proposed in [28]. Its modulation strategy is not regulated under this method, and the SM capacitor voltages of remaining SMs in the faulty arm will increase. For solving the problem of SM capacitor overvoltage produced in [28], a neutral-shift method for maintaining the balanced line voltages of the MMC was discussed in [29]. However, the modulation index and phase angle of modulation reference should be recalculated based on a table look-up. For a simplified calculation, modulation reconfiguration techniques based on zero-sequence voltage injection are proposed [30][31][32]. They provide fault tolerant operation without the requirement for additional hardware and are easily implemented. The outputs are balanced and the SM voltage in the faulty arm are controlled to a rated value by a modified modulation algorithm [30,31], the switching operations are different in unsymmetrical arms. However, the SMs failure only produced in one arm is considered in [29][30][31]. The universality of these methods should be further discussed. If the modulation technique [30,31] cannot be applied effectively, the unsymmetrical arm currents will cause unequal conduction and switching losses between the arms. Thus, the fault-tolerant ability under modulation reconfiguration techniques [30,31] should be calculated and discussed.
Aiming at these problems, the more effective modulation reconfiguration techniques regardless of fault detection and localization techniques that may be used will be proposed and discussed in this paper. An analysis of electrical quantities under a module fault condition is provided together with two reconfigurations of the modulation technique for maintaining voltage balance. Fault-tolerant ability of the algorithms is also discussed and the fault-tolerant ability is defined.
The paper is organized as follows. Sections 2 and 3 introduces the MMC's operating principles in order to derive an analytical mathematical model that is used for calculating the SM capacitor voltage ripples and the circulating currents. Section 4 adopts two modulation reconfiguration algorithms for fault-tolerant operation without a redundant SM and analyzes the capacitor voltage fluctuations and circulating current components under SM failures. In Sections 5 and 6, validity of the proposed methods is demonstrated by experimental and simulation results. Section 7 summarizes the conclusions of this paper.

Basic Structure and Principle of MMC
In this paper, this basic structure of the MMC is shown in Figure 1. The structure of SM is half-bridge. There are N SMs in one arm.  Table 1 shows the switching states of the HB-SM (half bridge sub-module) under different operation conditions. When faults occur, the bypass switch will keep the faulty SM in state 2. The upper and lower arms average switching functions of phase j (j = a, b and c), Sju and Sjl can be expressed as [33] ju jl 1 (1 cos ) (1) where ω represents the fundamental frequency, m represents the modulation index ( [0, ,1] m ∈ … ). Off/on 0 bypass uncharged Figure 2 shows the equivalent circuit of an MMC, which ju and jl represent the upper and lower arms of phase j. ij represents the AC-side current; ijdiff is the circulating current; udc and idc are the DC voltage and current, respectively. uj is the output voltage of phase j. uju and ujl are the upper and lower arms output voltages, respectively. They can be expressed as Equation (2). Figure 1. Basic structure of a modular multilevel converters (MMC) and sub-module (SM) model. Table 1 shows the switching states of the HB-SM (half bridge sub-module) under different operation conditions. When faults occur, the bypass switch will keep the faulty SM in state 2. The upper and lower arms average switching functions of phase j (j = a, b and c), S ju and S jl can be expressed as [33] s where ω represents the fundamental frequency, m represents the modulation index (m ∈ [0, . . . , 1]). Off/on 0 bypass uncharged Figure 2 shows the equivalent circuit of an MMC, which ju and jl represent the upper and lower arms of phase j. i j represents the AC-side current; i jdiff is the circulating current; u dc and i dc are the DC voltage and current, respectively. u j is the output voltage of phase j. u ju and u jl are the upper and lower arms output voltages, respectively. They can be expressed as Equation (2). Off/on 0 bypass uncharged Figure 2 shows the equivalent circuit of an MMC, which ju and jl represent the upper and lower arms of phase j. ij represents the AC-side current; ijdiff is the circulating current; udc and idc are the DC voltage and current, respectively. uj is the output voltage of phase j. uju and ujl are the upper and lower arms output voltages, respectively. They can be expressed as Equation (2). Figure 2. The three-phase equivalent circuit of MMC.
The i ju and i jl are given by Equation (3), respectively Circulating currents can be suppressed under balanced [3] and unbalanced AC conditions [11]. Circulating current controller is also designed for the submodule fault condition [22]. Thus, the arm currents can be only the fundamental component and DC component by the appropriate control method.

System Analysis Under Faulty Conditions
The following section will derive the analytical model for the MMC under faulty conditions and derive the closed-form equations for the capacitor voltage ripple and circulating current.
Without any loss in the general analysis, we assume that there are x faulty SMs in the upper arm of phase j, and that they have been bypassed. The main component of circulating current is a double-line frequency component [34] during steady state. From Equation (3), the arm currents i ju and i jl before the fault can be rewritten as where i jdiff_dc is the DC component in the circulating current, and I 2 represents the amplitude of second order harmonic. ϕ 2 and ϕ are the angles of second harmonic component in circulating current and the AC output current, respectively. Based Equations (1) and (4), the average current through the SM capacitors of the upper and lower arms i juc and i jlc can be given as .
The h-th frequency component of the arm current (h = 0, 1, 2, . . . , n) will cause a fluctuation of the same frequency in the SM capacitor voltages. The upper and lower arms' capacitor fluctuations ∆u juc and ∆u jlc are where C represents the capacitor value. Due to the switching actions within the arms, the fluctuations of SM capacitor voltages and the output voltage u ju(l) are coupled. Then, the output voltage fluctuations of SMs ∆u smju and ∆u smjl can be expressed as follows where B 0 is the DC component and B h is the h-th order harmonics on the voltages ripple.
Due to the x bypass SMs, the voltage fluctuation of the phase j ∆u j can be given as: The voltage fluctuation ∆u j exists within the whole arm, the circulating current i jdiff will include the same harmonic components can be expressed as follows where ∆u j (ω h ) represents the h-line frequency component in the voltage fluctuation, ω h represents the h-line frequency. Under conventional operation conditions, x is equal to zero, in which case the coefficients of the second term in Equation (8) are equal to zero. Thus, there are no fundamental or triple-line frequency components in the circulating current i jdiff . However, the odd frequency components (first term in Equation (8)) will exist in ∆u j and, hence, in i jdiff when a SM fault occurs. Meanwhile, when the harmonic components in the second term among three phases are asymmetrical, the harmonic components will also flow in the DC side. The unbalanced arm voltages will cause imbalances in output voltages under conventional modulation methods. Thus, fault-tolerant modulation strategy should be utilized for fault-tolerant operation in MMCs.

Proposed Fault-Tolerant Strategies
In order to handle SM faults, two modulation techniques based on zero-sequence voltage injection are discussed in this section. The principle and operation conditions are also discussed under the faulted SM operation.

Generalized Discontinuous Pulse Width Modulation (GDPWM)
Zero-sequence voltage injection techniques can reduce the switching losses and deal with the unbalanced cases for VSCs. In this paper, the injected zero-sequence component V z based on the generalized discontinuous pulse width modulation (GDPWM) [35] is written as: where k (0 ≤ k ≤ 1) is the coefficient of the zero-sequence component. V jmax and V jmin are the maximum and minimum of the three-phase modulation waves V j , respectively. The reconfigured modulation waves V j * by utilizing Equation (10) are shown in Figure 3. ω ω (9) where Δuj (ωh) represents the h-line frequency component in the voltage fluctuation, ωh represents the h-line frequency.
Under conventional operation conditions, x is equal to zero, in which case the coefficients of the second term in Equation (8) are equal to zero. Thus, there are no fundamental or triple-line frequency components in the circulating current ijdiff. However, the odd frequency components (first term in Equation (8)) will exist in Δuj and, hence, in ijdiff when a SM fault occurs. Meanwhile, when the harmonic components in the second term among three phases are asymmetrical, the harmonic components will also flow in the DC side. The unbalanced arm voltages will cause imbalances in output voltages under conventional modulation methods. Thus, fault-tolerant modulation strategy should be utilized for fault-tolerant operation in MMCs.

Proposed Fault-Tolerant Strategies
In order to handle SM faults, two modulation techniques based on zero-sequence voltage injection are discussed in this section. The principle and operation conditions are also discussed under the faulted SM operation.

Generalized Discontinuous Pulse Width Modulation (GDPWM)
Zero-sequence voltage injection techniques can reduce the switching losses and deal with the unbalanced cases for VSCs. In this paper, the injected zero-sequence component Vz based on the generalized discontinuous pulse width modulation (GDPWM) [36] is written as: where k (0 ≤ k ≤ 1) is the coefficient of the zero-sequence component. Vjmax and Vjmin are the maximum and minimum of the three-phase modulation waves Vj, respectively. The reconfigured modulation waves Vj * by utilizing Equation (10) are shown in Figure 3. Based on a 21-level simulation system which parameters are shown in Table 2, the modulation waves by GDPWM algorithm under different k is shown in Figure 4 during the modulation index m = 1.  Based on a 21-level simulation system which parameters are shown in Table 2, the modulation waves by GDPWM algorithm under different k is shown in Figure 4 during the modulation index m = 1. From the Figure 4 one can see that the modulation waveforms are obviously affected by k. They are consistent with space vector pulse width modulation (SVPWM) when k is 0.5. When k is close to 0 or 1, the appearance of neutral-shift is outstanding. Based on this point, different modulation waveforms can be achieved by changing k when modulation index m is certain. By detecting the position and number of the faulty SMs, k is chosen to be close to 0 or 1. With the neutral-shift, the amplitude of the modulation waveforms can be adjusted to a certain value. Therefore, we can only activate healthy SMs to finish the modulation calculation based on this characteristic. From the Figure 4 one can see that the modulation waveforms are obviously affected by k. They are consistent with space vector pulse width modulation (SVPWM) when k is 0.5. When k is close to 0 or 1, the appearance of neutral-shift is outstanding. Based on this point, different modulation waveforms can be achieved by changing k when modulation index m is certain. By detecting the position and number of the faulty SMs, k is chosen to be close to 0 or 1. With the neutral-shift, the amplitude of the modulation waveforms can be adjusted to a certain value. Therefore, we can only activate healthy SMs to finish the modulation calculation based on this characteristic.

Amplitude-Limited Modulation (ALM)
To maintain the line voltages balance, another modulation algorithm is proposed and discussed in this section. The reconfigured modulation waves Vj * can be written as (11) where Vj * represent the reconfigured modulation waves; Vj are the original modulation waves; and Vzu, Vzl represent the zero-sequence voltages injected to upper and lower arm, respectively. Assuming that xu is the maximum of faulty SMs among three upper arms, xl is the maximum of faulty SMs among three lower arms. k1 (k1 > 0) is the limiting factor of upper arm and k2 (k2 < 0) is the limiting factor of lower arm. They are decided by faulty SM numbers of upper and lower arms, and expressed as: When faulty SMs are detected and bypassed, the Vzu, Vzl can be expressed based (13 and 14):

Amplitude-Limited Modulation (ALM)
To maintain the line voltages balance, another modulation algorithm is proposed and discussed in this section. The reconfigured modulation waves V j * can be written as (11) where V j * represent the reconfigured modulation waves; V j are the original modulation waves; and V zu , V zl represent the zero-sequence voltages injected to upper and lower arm, respectively.
Assuming that x u is the maximum of faulty SMs among three upper arms, x l is the maximum of faulty SMs among three lower arms. k 1 (k 1 > 0) is the limiting factor of upper arm and k 2 (k 2 < 0) is the limiting factor of lower arm. They are decided by faulty SM numbers of upper and lower arms, and expressed as: When faulty SMs are detected and bypassed, the V zu , V zl can be expressed based (13 and 14): The rule of reconfiguration depends on the faulty SM number and the operating point of an MMC as follows:

Case 1: Faulty SMs only appear in upper (lower) arms.
We assume that x u 0, x l = 0. If the faulty SM number is x u ≤ N(1−m)/2, then the faulty SMs are not required in the regular operation of the MMC. Thus, the modulation functions of the arms do not need to be reconfigured (k 1 = 0, k 2 = 0). If, however, the number x u > N(1−m)/2, the failed SMs are being bypassed. In order to avoid the number of remaining SMs not being adequate to generate the arm voltage, the amplitude of the faulty arm modulation cannot beyond a fixed value 2x u /N. For maintaining line voltages, the same for pre-and post-fault, the non-fault phase modulations should be reconfigured during the fixed value period in fault phase. Thus, the three phase modulation waves V j * are given in Table 3 when only x u failure SMs appears in the upper arm of phase a. Figure 5 shows the modulation functions under m = 0.9, when 25% to 10% faulty SMs in the upper arm of phase a are considered. From Figure 5 we can observe that the larger faulty SMs number, the wider the reconfiguration range is. The peak values of the remaining two phases are decided by x. Figure 6 describes the different faulty SMs numbers in upper arms of phase a and b. The results show that the effects of amplitude-limited by zero-sequence voltage injection are not influenced by the position and number of faulty SMs. Table 3. Amplitude-limited modulation algorithm.

Range of ωt
The rule of reconfiguration depends on the faulty SM number and the operating point of an MMC as follows:

Case 1: Faulty SMs only appear in upper (lower) arms.
We assume that xu ≠ 0, xl = 0. If the faulty SM number is xu ≤ N(1−m)/2, then the faulty SMs are not required in the regular operation of the MMC. Thus, the modulation functions of the arms do not need to be reconfigured (k1 = 0, k2 = 0). If, however, the number xu ＞ N(1−m)/2, the failed SMs are being bypassed. In order to avoid the number of remaining SMs not being adequate to generate the arm voltage, the amplitude of the faulty arm modulation cannot beyond a fixed value 2xu/N. For maintaining line voltages, the same for pre-and post-fault, the non-fault phase modulations should be reconfigured during the fixed value period in fault phase. Thus, the three phase modulation waves Vj * are given in Table 3 when only xu failure SMs appears in the upper arm of phase a. Figure 5 shows the modulation functions under m = 0.9, when 25% to 10% faulty SMs in the upper arm of phase a are considered. From Figure 5 we can observe that the larger faulty SMs number, the wider the reconfiguration range is. The peak values of the remaining two phases are decided by x. Figure 6 describes the different faulty SMs numbers in upper arms of phase a and b. The results show that the effects of amplitude-limited by zero-sequence voltage injection are not influenced by the position and number of faulty SMs. Table 3. Amplitude-limited modulation algorithm.

Range of ωt
The rule of reconfiguration depends on the faulty SM number and the operating point of an MMC as follows: Case 1: Faulty SMs only appear in upper (lower) arms.
We assume that xu ≠ 0, xl = 0. If the faulty SM number is xu ≤ N(1−m)/2, then the faulty SMs are not required in the regular operation of the MMC. Thus, the modulation functions of the arms do not need to be reconfigured (k1 = 0, k2 = 0). If, however, the number xu ＞ N(1−m)/2, the failed SMs are being bypassed. In order to avoid the number of remaining SMs not being adequate to generate the arm voltage, the amplitude of the faulty arm modulation cannot beyond a fixed value 2xu/N. For maintaining line voltages, the same for pre-and post-fault, the non-fault phase modulations should be reconfigured during the fixed value period in fault phase. Thus, the three phase modulation waves Vj * are given in Table 3 when only xu failure SMs appears in the upper arm of phase a. Figure 5 shows the modulation functions under m = 0.9, when 25% to 10% faulty SMs in the upper arm of phase a are considered. From Figure 5 we can observe that the larger faulty SMs number, the wider the reconfiguration range is. The peak values of the remaining two phases are decided by x. Figure 6 describes the different faulty SMs numbers in upper arms of phase a and b. The results show that the effects of amplitude-limited by zero-sequence voltage injection are not influenced by the position and number of faulty SMs. Table 3. Amplitude-limited modulation algorithm.      From Figures 5-7 one can see that over-modulation exists in the modulation waveforms under some conditions. Thus, the fault-tolerant strategy ability based on ALM should be discussed.

Operation conditions of GDPWM and ALM
Compared to GDPWM, ALM achieves greater customization. Both of them have limitations in fault-tolerance under some conditions. a) Fault-Tolerant Capability of GDPWM Due to the balanced state of the three-phase modulation references, k = 0.5 can be chosen preferentially under normal operation conditions. The system can ensure normal operation when (1−√3m/2)N failure SMs are bypassed (peak modulation wave is √3m/2 when k = 0.5) under a conventional modulation technique. When extreme conditions appear, fault-tolerant strategies proposed in this paper can be applied for SM fault ride-through with no redundancy SMs. Without redundancy SMs, the system can keep running normally with the GDPWM algorithm under some SMs fault conditions. The maximum of faulty SMs in one arm is (2−√3m)N when GDPWM is applied.
The zero-sequence voltage vector coefficient k of GDPWM can be written as Equation (15). The k should approximate to 0 when xu is larger than xl. However, the k needs to approximate to 1 when xl is larger than xu. The MMC should stop operating when the faulty SM number reaches the threshold l u l u u l b) Fault-Tolerant Capability of ALM  From Figures 5-7 one can see that over-modulation exists in the modulation waveforms under some conditions. Thus, the fault-tolerant strategy ability based on ALM should be discussed.

Operation conditions of GDPWM and ALM
Compared to GDPWM, ALM achieves greater customization. Both of them have limitations in fault-tolerance under some conditions. a) Fault-Tolerant Capability of GDPWM Due to the balanced state of the three-phase modulation references, k = 0.5 can be chosen preferentially under normal operation conditions. The system can ensure normal operation when (1−√3m/2)N failure SMs are bypassed (peak modulation wave is √3m/2 when k = 0.5) under a conventional modulation technique. When extreme conditions appear, fault-tolerant strategies proposed in this paper can be applied for SM fault ride-through with no redundancy SMs. Without redundancy SMs, the system can keep running normally with the GDPWM algorithm under some SMs fault conditions. The maximum of faulty SMs in one arm is (2−√3m)N when GDPWM is applied.
The zero-sequence voltage vector coefficient k of GDPWM can be written as Equation (15). The k should approximate to 0 when xu is larger than xl. However, the k needs to approximate to 1 when xl is larger than xu. The MMC should stop operating when the faulty SM number reaches the threshold l u l u u l b) Fault-Tolerant Capability of ALM The zero-sequence voltage vector coefficient k of GDPWM can be written as Equation (15). The k should approximate to 0 when x u is larger than x l . However, the k needs to approximate to 1 when x l is larger than x u . The MMC should stop operating when the faulty SM number reaches the threshold The over-modulation will affect the outputs balanced, and the effectiveness is affected by the modulation index m and number of faulty SMs directly. The limiting condition is expressed as Equation (16). Figures 5-7 show that not every situation can be accommodated by the modulation algorithm. The range of modulation reconfiguration should be defined so that there are no overlap regions as in Equation (17).
This fault-tolerant scheme only needs to bypass the faulty sub-modules, and the remaining SMs rated voltages stay stable. The line voltages and currents will be balanced by the proposed approach. However, due to the difference between the upper arm and lower arm SM numbers of the faulty phase, the switching models in arms are asymmetric. The Fourier analysis results of the modulation waves of Figure 5a are given in Figure 9. The fundamental frequency of phase a makes a considerable difference from phase b and c, although the other components are nearly the same. Therefore, the three modulation waves are also asymmetric. Thus, the charging and discharging processes of SMs in different phases are different. Based on the analysis of Section 3 we can estimate that the coupling effects between the voltage fluctuation and differential current will generate the odd-line frequency components in the circulating current when this modulation scheme used. The over-modulation will affect the outputs balanced, and the effectiveness is affected by the modulation index m and number of faulty SMs directly. The limiting condition is expressed as Equation (16). Figures 5-7 show that not every situation can be accommodated by the modulation algorithm. The range of modulation reconfiguration should be defined so that there are no overlap regions as in Equation (17).
This fault-tolerant scheme only needs to bypass the faulty sub-modules, and the remaining SMs rated voltages stay stable. The line voltages and currents will be balanced by the proposed approach. However, due to the difference between the upper arm and lower arm SM numbers of the faulty phase, the switching models in arms are asymmetric. The Fourier analysis results of the modulation waves of Figure 5a are given in Figure 9. The fundamental frequency of phase a makes a considerable difference from phase b and c, although the other components are nearly the same. Therefore, the three modulation waves are also asymmetric. Thus, the charging and discharging processes of SMs in different phases are different. Based on the analysis of Section 3 we can estimate that the coupling effects between the voltage fluctuation and differential current will generate the odd-line frequency components in the circulating current when this modulation scheme used.

Capacitor Voltage Fluctuations and Circulating Current Analysis under GDPWM and ALM
Based on the results of Figures 4 and 8 we can see that the DC component (z ≠ 0.5) and third harmonic exist in the GDPWM and various orders of harmonics appear in ALM.
The average switching function sju and sjl in phase j can be rewritten as: where m0 is the DC component in the modulation reference, and mh and φh represent the modulation index and angle of h-th order harmonic.
Assuming that second order harmonic of circulating current is suppressed before SM failure occurs, the arm currents can be rewritten as:

Capacitor Voltage Fluctuations and Circulating Current Analysis under GDPWM and ALM
Based on the results of Figures 4 and 8 we can see that the DC component (z 0.5) and third harmonic exist in the GDPWM and various orders of harmonics appear in ALM.
The average switching function s ju and s jl in phase j can be rewritten as: where m 0 is the DC component in the modulation reference, and m h and ϕ h represent the modulation index and angle of h-th order harmonic. Assuming that second order harmonic of circulating current is suppressed before SM failure occurs, the arm currents can be rewritten as: Energies Following the calculation of Section 3, the upper and lower arm voltages of phase j are derived as: From Equation (20) we can observe that the existence of m 0 will produce the term m 0× i diff_dc , which causes the unequal DC component in the upper and lower arms under GDPWM. Meanwhile, the m 0 also causes the non-complementation among the two arms in one phase. Thus, the progress of the charging and discharging of capacitor in the two arms are different. It will cause different capacitor voltage fluctuations in the two arms. Due to the h-th order harmonic in the modulation references, h-th, h − 1 and h + 1 order harmonics will appear in the arms under GDPWM and ALM, and capacitor voltage fluctuations are different between the arms in one phase.
Based on Equations (18) and (20), the outputs of upper and lower arm voltages u ju , u jl are given in Equations (A1) and (A2) in the Appendix A. From the equations we can see that h, h ± 1, h ± 2, 2h and 2h ± 1 appear in the arm output voltages in addition to the fundamental component, second and third order harmonics. Assuming that x faulty SMs occur in the upper arm of phase j, the sum of the upper and lower arm output voltage is expressed in Equation (A3). The main components of Equation (A3) can be given as: The harmonic components among the phase voltage are complex. Fundamental, second order, h and h + 1 order harmonics exist in the voltage. The fundamental component will provide the fundamental component in the circulating current, and it will cause energy imbalance between the arms. Fundamental, second-and third-order harmonics are the main components of the circulating currents. Thus, the circulating current controller should be designed aimed at these components under GDPWM and ALM.

Simulation Studies
This section provides two sets of results in order to demonstrate and evaluate the proposed methods and analysis results. A 21-level simulation system was used to verify the fault-tolerant strategies of the GDPWM and ALM.

a) GDPWM under Balanced Conditions
For verifying the effect of GDPWM in capacitor voltages and circulating current, simulation results with k changing from 0 to 1 are shown in Figure 10.

a) GDPWM under Balanced Conditions
For verifying the effect of GDPWM in capacitor voltages and circulating current, simulation results with k changing from 0 to 1 are shown in Figure 10. From the results we can see that the AC current ia, ib and ic (shown in Figure 10e) were balanced when k changed from 0 to 1. The performance of AC system control was not affected by the GDPWM under this condition. The upper and lower capacitors voltages (usma1-usma20) in Figure 10c and capacitors voltages (usma21-usma40) in Figure 10d were deviated from the rated value when k kept away from 0.5. Based on the characteristic of GDPWM, the activated SM in the lower arm was larger than that in upper arm when k was close to 0. Therefore, the fundamental component of the lower arm current was larger than that in the upper arm. Meanwhile, the lower arm SMs activated time was longer than that of the upper arm, and SMs capacitor voltages of the lower arm were higher. The consequence was opposite between k = 1 and k = 0. The fundamental and other harmonic components exist in the circulating current iadiff when k ≠ 0.5. When k was close to 0 or 1, the oscillation was larger in the circulating current.

b) Fault-Tolerance under GDPWM
Results of GDPWM are shown in Figure 11. At time 0.05 s, five faulty SMs appear in the upper arm of phase a (xu = 5). GDPWM was activated at 0.09 s. From the Figure 11b,c we can see that the SM faulty may have caused the over current in the arm. In Figure 11d, faulty SMs usma1-usma5 were bypassed. The healthy SMs capacitor voltages (usma6-usma20) increased to 580 V. The lower arm capacitor voltages (usma21-usma40) also increased. From these one can see that the performance of SM fault-tolerance was good when GDPWM was activated. The average capacitor voltages decreased From the results we can see that the AC current i a , i b and i c (shown in Figure 10e) were balanced when k changed from 0 to 1. The performance of AC system control was not affected by the GDPWM under this condition. The upper and lower capacitors voltages (u sma1 -u sma20 ) in Figure 10c and capacitors voltages (u sma21 -u sma40 ) in Figure 10d were deviated from the rated value when k kept away from 0.5. Based on the characteristic of GDPWM, the activated SM in the lower arm was larger than that in upper arm when k was close to 0. Therefore, the fundamental component of the lower arm current was larger than that in the upper arm. Meanwhile, the lower arm SMs activated time was longer than that of the upper arm, and SMs capacitor voltages of the lower arm were higher. The consequence was opposite between k = 1 and k = 0. The fundamental and other harmonic components exist in the circulating current i adiff when k 0.5. When k was close to 0 or 1, the oscillation was larger in the circulating current.

b) Fault-Tolerance under GDPWM
Results of GDPWM are shown in Figure 11. At time 0.05 s, five faulty SMs appear in the upper arm of phase a (x u = 5). GDPWM was activated at 0.09 s. From the Figure 11b,c we can see that the SM faulty may have caused the over current in the arm. In Figure 11d, faulty SMs u sma1 -u sma5 were bypassed. The healthy SMs capacitor voltages (u sma6 -u sma20 ) increased to 580 V. The lower arm capacitor voltages (u sma21 -u sma40 ) also increased. From these one can see that the performance of SM fault-tolerance was good when GDPWM was activated. The average capacitor voltages decreased and arm currents were balanced. The capacitor voltage fluctuations were consistent with theoretical analysis.

c) Fault-Tolerance under ALM
The simulation results with ALM are illustrated in Figure 12. Open-circuit SM failure occurred in the upper arm in phase a (ua1-ua4) at time 0.2 s. At time 0.4 s, the ALM method is activated. It was observed that iau, ial and iadiff were sinusoidal and the capacitor voltages were stable under healthy operating conditions. Assuming that a SM fault occurs at t = 0.2 s, three phase currents iau, ial and iadiff became higher than normal which led to overcurrent within the arms. As (usma1-usma4) were

c) Fault-Tolerance under ALM
The simulation results with ALM are illustrated in Figure 12

c) Fault-Tolerance under ALM
The simulation results with ALM are illustrated in Figure 12. Open-circuit SM failure occurred in the upper arm in phase a (ua1-ua4) at time 0.2 s. At time 0.4 s, the ALM method is activated. It was observed that iau, ial and iadiff were sinusoidal and the capacitor voltages were stable under healthy operating conditions. Assuming that a SM fault occurs at t = 0.2 s, three phase currents iau, ial and iadiff became higher than normal which led to overcurrent within the arms. As (usma1-usma4) were It was observed that i au , i al and i adiff were sinusoidal and the capacitor voltages were stable under healthy operating conditions. Assuming that a SM fault occurs at t = 0.2 s, three phase currents i au , i al and i adiff became higher than normal which led to overcurrent within the arms. As (u sma1 -u sma4 ) were faulty and bypassed, the remaining SMs voltages of the upper arm (u sma5 -u sma20 ) increased, and their ripples also increased. The voltage increments were less than 10% of the rated voltage, it was relatively safe for SM voltages. At time 0.4 s, the ALM method was used and the values of (u sma5 -u sma20 ) return to the reference value. From the FFT analysis of the circulating current, shown in Figure 12f, we observed that a decrease of 60% in the fundamental frequency component and a decrease of 85% in the third harmonic. These results meet the theoretical analysis of the previous section, which demonstrated that the ALM will not cause over current in the arms or overvoltage in SM capacitors.
From Equations (16) and (17), the maximum proportion of faulty SMs should be less than 30.72%N for an m = 0.8. When utilizing the simulation system by N = 20, the permitted greatest integer of faulty SMs is six. Figure 13 shows the results of the fault-tolerant ability when 30%N (x u = 6, k 1 = 0.4) and . When x 4 = 30%N, the line voltages were balanced, however, the voltages were unbalanced when x 4 = 40%N. Thus, the simulation results illustrate the validity of the theoretical calculation for Case 1.
For verifying the fault-tolerant capability of Case 3, Figure 14a provides the results of the fault-tolerant ability when 15%N faulty sub-modules in upper arm of phase a (x u = 3, k 1 = 0.7) and 15%N faulty sub-modules in lower arm of phase b (x l = 3, k 2 = −0.7). Figure 14b shows the results of x u = 4 and x l = 3. The line voltages were balanced in Figure 13a, however the voltages were unbalanced due to the distortion in the modulation wave of phase b in Figure 14b. The overlap regions affect the results of the ALM. Thus, these results illustrate that the validity of the theoretical calculation for Case 3. faulty and bypassed, the remaining SMs voltages of the upper arm (usma5-usma20) increased, and their ripples also increased. The voltage increments were less than 10% of the rated voltage, it was relatively safe for SM voltages. At time 0.4 s, the ALM method was used and the values of (usma5-usma20) return to the reference value. From the FFT analysis of the circulating current, shown in Figure  12f, we observed that a decrease of 60% in the fundamental frequency component and a decrease of 85% in the third harmonic. These results meet the theoretical analysis of the previous section, which demonstrated that the ALM will not cause over current in the arms or overvoltage in SM capacitors. From Equations (16) and (17), the maximum proportion of faulty SMs should be less than 30.72%N for an m = 0.8. When utilizing the simulation system by N = 20, the permitted greatest integer of faulty SMs is six. Figure 13 shows the results of the fault-tolerant ability when 30%N (xu = 6, k1 = 0.4) and x4 = 40%N (xu =8, k1 = 0.2). When x4 = 30%N, the line voltages were balanced, however, the voltages were unbalanced when x4 = 40%N. Thus, the simulation results illustrate the validity of the theoretical calculation for Case 1.   Figure 14b shows the results of xu = 4 and xl = 3. The line voltages were balanced in Figure 13a, however the voltages were unbalanced due to the distortion in the modulation wave of phase b in Figure 14b. The overlap regions affect the results of the ALM. Thus, these results illustrate that the validity of the theoretical calculation for Case 3. faulty and bypassed, the remaining SMs voltages of the upper arm (usma5-usma20) increased, and their ripples also increased. The voltage increments were less than 10% of the rated voltage, it was relatively safe for SM voltages. At time 0.4 s, the ALM method was used and the values of (usma5-usma20) return to the reference value. From the FFT analysis of the circulating current, shown in Figure  12f, we observed that a decrease of 60% in the fundamental frequency component and a decrease of 85% in the third harmonic. These results meet the theoretical analysis of the previous section, which demonstrated that the ALM will not cause over current in the arms or overvoltage in SM capacitors. From Equations (16) and (17), the maximum proportion of faulty SMs should be less than 30.72%N for an m = 0.8. When utilizing the simulation system by N = 20, the permitted greatest integer of faulty SMs is six. Figure 13 shows the results of the fault-tolerant ability when 30%N (xu = 6, k1 = 0.4) and x4 = 40%N (xu =8, k1 = 0.2). When x4 = 30%N, the line voltages were balanced, however, the voltages were unbalanced when x4 = 40%N. Thus, the simulation results illustrate the validity of the theoretical calculation for Case 1.   Figure 14b shows the results of xu = 4 and xl = 3. The line voltages were balanced in Figure 13a, however the voltages were unbalanced due to the distortion in the modulation wave of phase b in Figure 14b. The overlap regions affect the results of the ALM. Thus, these results illustrate that the validity of the theoretical calculation for Case 3.

Experimental Studies
For evaluating the feasibility and effectiveness of the proposed fault-tolerant strategies, a downscaled three-phase MMC prototype (N = 4) was utilized in this section. Figure 15 shows the experiment platform. The proposed methods were implemented in a digital signal processor. Meanwhile, a field programmable gate array was used to finish the PWM function. Every sub-module is controlled by a local complex programmable logic device. The parameters of this platform are listed in Table 4. For evaluating the feasibility and effectiveness of the proposed fault-tolerant strategies, a downscaled three-phase MMC prototype (N = 4) was utilized in this section. Figure 15 shows the experiment platform. The proposed methods were implemented in a digital signal processor. Meanwhile, a field programmable gate array was used to finish the PWM function. Every submodule is controlled by a local complex programmable logic device. The parameters of this platform are listed in Table 4.  a) GDPWM Figure 16 shows the results of GDPWM under one faulty and bypassed sub-module (usma1) in the upper arm of phase a. From the results one can see that the healthy capacitor usma2 increased 2 V during this fault period before the fault-tolerant strategy. When GDPWM was activated, the lower arm capacitor voltage usma5 was lower than its rated value and the upper arm capacitor voltage usma2 stopped increasing. The upper arm output voltage uau was changed by k = 0 during the fault. From Figure 16b one can see that the DC-bus current and arm currents iau, ial are distorted. When GDPWM was used, AC output currents (ia, ib) were not affected pre-and post-fault.  a) GDPWM Figure 16 shows the results of GDPWM under one faulty and bypassed sub-module (u sma1 ) in the upper arm of phase a. From the results one can see that the healthy capacitor u sma2 increased 2 V during this fault period before the fault-tolerant strategy. When GDPWM was activated, the lower arm capacitor voltage u sma5 was lower than its rated value and the upper arm capacitor voltage u sma2 stopped increasing. The upper arm output voltage u au was changed by k = 0 during the fault. From Figure 16b one can see that the DC-bus current and arm currents i au , i al are distorted. When GDPWM was used, AC output currents (i a , i b ) were not affected pre-and post-fault. For evaluating the feasibility and effectiveness of the proposed fault-tolerant strategies, a downscaled three-phase MMC prototype (N = 4) was utilized in this section. Figure 15 shows the experiment platform. The proposed methods were implemented in a digital signal processor. Meanwhile, a field programmable gate array was used to finish the PWM function. Every submodule is controlled by a local complex programmable logic device. The parameters of this platform are listed in Table 4.  a) GDPWM Figure 16 shows the results of GDPWM under one faulty and bypassed sub-module (usma1) in the upper arm of phase a. From the results one can see that the healthy capacitor usma2 increased 2 V during this fault period before the fault-tolerant strategy. When GDPWM was activated, the lower arm capacitor voltage usma5 was lower than its rated value and the upper arm capacitor voltage usma2 stopped increasing. The upper arm output voltage uau was changed by k = 0 during the fault. From Figure 16b one can see that the DC-bus current and arm currents iau, ial are distorted. When GDPWM was used, AC output currents (ia, ib) were not affected pre-and post-fault.

b) ALM
In the following simulations and experiments, the ALM was enabled at time t0. Sub-module usma1 was assumed to exhibit a fault at time t1. At time t2, the ALM method was enabled.
Illustrative experimental results are given in Figure 17, with the circulating current control enabled at all times. The unbalanced line voltages were balanced due to the ALM scheme used. The fundamental frequency component could be measured in the DC-link current idc (Figure 17a). By using the ALM scheme, the fluctuation in idc decreased by 60%. In Figure 17b, the remaining submodule voltages in the upper arm increased, but the fluctuations of capacitor voltages were also stable. When the modulation was reconfigured, the SM voltages returned to their reference values. The arm currents iau,ial, circulating current iadiff are also shown in Figure 17c. Although a small fundamental frequency component was still present in the circulating current, there was no overcurrent in arm currents when the SM fault occurs.

b) ALM
In the following simulations and experiments, the ALM was enabled at time t 0 . Sub-module u sma1 was assumed to exhibit a fault at time t 1 . At time t 2 , the ALM method was enabled.
Illustrative experimental results are given in Figure 17, with the circulating current control enabled at all times. The unbalanced line voltages were balanced due to the ALM scheme used. The fundamental frequency component could be measured in the DC-link current i dc (Figure 17a). By using the ALM scheme, the fluctuation in i dc decreased by 60%. In Figure 17b, the remaining sub-module voltages in the upper arm increased, but the fluctuations of capacitor voltages were also stable. When the modulation was reconfigured, the SM voltages returned to their reference values. The arm currents i au ,i al , circulating current i adiff are also shown in Figure 17c. Although a small fundamental frequency component was still present in the circulating current, there was no overcurrent in arm currents when the SM fault occurs.

b) ALM
In the following simulations and experiments, the ALM was enabled at time t0. Sub-module usma1 was assumed to exhibit a fault at time t1. At time t2, the ALM method was enabled.
Illustrative experimental results are given in Figure 17, with the circulating current control enabled at all times. The unbalanced line voltages were balanced due to the ALM scheme used. The fundamental frequency component could be measured in the DC-link current idc (Figure 17a). By using the ALM scheme, the fluctuation in idc decreased by 60%. In Figure 17b, the remaining submodule voltages in the upper arm increased, but the fluctuations of capacitor voltages were also stable. When the modulation was reconfigured, the SM voltages returned to their reference values. The arm currents iau,ial, circulating current iadiff are also shown in Figure 17c. Although a small fundamental frequency component was still present in the circulating current, there was no overcurrent in arm currents when the SM fault occurs.

c) Comparison
Simulation and experiment results of GDPWM and ALM indicated that the two strategies can achieve the fault-tolerant ability. The healthy SM capacitor voltages in the leg under ALM could reach to the rated value. Due to the obvious DC component, the fluctuations and average value of healthy SM capacitor voltages in the arms were different under GDPWM. It is consistent to the analysis of Equation (20). Thus, ALM achieved a better performance compared to GDPWM.

Conclusions
In this paper, a mathematical model for the fundamental and triple frequency components under SM fault and modulation reconfiguration conditions are derived. The proposed modulation reconfiguration methods to account for the faulty SMs in the arms of the MMC suppresses the overcurrent when fault detection, localization and modulation reconfiguration occurs while providing control of the circulating current under faulty SM conditions. The feasibility and effectiveness of proposed methods have been demonstrated by simulations and experiments results on three-phase 21-level and five-level MMC topologies.

c) Comparison
Simulation and experiment results of GDPWM and ALM indicated that the two strategies can achieve the fault-tolerant ability. The healthy SM capacitor voltages in the leg under ALM could reach to the rated value. Due to the obvious DC component, the fluctuations and average value of healthy SM capacitor voltages in the arms were different under GDPWM. It is consistent to the analysis of Equation (20). Thus, ALM achieved a better performance compared to GDPWM.

Conclusions
In this paper, a mathematical model for the fundamental and triple frequency components under SM fault and modulation reconfiguration conditions are derived. The proposed modulation reconfiguration methods to account for the faulty SMs in the arms of the MMC suppresses the overcurrent when fault detection, localization and modulation reconfiguration occurs while providing control of the circulating current under faulty SM conditions. The feasibility and effectiveness of proposed methods have been demonstrated by simulations and experiments results on three-phase 21-level and five-level MMC topologies. [sin(2ωt + ϕ) + sin ϕ] −