Design and Implementation of Finite Time Nonsingular Fast Terminal Sliding Mode Control for a Novel High Step-Up DC-DC Converter

: In this paper, a new, high step-up quadratic boost converter with high conversion efﬁciency is discussed. A storage capacitor and resonant inductor are connected in series with a clamp capacitor through a diode. These compose a voltage multiplier cell, which is applied on the switch of the quadratic boost converter. The clamp capacitor can protect the switch from a voltage spike and absorb energy when the switch turns off; then, the storage capacitor and resonant inductor are charged by the energy stored in the clamped capacitor to increase the voltage transfer gain. In addition, the voltage multiplier cell can also reduce the voltage stresses of power devices. Then, a 16 V input, 200 V output prototype with 80 W nominal power is built up and tested. Furthermore, a ﬁnite time fast terminal sliding mode (NFTSM) control is proposed, with constant frequency for the voltageFundamental Building B213:tracking control of this converter. The new NFTSM is obtained by introducing an adjustable nonlinear term into fast terminal sliding mode (FTSM) control, and a singularity problem is avoided. The experiment illustrates that the maximum efﬁciency of the proposed converter achieves 95% at D = 0.25, V o = 150 V. The voltage stress is reduced to half of the corresponding component of the basic boost converter at the same voltage level. Moreover, the proposed NFTSM controller can track the reference signal, and provide a short settling time of about 48 ms with no overshoot, and the system response exhibits strong robustness against 11.7% input voltage disturbance and 30% load variation.


Introduction
Recently, the fast development of electronics products, such as solar energies, uninterruptible power supplies (UPS), and electric automobiles have been witnessed [1][2][3]. DC-DC converters has been wildly applied to these applications. However, due to a low and varying input voltage of these applications, the boost converter is a convenient solution for step-up conversion. However, it is difficult for the conventional converter to provide such a high direct-current (DC) voltage gain. Moreover, many power devices of boost converters suffer from overlarge stress at a high output voltage level, leading to decreased efficiency [4].
Some scholars have strived to increase steady voltage gain and efficiency of boost converters. Some structures, such as the cascaded structure or switched-capacitor [5][6][7] can extend the steady voltage gain at a low cost. However, with the increase of voltage gain, more stages are adopted, leading to a complex circuit and significant current ripple [8]. In some isolated converters [9,10], much high-voltage conversion ratios can be achieved at a relatively low-duty cycle, but the leakage

Topology of the Proposed High Step-Up DC-DC Converter
The proposed converter based on a quadratic boost converter and a clamp circuit consisted of D 3 , C c , and was applied on the switch (Q) to clamp the voltage of the switch and eliminate voltage spikes in the turned-off state. Then, C c , D 4 , C r , L r were composed a multiplier cell so that capacitor C r could absorb energy from C c during the turned-on state of the switch in a resonant way, and release energy to the load (R) and output capacitor (D o ) during the turned-off state. By recycling the energy stored in C c , the voltage gain of the proposed converter has been improved. The voltage stresses of output diode D o and switch Q were halved compared to the conventional boost converter, and the conversion efficiency was promoted, owing to the clamp circuit. More detailed theoretical analyses can be found later on. Figure 1 plots the simplified equivalent circuit of the proposed converter. Some assumptions were postulated to simplify circuit analysis, as the following:

Operational Principles
(1) The converter works with high operation frequency, and all components are ideal; (2) L 1 , L 2 are sufficiently large, such that the circuit operates under the current continuous mode (CCM); (3) C 1 , C o are also large enough, such that the voltage across them are considered as a constant.
In accordance with above assumptions, a complete period mainly includes six operation modes, and the simplified equivalent circuit of every mode is shown in Figure 2. It restarts the whole process after mode 6 is finished. Mode 1 ([t 0 -t 1 ], (a)): at the instant t 0 , the switch Q is turned off, D 1 , D 4 , D o are reverse biased, and D 2 , D 3 are conducted. The input source (V in ) and L 1 , L 2 release energy to C c through D 3 , and to C 1 through D 2 . During this mode, the converter can be modeled as follows: where i L 1 , i L 2 ,i L r , i Cc denote the current flowing through L 1 , L 2 , L r , and C r , respectively; V in , V o , V C1 denote the averaged input voltage, output voltage, and the voltage across C 1 . Mode 2 ([t 1 -t 2 ], (b)): at the instant t 1 , D 1 , D 4 are reverse biased, and D o begins to be conducted. The input source (V in ) and L 1 , L 2 release energy to C c , C 1 , R, and C o unceasingly. i L 1 , i L 2 decrease linearly until the switch is turned on. The resonant inductor current (i Lr ) increases linearly until it equals the input current (i in ). In this mode, the new dynamics of this converter can be modeled as follows: di Mode 3 ([t 2 -t 3 ], (c)): at the instances t 2 , D 3 , D 1 , D 4 is reverse biased, and D 2 , D o were conducted. The charging process of C c was completed. The input source (V in ) and L 1 , L 2 release energy to R and C o , sequentially. In this mode, the extra dynamics of this converter can be modeled as follows: Mode 4 ([t 3 -t 4 ], (d)): at the instant t 3 , the switch Q is turned on, and D 2 , D 3 , D 4 were reverse biased, and D 1 , D o were conducted. L 1 , L 2 start to absorb energy from the input sources (V in ) and C 1 . The resonant inductor current reduces to zero until D o is blocked. In this mode, the new dynamics can be modeled as follows: Mode 5 ([t 4 -t 5 ], (e)): at the instances t 4 , D 2 , D 3 , D o it is reverse-biased. The resonant process starts when D o is reverse-biased. The diode D 4 transfers energy stored in C c to C r in a resonant way [23]. D 4 is blocked when half of the resonant period is completed at the instant t 5 . It is noticed that the average output voltage of the proposed converter is equal to the average voltage across C r , plus the voltage of C c . The new dynamics in this mode can be modeled as follows: C eq = C e C r C e + C r (17) where C eq denotes the equivalent capacitance of the multiplier cell, and ω 0 is the angular frequency of this cell. Mode 6 ([t 5 -t 6 ], (f)): at the instant t 5 , the resonant process stops, and D 4 is reverse biased. L 1 , L 2 store energy from the input source (V in ) and C 1 sequentially until the switch is turned off. A new period restarts from mode 1. In this mode, the new dynamics can be modeled as follows:  Figure 3 shows the theoretical operation waveforms of some key variables in a case of a duty cycle D = 0.5 to exhibit operating principles of the converter ulteriorly. The time period from t 0 -t 6 represents a complete operating cycle, where t 0 -t 3 represents a duration of the switch turned off, and t 4 -t 6 represents a duration of the switch turned on.
Observing Figure 3, one can see that the resonant inductor current (i Lr ) starts to rise at t 1 until it reaches the value of i L2 , and then decreases linearly during t 2 -t 3 . A half period of a resonant procedure is completed during t 4 -t 5 .

The Voltage Gain
To simplify the analysis, only modes 2, 3, 5, and 6 were considered, while modes 1, 4 were neglected due to their short duration and micro-variation of the related variables. During modes 2 and 3, the switch was turned off, and L 1 and L 2 started to release energy to C 1 , C c , R. The voltage of inductors functions are described in (1), (2).
When the switch is turned on during modes 5 and 6, L 1 , L 2 start to store energy from the input source (V in ) and C 1 , demonstrated in (11)- (12). When the circuit arrives at a steady state, using the inductor voltage-second balance principle on the inductors L 1 and L 2 in the whole period, the following equations can be achieved: where D denotes the duty cycle. According to (20)-(21), the steady voltage of C 1 and C c can be obtained by: The average voltage of C r is equal to the average voltage across Cc because it is charged by C c during mode 5. Moreover, C r is connected in series with the output of the quadratic converter. The output voltage gain of this converter is given by: The voltage gain of boost converter is expressed as: According to [11], the voltage gain of the quadratic boost converter is given by: The comparison between the voltage gain and duty cycle of the proposed converter and other converters are plotted in Figure 4. According to Equations (24)-(26) and from Figure 4, one can observe that the voltage gain of the proposed converter is higher than that of a conventional boost converter and twice as much as that of quadratic converter under the same duty cycle. The voltage gain of the converter in [9] where a coupling inductor exists is higher than the proposed converter at the duty cycle under 0.55. However, the proposed converter provides the highest voltage gain among these converters when the duty cycle is larger than 0.55.

The Power Device Stresses
The voltage across the switch (Q) equals V cc when it is turned off. During modes 1, 5, and 6, D o is reverse biased, meaning this voltage of D o can be described as follows: The maximum voltage stresses of the switch (Q) and output diode (D o ) compared with those in [9,10] are given in Table 1. n, k represent the turns ratio of a coupling-inductor and switching capacitor stages in Table 1. It shows that the voltage stresses are half of those of a quadratic converter and boost converter at the same voltage level. The voltage stress in converters [9,10] changes with the duty cycle. Moreover, the switching voltage stresses of the proposed converter is also smaller than that of converters in [9,10].

Key Power The Proposed The Converter The Converter The Boost
The Quadratic Devices Converter in [9] in [10] Converter Converter

Key Parameters Design
Input inductances: When the switch is turned on, the current variation of the input inductor L 1 and L 2 can be described by: The average current of the input inductor L 1 and L 2 in the whole period can be described by: To ensure that the proposed converter is operating in CCM, the current variation (∆i L 1 , ∆i L 2 ) of input inductors L 1 and L 2 must be smaller than double that of the average current ( i L 2ss , i L 2ss ) in the whole period.
∆i L ≤ 2i ss (32) According to (28)-(32), the inductances are given by: where f denotes the switching frequency. Stored capacitors: ∆V C o , representing the voltage ripple of C o , can be described by: According to (31), the capacitances of C o are calculated by: thus, the capacitance of C 1 is also calculated by Voltage multiplier capacitors: The maximum output power is limited by the energy stored in C c , C r . The output voltage will decrease if the load power increases above that of the nominal output power (P max ) [24]. In other words, the voltage multiplier will lose voltage boost effect and only operate as a clamp circuit. The capacitance of C c should be about ten times larger or more than C r . The minimum capacitance of C c is calculated by: Resonant inductor: Half of the resonant period must be smaller than the duration of the switch turned on.
where T r denotes the resonant period of the voltage multiplier cell, and T denotes the switching period. According to (39), the resonant inductance and capacitance must satisfy the following inequality: The resonant inductor limits the current variation of the switch. Thus, the inductance can be selected according to the maximum current rate of change of a actual switch device. The minimum inductance is calculated by: where ∆i/dt max is the maximum current change rate of the switch.

Modeling of the Proposed Converter
According to the aforementioned assumption and analysis, modes 1 and 4 were neglected. The current flowing into C c was also neglected. The voltages of C c and C r were considered as a constant. During modes 2 and 3, the switch was turned off, and the relative state equations can be described as (1)-(3) and During modes 5 and 6, the switch was turned on, and the relative state equations can be described as (11)- (14). Thus, the switch model of the proposed converter operating in CCM can be written as: where u is the control input which takes "0" to be the turned-off state and "1" as the turned-on state of the switch, respectively. To design the proposed finite sliding mode controller for the converter, the output voltage V o was set as the control variable. The tracking error can be explicated as: where e 1 is the voltage error, and V r is the reference voltage.
Taking the derivative of (44), one can obtain a differential equation. Then, substituting (43) into this equation yields:ė

Improved Finite Time Fast Terminal Sliding Mode
Many typical TSM and FTSM can be described as: where k 1 > 0, k 2 > 0, p > q, a is formed of q a /p a , and p, q, p a , q a are both positive odd integers satisfying p > q, a ≥ 1, respectively. It is evident that TSM (S 1 ) accelerates the convergence rate within the vicinity of the equilibrium point and the state trajectory converges the sliding surface in finite time, owing to the non-linearly term x q p . However, TSM also offers a relatively slow convergence rate when the system trajectory stays at a distance from the equilibrium point. Based on (42), it can be concluded that the dynamics are globally finite-time stable, and it reaches the steady state within the time: In FTSM, k 2 x a guarantees the convergence rate when the system dynamic is far away from the equilibrium point. Moreover, k 1 x q p determines finite time convergence when the system state trajectory is close to the equilibrium point. Thus, the dynamic converges quickly in the whole convergence process, and converges to an equilibrium point within the time: where F(·) represents the Gauss Hypergeometric Function [25], and the coefficients of q p , a, k 1 , k 2 attract F(·) to keep convergent.
In order to accelerate the convergence rate further, an improved NFTSM scheme was proposed as follows: where k 1 > 0, k 2 > 0, k 3 > 0, b, c are also formed of q b /p b , q c /p c respectively. p b , q b , p c , q c are both positive odd integers satisfying 1 < c < 2, a > c, b > 1. It is concluded that the system will arrive at the equilibrium point, and the convergence time is given by: From the above equation, it is observed that the convergence time of S 3 is shorter than T 1 and T 2 because of the extra item, There is a convergence performance comparison between TSM, FTSM, and the improved NFTSM. The following sliding modes are considered: with the initial value x(0) = 10. The corresponding response curves are given by Figure 5. It can be seen that the improved NFTSM (S 3 ) has a faster convergence rate than FTSM (S 2 ) and TSM (S 1 ).

Controller Design of DC-DC Converter
Now, consider the dynamical system (45), according to the scheme of NFTSM, the switching surface is defined as follows: For the proposed converter with a single switch, a general control law satisfying the hitting condition can be plotted as: To guarantee that the system state stays within the vicinity of the sliding surface, the existence condition derived from Lyapunov's direct method must be obeyed: whereṠ 3 is the time derivative of S 3 , and is shown as follows: Substituting (56) into (55) gives the following existence condition: every coefficient must be satisfied by (57), considering the minimum of the load.
To overcome a variable switching frequency of this system suffering external disturbance, an equivalent sliding mode control with constant operation frequency is adopted. EquatingṠ yields the equivalent control input: To improve the transient response, an exponential reaching law is chosen, and can be expressed as:Ṡ where k 4 , k 5 are positive parameters. When (60) is solved for u, the control input can be obtained as: Finally, the control input u and ramp signal V ramp = 1 with a constant frequency were fed into a pulse-width modulator to produce the practical control input. Thanks to u, the system converged quickly to an equilibrium point within a finite time. It should be noted that no singularity exists during the whole process, owing to 0 < c < 2. Theorem 1. For the system (45), when the control input is chosen as (61), the system trajectory will then converge quickly to a steady state within a finite time.
Proof of Theorem 1. Consider the Lyapunov function candidate as: It can be seen that whenė 1 = 0,V ≤ 0, the system state will slide to the sliding mode S = 0 within a finite time. Whenė 1 = 0, by substituting (61) into the second equation of (45), one can obtain: Equation (64) can be rewritten as:ė This equation indicates thatė 2 < −k 5 for S > 0 andė 2 > k 5 for S < 0. Therefore, the system trajectory will continue moving to an equilibrium point instead of staying on the state of e 1 = 0 and e 2 = 0. Moreover, it can be assumed that there exists a vicinity of e 2 = 0, |e 2 | ≤ δ, ( δ is a positive constant) and satisfyingė 2 < −k 5 for S > 0 andė 2 > k 5 for S < 0, respectively. Therefore, the crossing of trajectories between two boundaries of |e 2 | ≤ δ is achieved in a finite time, and the trajectory from the region |e 2 | ≥ δ reach the boundaries in finite time too. It can be summarized that the system controlled by (61) can converge to S = 0 from any initial state within a finite time. This completes the proof.

Experimental Results
To illustrate the effectiveness of the previous theoretical analysis, a laboratory prototype of the proposed converter was built and experimented. The related parameters of this system are shown in Table 2. Table 2. Related parameters of this system.  Figure 6 shows the voltage waveforms across the switch and output diode (D o ), respectively when the output voltage is at 200 V. From (a), it shows that the voltage of the switch equals to 100 V at the "OFF" state, with a small voltage spike about 10 V at the moment when the switch turned off.
The subgraph (b) shows that the anode voltage of the output diode (D o ) to the ground reaches 100 V at the reversed state when the cathode voltage is at 200 V with no voltage spike. One can see that the voltage stress of the output diode arrives at 100 V equalling to half of the output voltage too. Therefore, the voltage stresses of the output diode and switch have been alleviated. Figure 7a indicates that the switching waveform maintains about four periods in a grid that represents 100 µs against a variational output voltage. One can see that the equivalent control (u) keeps the switching period constant, at about 25 µs.
The efficiency versus a wide range of duty cycle and output voltage is plotted in Figure 7b. It shows that the peak efficiency reaches 95% at D = 0.25,V o = 150 V. The efficiency reduces with the increase of the duty cycle, due to an increasing duty cycle accompanied by a more severe conduction loss of the switch and reverse loss of diodes. In addition, the efficiency, at a 150 V output voltage, only has a small advantage than when the output voltage is 200 V, meaning that the output voltage also has a slight impact on the efficiency. This is because the improved output voltage aggravates the heat loss of inductors and capacitors.
An experiment was also carried out for the performance analysis of the proposed NFTSM controller. The result is given in Figures 8-10. The startup transient response is shown in Figure 8, the output voltage against input voltage variation plots in Figure 9, and the output voltage versus load disturbance is illustrated in Figure 10, respectively.   Figure 8c, one can seen that the output voltage controlled by the proposed controller can track the reference value (200 V) with no overshoot, and has a settling time about 48 ms. Figure 8a, the system controlled by the TSM controller (S 1 ) takes 104 ms to reach the reference value (200 V), and the system controlled by the FTSM controller (S 2 ) has a settling time of 64 ms in Figure 8b. we can notice that the proposed controller has a 29.4%, 64.8% settling time improvement than FTSM and TSM, respectively, in this system. Figure 9 shows the steady output voltage (V o ) comparison against input voltage disturbance. The input voltage changes from 17 V to 15 V (11.7%) and then returns to 17 V. From the Figure 9c, the output voltage (V o ) response exhibits no obvious variation. Figure 9a, one can see that the output voltage (V o ) response controlled by the TSM controller (S 1 ) takes about 100 ms to recover to the reference value, accompanied by a variation of 10 V (5%). The output voltage (V o ) response controlled by the FTSM controller (S 2 ) has a 80 ms recovery time, and a variation of 10 V too in Figure 9b. However, a sharp voltage spike was not visible in the three responses. The steady output voltage response versus the output load variation is demonstrated in Figure 10. Here, resistance changes of −150 Ω (−30% variation) were added to a nominal output load of 500 Ω, and then the load returned to 500 Ω. Figure 10c, one can see that the output voltage controlled by the proposed controller almost remains constant at the reference value. Figure 10a, the output voltage controlled by the TSM (S 1 ) controller has a slight voltage variation of about 8 V, and takes about 60 ms of recovery time after the moment where the load's resistance has been decreased, and has a settling time of 25 ms with a variation of 8 V after the moment of the load's resistance turns back. Figure 10b, the output voltage controlled by the FTSM (S 2 ) controller has 80 ms recovery time with a variation of 5 V after the instant where the load's resistance is been changed the first time; then, it takes 40 ms to reach the reference signal with a small variation after the moment of the load's resistance turning back. According to Figures 9 and 10, it can be seen that the proposed NFTSM controller has the strongest robustness amongst the three methods. Based on the above results, it can be noticed that the proposed controller has faster convergence time and greater robustness compared with the TSM (S 1 ) and FTSM (S 2 ) controller. Thus, the proposed control scheme is more superior than the TSM and FTSM control strategies for the high step-up converter. In addition, there was no sharp voltage spike in the voltage waveforms of the switch, diodes, and output voltage at different test conditions, meaning that some low-cost elements can be used.

Conclusions
A high step-up DC-DC converter based on a single-switch quadratic boost converter and a limited time converge fast terminal sliding mode control strategy was proposed in this paper. Firstly, the operation modes, performance discussion, and key parameter design of the proposed converter were presented. Owing to the voltage multiplier cell, the voltage gain of the proposed converter was highly enhanced; in particular, the peak efficiency reached 95% at an output voltage range of (100 V-200 V). At the mean time, the voltage stresses of the switch and diodes (D 3 , D 4 , D o ) were decreased to half of the output voltage, and the conversion efficiency was improved. Then, a new finite-time NFTSM scheme was proposed. This can provide a faster convergence rate and stronger robustness than the conventional TSM and FTSM schemes. In particular, the singularity problem does not exist during the whole convergence process. Finally, the proposed controller was applied to the converter to stabilize it and track the reference signal. The experiment demonstrates that the system controlled by the proposed controller can track the reference voltage with a short settling time of about 48 ms and no overshoot. The strong robustness of the proposed controller against input voltage variation and load disturbances was also verified.
Author Contributions: Y.L. designed the NFTSM controller and accomplished the theoretical proof; J.W. designed the topology of the proposed converter, implemented the experiments, and wrote the paper; H.T. designed the circuit and analysed the data.