Simple DC-Link Voltage Balancing Approach for Cascaded H-Bridge Rectifier with Asymmetric Parameters of Independent DC Loads

Jin Zhu 1, Tongzhen Wei 1,2,*, Ming Ma 3 and Libo Han 1 1 Institute of Electrical Engineering, Chinese Academy of Sciences, Haidian District, Beijing 100190, China; zhujin_whut@126.com (J.Z.); hanlibo@mail.iee.ac.cn (L.H.) 2 University of Chinese Academy of Sciences, Beijing, Shijingshan District, Beijing 100049, China 3 Institute of Electric Power Science, Guangdong Power Grid Company, Guangzhou, Guangdong 510080, China; sdmaming@126.com * Correspondence: tzwei@mail.iee.ac.cn; Tel.: +86-10-82547105


Introduction
Nowadays, it is well established that the cascaded H-bridge (CHB) is the most suitable choice for many medium-voltage high power applications [1][2][3], especially for synchronous rectifier application which have two or more independent DC loads, but one of the most extensively addressed drawbacks of CHB rectifiers is the DC voltage balancing across all DC-link of the H-bridge sub-modules (SMs) with asymmetric parameters of independent DC loads [4].A variety of methods have been proposed to maintain the voltage balancing across the capacitors of cascaded modular structure, including carrier phase-shift pulse width modulation (PS-PWM), nearest level modulation (NLM), predictive control strategy, phase disposition-pulse width modulation (PD-PWM).
NLM has been widely used in a large-scale sub-module scenario, such as a voltage source converter high-voltage direct current (VSC-HVDC) converter station [5,6].However, NLM normally requires an additional filtering device when the number of sub-modules is insufficient for medium-voltage applications, because the output is a step waveform that contains a large proportion of harmonic waves.
As in a medium-voltage scenario when there are fewer sub-modules, phase shift PWM (PS-PWM) have proved to be a viable candidate for implementation [4,[7][8][9].In order to balance the DC-link voltage, an extra proportional-integral module can be added to the control unit of each SM to adjust Energies 2019, 12, 1654 3 of 20 voltage.The capacitor will charge or discharge during the period of the ON status of the chopper SM depending on the direction of I L .For example, if I L > 0, the capacitor would be charged, and if I L < 0, the capacitor would be discharged.The capacitor voltage will not change or discharge while the chopper SM is OFF.and if IL < 0, the capacitor would be discharged.The capacitor voltage will not change or discharge while the chopper SM is OFF.
Figure 1b shows a 5-SM single-phase CHBR.Unlike the capacitor of chopper SM will only charge or discharge during the period of the ON status, the charge-discharge law of H-bridge SM, as shown in Table 2, not only depends on the direction of IL but also depends on the output voltages (USMi).
Compared Tables 1 and 2, the charge-discharge law of H-bridge SM is more complicated than chopper SM, hence the cascaded H-bridge SMs structure has more switching states that need to be considered and the PD-PWM used in CHB structures must be different from the PD-PWM used in CC structures.The differences will be described in Section 3. Table 1.Working states of chopper sub-module.The State of the DC-Link Capacitor

Mode S1 S2
Figure 1b shows a 5-SM single-phase CHBR.Unlike the capacitor of chopper SM will only charge or discharge during the period of the ON status, the charge-discharge law of H-bridge SM, as shown in Table 2, not only depends on the direction of I L but also depends on the output voltages (U SMi ).Compared Tables 1 and 2, the charge-discharge law of H-bridge SM is more complicated than chopper SM, hence the cascaded H-bridge SMs structure has more switching states that need to be considered and the PD-PWM used in CHB structures must be different from the PD-PWM used in CC structures.The differences will be described in Section 3.

PD-PWM Method
As an important modulation method, phase disposition PWM (PD-PWM) has been widely used in multilevel modulation of various topologies such as cascaded half-bridge sub-modules structures and cascaded H-bridge sub-module structures.

PD-PWM Used in Cascaded Chopper Structure
The principle of PD-PWM used in cascaded chopper structure is shown in Figure 2, N number of triangular carrier signals and one modulation signal can be used to produce N + 1 level output voltage levels [20,21], where each triangular carrier signal consists of two components: the standard triangle wave ranging from 0 to 0.2 and the corresponding bias ∆U i (i = 1-5) .In Figure 2, ∆U 1 = 0, ∆U 2 = 0.2, ∆U 3 = 0.4, ∆U 4 = 0.6, ∆U 5 = 0.8.Assuming the period of the triangular carrier signal is Ts, the output voltage and the DC-link voltage of SM i (i = 1-5) can be described as: where U ci(k+1) is the DC-link voltage of SM i at the end of this period, U ci(k) is the DC-link voltage of SM i at the beginning of this period, D is the duty cycle, I L(k) is the current value of this period, U SMi is the output voltage of the SM i , C is the capacitor value of DC-link.It can be seen from Equations ( 1) and ( 2) that charge-discharge state of SM depends on the comparison results of the corresponding triangular carrier signal and modulation signal (U m_CC ) as shown in Table 3.The (N + 1)-level modulation truth table can be shown as Table 4. Here, "1" means that the corresponding SM is ON, while "0" means OFF.P1-P5 are the PWM wave based on comparison results of the triangular carrier signal and the modulation signal.The range of normalized signals corresponds to regions I-V.In each region, each SM has a different PWM signal [20,21].For example, when the modulation signal U m_CC is in region II, P2 will be transferred to SMs 2. At the same time, "1" will be outputted to SMs 1, and "0" will be outputted to SMs 3, 4, and 5. Other regions can also be analyzed like this.

Relationship of Modulation Signal (U m_CC ) and Corresponding Triangular
Carrier Signal (U tsi )

Conventional PD-PWM Used in Cascaded H-Bridge Structure
In a conventional phase disposition pulse width modulation technique used in CHB, like in a cascaded chopper SMs structure, one sinusoidal modulation signal is compared with triangular carrier signals to generate gate signals for the semiconductor switches of every H-bridge SMs in CHB structure.The difference is that 2N number of triangular carrier signal should be used for CHB structure N number SMs to ensure the capacity of 2N + 1 output voltage levels [19,21].The working principle of conventional PD-PWM used in CHB is described in [21].

Dual Modulation Signal Based PD-PWM Used in Cascaded H-Bridge Structure
Using a double number triangular carrier signal (2N number of triangular carrier signal for N number of SMs in CHB structure) will increase the complexity of the control system as the number of SM increases.To overcome the above problem, a dual modulation signals based PD-PWM method is used in this paper as shown in Figure 3.The (2N + 1) output voltage levels are fully exploited only by N number of triangular carrier signals and dual modulation signals.The same as Figure 2, each triangular carrier signal consists of two components: the standard triangular wave ranging from 0 to 0.2 and the corresponding bias ∆U i (i = 1-5) , and in Figure 3, ∆U 1 = 0, ∆U 2 = 0.2, ∆U 3 = 0.4, ∆U 4 = 0.6, ∆U 5 = 0.8.Assuming the period of the triangular carrier signal is Ts, the output voltage and the DC-link voltage of SM i (i = 1-5) can be described as Equations ( 3) and (4): results of the triangular carrier signals and the dual modulation signals (shown in Table 5).The range of normalized signals corresponds to regions I-V.In each region, each SM has a different PWM signal.For example, when the reference voltage signal Um_CHB1 is in region II, based on Table 6, −P2 and −P4 will be transferred to SM2 and SM4.At the same time, "−1" will be output to SM3, and "0" will be output to SM1 and SM5.Other regions can also be analyzed like this.The output level and charge-discharge state of SM depends on the comparison results of the corresponding triangular carrier signal and dual modulation signals as shown in Table 5.
According to Figure 3 and Table 5, the (2N + 1)-level modulation truth table can be shown as Table 6.Here, "1" means that the output voltage of corresponding SM is "U c ", "−1" means that the output voltage of corresponding SM is "−U c ", while "0" means output voltage of SM is "0".The value of PWM signals (P1 to P5, −P1 to −P5) would change in one cycle based on the comparison results of the triangular carrier signals and the dual modulation signals (shown in Table 5).The range of normalized signals corresponds to regions I-V.In each region, each SM has a different PWM signal.For example, when the reference voltage signal U m_CHB1 is in region II, based on Table 6, −P2 and −P4 will be transferred to SM2 and SM4.At the same time, "−1" will be output to SM3, and "0" will be output to SM1 and SM5.Other regions can also be analyzed like this.

Dynamic Carrier Bias Allocation Strategy Based on Operation Condition
The working state and charge-discharge law of H-bridge SM is more complicated than a chopper SM as shown in Tables 1 and 2. Hence, a different PD-PWM modulation strategy (dual modulation signal-based PD-PWM) is used in CHB structures as described in Section 3, and their switch combination is fundamentally different as shown in Tables 4 and 6.In this paper a new dynamic triangular carrier signal bias allocation method is proposed based on new charge-discharge law of dual modulation signal-based PD-PWM suitable for CHB structures.The switching state rules can be seen in Table 6.For N sub-module CHB structure (suppose N is an odd number), it can be described as Equations ( 5)-( 7): where U carrier_longest_forward is the bias value that enables the corresponding SM has the longest forward access time to the main circuit, U carrier_shortest_forward_1 and U carrier_shortest_forward_2 are the bias value that enable the corresponding SMs have the shortest forward access time to the main circuit, U carrier_longest_reverse is the bias value that enables the corresponding SM has the longest reverse access time to the main circuit, U carrier_shortest_reverse_1 and U carrier_shortest_reverse_2 are the bias value that enable the corresponding SMs have the shortest reverse access time to the main circuit.U carrier_base is the basic bias value of triangular wave and is set to 0 in this paper, ∆U is the standard triangular wave range, and Ûm_CHB is the peak-to-peak value of modulation signal.Take N = 5, Ûm_CHB = 1 as an example, thus the rules mentioned in Equations ( 5)-( 7) can be transferred to: (1) In Area 1, when U m_CHB_1 > U m_CHB_2 , the SM superposed with the bias value "0.4" has the longest forward access time to the main circuit, and the SMs superposed with the bias value "0" and "0.8" have the shortest forward access time to the main circuit.(2) In Area 2, when U m_CHB_1 < U m_CHB_2 , the SM superposed with the bias 3 signal has the longest reverse access time to the main circuit, and the SM superposed with the bias 1 signal and the bias 5 signal has the shortest reverse access time to the main circuit.
Considering these rules and the charge-discharge law of H-bridge SM in Table 2, the charge-discharge law based on area partition and the CHB structure current (I L ) direction can be divided into two operation condition, for N sub-module CHB structure (suppose N is an odd number), it can be described as Equations ( 8) and ( 9): where U carrier_fastest_charge is the bias value that enables the corresponding SM in fastest changing state, U carrier_slowest_charge_1 and U carrier_slowest_charge_2 are the bias value that enable the corresponding SMs in the slowest changing state, U carrier_fastest_discharge is the bias value that enables the corresponding SM in the fastest discharging state, U carrier_slowest_discharge_1 and U carrier_slowest_discharge_2 are the bias value that enable the corresponding SMs in the slowest discharging state.The symbol where Ucarrier_fastest_charge is the bias value that enables the corresponding SM in fastest changing state, Ucarrier_slowest_charge_1 and Ucarrier_slowest_charge_2 are the bias value that enable the corresponding SMs in the slowest changing state, Ucarrier_fastest_discharge is the bias value that enables the corresponding SM in the fastest discharging state, Ucarrier_slowest_discharge_1 and Ucarrier_slowest_discharge_2 are the bias value that enable the corresponding SMs in the slowest discharging state.The symbol ⌊x⌋ is a floor function which means an integer less than x but nearest to x.Take N = 5 as an example, the charge-discharge law mentioned in Equations ( 8) and ( 9) is as shown in Table 7.

Realization of Proposed Dynamic Carrier Bias Allocation Method for CHB
To maintain the DC-link voltage of SM balance, there are two mechanisms: the loop bias distribution (LBD) method and the enhanced dynamic bias allocation method based on DC voltage MIN/MAX value comparison.
The loop bias distribution (LBD) method allocates the bias value with a predetermined cycle rule and regardless of the charge-discharge law or real-time DC-link voltage of SMs, but this method works only under symmetric conditions.A practical modulation method should not only be effective in a symmetrical system, but also have the ability to regulate dynamically and provide some error correction capabilities to ensure that the system works well under the conditions of asymmetric parameters of independent DC loads.This paper focus on the realization of dynamic bias allocation method based on operation condition to achieve the effect of dynamic regulation ability for CHB structure with floating DC capacitor and asymmetric parameters of independent DC loads in each SM.
As shown in Figure 3, in PD-PWM method, each triangular carrier signal consist two components: the standard triangular wave and the corresponding bias ΔUi (i = 1-N).Take N = 5 as an example, Figure 3 can be translated to be expressed with the schematics shown in Figure 4.In order to keep the DC voltages of each SM in balance, ΔUi should be added to Ui as needed, as shown in Figure 4.
is a floor function which means an integer less than x but nearest to x.Take N = 5 as an example, the charge-discharge law mentioned in Equations ( 8) and ( 9) is as shown in Table 7.The loop bias distribution (LBD) method allocates the bias value with a predetermined cycle rule and regardless of the charge-discharge law or real-time DC-link voltage of SMs, but this method works only under symmetric conditions.A practical modulation method should not only be effective in a symmetrical system, but also have the ability to regulate dynamically and provide some error correction capabilities to ensure that the system works well under the conditions of asymmetric parameters of independent DC loads.This paper focus on the realization of dynamic bias allocation method based on operation condition to achieve the effect of dynamic regulation ability for CHB structure with floating DC capacitor and asymmetric parameters of independent DC loads in each SM.
As shown in Figure 3, in PD-PWM method, each triangular carrier signal consist two components: the standard triangular wave and the corresponding bias ∆U i (i = 1-N) .Take N = 5 as an example, Figure 3 can be translated to be expressed with the schematics shown in Figure 4.In order to keep the DC voltages of each SM in balance, ∆U i should be added to U i as needed, as shown in Figure 4.For the partitioning of the operation condition in Table 7 in each triangular carrier signal period, we can use the following steps to calculate the bias value that should be superposed on each triangular carrier signal of each SM: 1) The current real-time measured and the dual modulation signal generation method described in the Section 3.2 are used to determine the operation condition for the CHB structure at the current time (as defined in Equations ( 8) and ( 9)).  2), it can be expressed as Equation ( 10): (10) where IndexUc_min is the SM index having the minimum capacitor voltage, IndexUc_max is the SM index having the maximum DC voltage, for example, if in j triangular carrier signal wave cycle, SM4 has the lowest voltage and SM5 has the highest voltage, the Y array would be assigned like Figure 5a.And if in j + 1 triangular carrier signal wave cycle, SM1 has the lowest voltage and SM3 has the highest voltage, the Y array would be assigned like Figure 5b.
3) Then, a new multiport triangular carrier signal bias selector array ΔU[Y(k)] has to be set up, as shown in Equations ( 11)- (13).Its index is Y(k).A flag is the symbol of operation condition classification of Table 7.For the partitioning of the operation condition in Table 7 in each triangular carrier signal period, we can use the following steps to calculate the bias value that should be superposed on each triangular carrier signal of each SM: (1) The current real-time measured and the dual modulation signal generation method described in the Section 3.2 are used to determine the operation condition for the CHB structure at the current time (as defined in Equations ( 8) and ( 9)). ( 2 where Index Uc_min is the SM index having the minimum capacitor voltage, Index Uc_max is the SM index having the maximum DC voltage, for example, if in j triangular carrier signal wave cycle, SM4 has the lowest voltage and SM5 has the highest voltage, the Y array would be assigned like Figure 5a.And if in j + 1 triangular carrier signal wave cycle, SM1 has the lowest voltage and SM3 has the highest voltage, the Y array would be assigned like Figure 5b. (3) Then, a new multiport triangular carrier signal bias selector array ∆U[Y(k)] has to be set up, as shown in Equations ( 11)- (13).Its index is Y(k).A flag is the symbol of operation condition classification of Table 7.
Energies 2019, 12, x FOR PEER REVIEW 10 of 20 Take N = 5 as an example, if the Flag = 0 (Operation condition classification I), ΔU[Y (1)] would be assigned to "0.4" to make the corresponding SM in fastest charging state.And ΔU[Y (2)] would also be assigned to "0"or "0.8".If the Flag = 1 (operation condition classification II in Table 7), ΔU[Y (1)] would be assigned to "0.8" or "0".And ΔU[Y (2)] would also be assigned to "0.4".For example as mentioned above, if in in j triangular carrier signal wave cycle, SM4 has the lowest voltage and SM5 has the highest voltage, Figures 6a,b show the bias value assignment of ΔUi, and if in j + 1 triangular carrier signal wave cycle, SM1 has the lowest voltage and SM3 has the highest voltage, Figures 6c,d show the bias value assignment of ΔUi.As described above, the dynamic carrier bias allocation method can readjust the bias value of each SM according to the method mentioned above in every triangular carrier signal wave cycle so as to dynamically balance the capacitor voltage of each SM.The aforementioned method is embedded as a modulation strategy into the CHB structure grid-connection control strategy.
In this paper, a two-stage cascaded controller is employed to achieve the control goals.The outer loop is responsible for regulating the total voltage of capacitors by a classical PI controller.The output of the PI controller is a DC signal which controls the amplitude of active current which is absorbed from grid.The inner loop is a current controller which ensures the current tracking the reference value.A proportional-resonant controller is used to achieve this goal in this paper.The output of current controller is used to produce modulation signal of PD-PWM.In each triangular carrier signal cycle and according to the operation condition classification as shown in Table 7, the balancing algorithm mentioned above assigns appropriate bias to the corresponding triangular carrier signal of each SM in a way that the CHB rectifier synthesizes AC voltage at its AC terminals.Take N = 5 as an example, if the Flag = 0 (Operation condition classification I), ∆U[Y(1)] would be assigned to "0.4" to make the corresponding SM in fastest charging state.And ∆U[Y(2)] would also be assigned to "0"or "0.8".If the Flag = 1 (operation condition classification II in Table 7), ∆U[Y(1)] would be assigned to "0.8" or "0".And ∆U[Y(2)] would also be assigned to "0.4".For example as mentioned above, if in in j triangular carrier signal wave cycle, SM4 has the lowest voltage and SM5 has the highest voltage, Figure 6a 2)] would also be assigned to "0"or "0.8".If the Flag = 1 (operation condition classification II in Table 7), ΔU[Y(1)] would be assigned to "0.8" or "0".And ΔU[Y( 2)] would also be assigned to "0.4".For example as mentioned above, if in in j triangular carrier signal wave cycle, SM4 has the lowest voltage and SM5 has the highest voltage, Figures 6a,b show the bias value assignment of ΔUi, and if in j + 1 triangular carrier signal wave cycle, SM1 has the lowest voltage and SM3 has the highest voltage, Figures 6c,d show the bias value assignment of ΔUi.As described above, the dynamic carrier bias allocation method can readjust the bias value of each SM according to the method mentioned above in every triangular carrier signal wave cycle so as to dynamically balance the capacitor voltage of each SM.The aforementioned method is embedded as a modulation strategy into the CHB structure grid-connection control strategy.
In this paper, a two-stage cascaded controller is employed to achieve the control goals.The outer loop is responsible for regulating the total voltage of capacitors by a classical PI controller.The output of the PI controller is a DC signal which controls the amplitude of active current which is absorbed from grid.The inner loop is a current controller which ensures the current tracking the reference value.A proportional-resonant controller is used to achieve this goal in this paper.The output of current controller is used to produce modulation signal of PD-PWM.In each triangular carrier signal cycle and according to the operation condition classification as shown in Table 7, the balancing algorithm mentioned above assigns appropriate bias to the corresponding triangular carrier signal of each SM in a way that the CHB rectifier synthesizes AC voltage at its AC terminals.As described above, the dynamic carrier bias allocation method can readjust the bias value of each SM according to the method mentioned above in every triangular carrier signal wave cycle so as to dynamically balance the capacitor voltage of each SM.The aforementioned method is embedded as a modulation strategy into the CHB structure grid-connection control strategy.
In this paper, a two-stage cascaded controller is employed to achieve the control goals.The outer loop is responsible for regulating the total voltage of capacitors by a classical PI controller.The output of the PI controller is a DC signal which controls the amplitude of active current which is absorbed from grid.The inner loop is a current controller which ensures the current tracking the reference value.A proportional-resonant controller is used to achieve this goal in this paper.The output of current controller is used to produce modulation signal of PD-PWM.In each triangular carrier signal cycle  7, the balancing algorithm mentioned above assigns appropriate bias to the corresponding triangular carrier signal of each SM in a way that the CHB rectifier synthesizes AC voltage at its AC terminals.

Simulation
In this paper, the electromagnetic transient simulation software PSIM is used to formulate a single-phase converter model for the CHB rectifier grid-connection model.The simulation parameters are shown in Table 8.In order to test the ability of this method to regulate the dynamic DC-link voltage under conditions of asymmetric parameters of independent DC loads, a 20 Ω resistor was paralleled to capacitor of SM1, and the proposed dynamic bias allocation function would be on at 0.7 s.The bias relationship has been changed after 0.7 s, and the results are shown in Figure 7.

Simulation
In this paper, the electromagnetic transient simulation software PSIM is used to formulate a single-phase converter model for the CHB rectifier grid-connection model.The simulation parameters are shown in Table 8.In order to test the ability of this method to regulate the dynamic DC-link voltage under conditions of asymmetric parameters of independent DC loads, a 20 Ω resistor was paralleled to capacitor of SM1, and the proposed dynamic bias allocation function would be on at 0.7 s.The bias relationship has been changed after 0.7 s, and the results are shown in Figure 7.
The capacitor voltages of the five SMs are shown in Figure 8, respectively.It is clear that the capacitor voltages are balanced after 0.7s and the capacitor voltage of SM1 is close to the other ones in the CHB while the capacitor voltages have been adjusted equally.
Figure 9 shows the corresponding output voltage.The difference of the capacitor voltage can be greatly reduced, and the system output voltage is improved as shown in Figure 9.
To test the dynamic response of the developed method to variations in the current, the current value is suddenly changed during the simulation in t1 (as shown in Figure 10).The increase in the current causes the amplitude of the capacitor voltage fluctuations to increase (as shown in Figure 11).However, the voltage of each sub-module capacitor voltage remains balanced.This result demonstrates the desirable dynamic response of the PD-PWM strategy that is based on dynamic bias allocation method.The capacitor voltages of the five SMs are shown in Figure 8, respectively.It is clear that the capacitor voltages are balanced after 0.7s and the capacitor voltage of SM1 is close to the other ones in the CHB while the capacitor voltages have been adjusted equally.Figure 9 shows the corresponding output voltage.The difference of the capacitor voltage can be greatly reduced, and the system output voltage is improved as shown in Figure 9.To test the dynamic response of the developed method to variations in the current, the current value is suddenly changed during the simulation in t1 (as shown in Figure 10).The increase in the current causes the amplitude of the capacitor voltage fluctuations to increase (as shown in Figure 11).However, the voltage of each sub-module capacitor voltage remains balanced.This result demonstrates the desirable dynamic response of the PD-PWM strategy that is based on dynamic bias allocation method.A different value of resistor was paralleled to the capacitor of SM1 at different times while a 20 Ω resistor was paralleled to the capacitors of other sub-modules to test the maximum admissible unbalancing ratio.Before 1 s, 20 Ω was paralleled to DC capacitor of SM1-SM5.Between 1 and 1.2 s, the paralleled resistor value of SM1 turned to 10 Ω. Between 1.2 and 1.4 s, the paralleled resistor value of SM1 turned to 8 Ω.After 1.4 s, the paralleled resistor value of SM1 turned to 7 Ω.It can be seen in Figure 12a that the DC capacitor voltage remains balanced before 1.4 s, and become unbalanced in 1.4 s, so the maximum admissible unbalancing ratio can be estimated to be about 40% (8 Ω/20 Ω) based on the simulation results, which means that the ratio of equivalent DC paralleled resistors of SMs should not be less than 40% while using the proposed balance method.The variation of AC current is shown in Figure 12b.The power of AC side and the sum value of DC side output power of CHBR is shown in Figure 12c, It can be seen that both the active and reactive power at the input of the rectifier were controlled well before 1.4 s, the active power controller responds quickly to the sum value of DC side output power of SM1-SM5, and the reactive power is close to zero.
Energies 2019, 12, x FOR PEER REVIEW 14 of 20 the paralleled resistor value of SM1 turned to 10 Ω. Between 1.2 and 1.4 s, the paralleled resistor value of SM1 turned to 8 Ω.After 1.4 s, the paralleled resistor value of SM1 turned to 7 Ω.It can be seen in Figure 12a that the DC capacitor voltage remains balanced before 1.4 s, and become unbalanced in 1.4 s, so the maximum admissible unbalancing ratio can be estimated to be about 40% (8 Ω/20 Ω) based on the simulation results, which means that the ratio of equivalent DC paralleled resistors of SMs should not be less than 40% while using the proposed balance method.The variation of AC current is shown in Figure 12b.The power of AC side and the sum value of DC side output power of CHBR is shown in Figure 12c, It can be seen that both the active and reactive power at the input of the rectifier were controlled well before 1.4 s, the active power controller responds quickly to the sum value of DC side output power of SM1-SM5, and the reactive power is close to zero.However, maximum admissible unbalancing ratio is not a fixed coefficient because it depends on many factors such as the ratio of active and reactive power.While the paralleled resistor value of SM1 turned to 7 Ω in 1.4 s as the same as the condition mentioned above and keep the given value of active power unchanged, but the given value of reactive power is turned to 3 kW after 1.5 s, the DC capacitor voltage get back in balance as shown in Figure 13, that means maximum admissible unbalancing ratio will rise as the given value of reactive power increase.

Experiments
To further verify the feasibility of the modulation strategy, an experimental platform for the three sub-modules was set up in the lab, as shown in Figure 14.The experimental parameters are shown in Table 9.However, maximum admissible unbalancing ratio is not a fixed coefficient because it depends on many factors such as the ratio of active and reactive power.While the paralleled resistor value of SM1 turned to 7 Ω in 1.4 s as the same as the condition mentioned above and keep the given value of active power unchanged, but the given value of reactive power is turned to 3 kW after 1.5 s, the DC capacitor voltage get back in balance as shown in Figure 13, that means maximum admissible unbalancing ratio will rise as the given value of reactive power increase.

Experiments
To further verify the feasibility of the modulation strategy, an experimental platform for the three sub-modules was set up in the lab, as shown in Figure 14.The experimental parameters are

Experiments
To further verify the feasibility of the modulation strategy, an experimental platform for the three sub-modules was set up in the lab, as shown in Figure 14.The experimental parameters are shown in Table 9.
of each sub-module is maintained.Figures 15 and 16 show that even with unbalanced DC load parameters, the improved PD-PWM strategy developed here can still achieve the desired voltage balancing and a fast response.
At t3, we change the value of the current while both ends of the SM 1 capacitor are still connected in parallel with a 100-Ohm resistor, as shown in Figure 17. Figure 17 shows the inductor current and the voltage waveform of the three sub-module capacitors when the current value changes.Figure 18 shows the inductor current and the output voltage waveform for the CHB structure when the current value changes.Figures 17 and 18 show that when the value of the reactive current changes dynamically, the improved PD-PWM developed here can still ensure a balanced sub-module capacitor voltage around the set value and a fast dynamic response for the entire system.A multi-output isolation transformer is used to precharge the sub-module capacitor.An asymmetric condition is created by connecting the DC bus capacitor of SM1 in parallel with a 100-Ohm resistor and using the pre-charged circuit to charge the DC bus capacitor of SM2 and 3 to 40 V.At the start time (t1), the three sub-modules CHBR are connected to the power grid: the sub-module capacitor voltage waveform is shown in Figure 15.In Figure 15, the yellow line corresponds to the voltage waveform of the SM1 capacitor that is connected in parallel with a 100-Ohm resistor.At the period t1-t2, according to the control law, SM1 is charged to the rated voltage by the system injecting a large amount of active power with a large current amplitude into the CHB structure, as shown in Figure 16.With the improved PD-PWM strategy, the three sub-modules capacitor voltages begin to converge, and after the PI adjustment from t2, the stability of each sub-module is maintained.Figures 15 and 16 show that even with unbalanced DC load parameters, the improved PD-PWM strategy developed here can still achieve the desired voltage balancing and a fast response.At t3, we change the value of the current while both ends of the SM 1 capacitor are still connected in parallel with a 100-Ohm resistor, as shown in Figure 17. Figure 17 shows the inductor current and the voltage waveform of the three sub-module capacitors when the current value changes.Figure 18 shows the inductor current and the output voltage waveform for the CHB structure when the current value changes.Figures 17 and 18 show that when the value of the reactive current changes dynamically, the improved PD-PWM developed here can still ensure a balanced sub-module capacitor voltage around the set value and a fast dynamic response for the entire system.

Discussion
A comprehensive comparison between the proposed PD-PWM, conventional PD-PWM, PS-PWM, NLM, and predictive control method is summarized in Table 10, where more "+" means the corresponding control method performs better in the corresponding characteristic for CHBR with asymmetric parameters of independent DC loads.It can be seen in Table 10 that the proposed PD-PWM strategy has advantages in several aspects compared with the other control strategy: • Lower harmonic distortion in medium voltage application compared with NLM method, because of its AC side voltage is multilevel PWM waveform instead of step waveform; • Less computational effort compared with predictive control method; • Lower complexity of the control system compared with PS-PWM for no extra multiple proportional-integral control signal added to the reference voltage; • Much stronger dynamic regulation ability under the conditions of asymmetric parameters of independent DC loads for it can quickly adjust the access time of each sub-module in the beginning of each sampling period such as NLM.

Discussion
A comprehensive comparison between the proposed PD-PWM, conventional PD-PWM, PS-PWM, NLM, and predictive control method is summarized in Table 10, where more "+" means the corresponding control method performs better in the corresponding characteristic for CHBR with asymmetric parameters of independent DC loads.It can be seen in Table 10 that the proposed PD-PWM strategy has advantages in several aspects compared with the other control strategy:

•
Lower harmonic distortion in medium voltage application compared with NLM method, because of its AC side voltage is multilevel PWM waveform instead of step waveform; • Less computational effort compared with predictive control method; • Lower complexity of the control system compared with PS-PWM for no extra multiple proportional-integral control signal added to the reference voltage; • Much stronger dynamic regulation ability under the conditions of asymmetric parameters of independent DC loads for it can quickly adjust the access time of each sub-module in the beginning of each sampling period such as NLM.

Conclusions
This paper proposed a dynamic bias allocation method based PD-PWM considering the operation condition of CHBR structure with asymmetric parameters of independent DC loads.Through the analysis and demonstration mentioned above, the characteristics of the proposed modulation strategy are summarized as follows: (1) Simulation and experiment results show that this method has dynamic regulation ability to balance the DC voltage of each sub-module with asymmetry parameters of independent DC loads and a fast dynamic response for the entire system by allocate the bias of SMs flexibly; (2) Comparison analysis show that this method can reduce harmonic distortion in medium voltage applications compared with the NLM method when the number of sub-modules is insufficient for medium-voltage application while keep much stronger dynamic regulation ability because of the characteristics of the PWM method; (3) This method also facilitates engineering implementation in real applications because it has no issues of sorting (like the NLM method) and no need for extra multiple proportional-integral control signals added to the reference voltage (like the PD-PWM method), so the computational burden is also reduced.

Figure 3 .
Figure 3. PWM transfer relationships of dual modulation signal based unipolar PD-PWM of CHB.

Figure 3 .
Figure 3. PWM transfer relationships of dual modulation signal based unipolar PD-PWM of CHB.

4. 1 .
Charge-Discharge Law of Dual Modulation Signal Based PD-PWM Used in CHB Structure At first we analyzed the law of the capacitance fluctuations based on Figure 3.The relation of the two modulation signal (U m_CHB_1 , U m_CHB_2 ) are used to divide Figure 3 into two areas in one sinusoidal period as shown (U m_CHB_1 > U m_CHB_2 for Area 1 and U m_CHB_1 < U m_CHB_2 for Area 2.
2) The FPGA parallel calculation is used to select the maximum sub-module DC capacitor voltage and the minimum sub-module DC capacitor voltage at the current time.Uci (i = 1-N) are the DC capacitor voltages of the SMs, and they are compared to each other at the same time, which means that the time is limited.An array Y is used to record the comparative result.Y(1) would be equal to the SM index having the minimum DC capacitor voltage, Y(2) would be equal to the SM index having the maximum DC capacitor voltage.The other SMs indexes except the minimum and maximum DC capacitor voltages would also be assigned to the Y array by sequence after Y(
) The FPGA parallel calculation is used to select the maximum sub-module DC capacitor voltage and the minimum sub-module DC capacitor voltage at the current time.U ci (i = 1-N) are the DC capacitor voltages of the SMs, and they are compared to each other at the same time, which means that the time is limited.An array Y is used to record the comparative result.Y(1) would be equal to the SM index having the minimum DC capacitor voltage, Y(2) would be equal to the SM index having the maximum DC capacitor voltage.The other SMs indexes except the minimum and maximum DC capacitor voltages would also be assigned to the Y array by sequence after Y(2), it can be expressed as Equation (10):

Figure 5 .
Figure 5. Assignment of the Y array: (a) j carrier wave cycle; (b) j + 1 carrier wave cycle.
,b show the bias value assignment of ∆Ui, and if in j + 1 triangular carrier signal wave cycle, SM1 has the lowest voltage and SM3 has the highest voltage, Figure 6c,d show the bias value assignment of ∆Ui.Energies 2019, 12, x FOR PEER REVIEW 10 5 as an example, if the Flag = 0 (Operation condition classification I), ΔU[Y(1)] would be assigned to "0.4" to make the corresponding SM in fastest charging state.And ΔU[Y(
the operation condition classification as shown in Table

Figure 8 .
Figure 8. Capacitor voltages of the five SMs of CHB before and after the proposed bias allocation method is on.

Figure 7 .
Figure 7. Bias allocation of the SMs before and after the proposed bias allocation method is on.(a) Bias allocation of SM1; (b) Bias allocation of SM2; (c) Bias allocation of SM3; (d) Bias allocation of SM4; (e) Bias allocation of SM5.

Figure 8 .
Figure 8. Capacitor voltages of the five SMs of CHB before and after the proposed bias allocation method is on.

Figure 8 .
Figure 8. Capacitor voltages of the five SMs of CHB before and after the proposed bias allocation method is on.

Energies 2019 , 20 Figure 9 .
Figure 9. Output voltage of CHB before and after the proposed bias allocation method is on.

Figure 10 .
Figure 10.Waveform of inductor current for change in current reference.

Figure 11 .Figure 9 .
Figure 11.Sub-module voltage waveform under current variation.A different value of resistor was paralleled to the capacitor of SM1 at different times while a 20 Ω resistor was paralleled to the capacitors of other sub-modules to test the maximum admissible unbalancing ratio.Before 1 s, 20 Ω was paralleled to DC capacitor of SM1-SM5.Between 1 and 1.2 s,

Energies 2019 , 20 Figure 9 .
Figure 9. Output voltage of CHB before and after the proposed bias allocation method is on.

Figure 10 .
Figure 10.Waveform of inductor current for change in current reference.

Figure 11 .Figure 10 . 20 Figure 9 .
Figure 11.Sub-module voltage waveform under current variation.A different value of resistor was paralleled to the capacitor of SM1 at different times while a 20 Ω resistor was paralleled to the capacitors of other sub-modules to test the maximum admissible unbalancing ratio.Before 1 s, 20 Ω was paralleled to DC capacitor of SM1-SM5.Between 1 and 1.2 s,

Figure 10 .
Figure 10.Waveform of inductor current for change in current reference.

Figure 11 .Figure 11 .
Figure 11.Sub-module voltage waveform under current variation.A different value of resistor was paralleled to the capacitor of SM1 at different times while a 20 Ω resistor was paralleled to the capacitors of other sub-modules to test the maximum admissible unbalancing ratio.Before 1 s, 20 Ω was paralleled to DC capacitor of SM1-SM5.Between 1 and 1.2 s,

Figure 13 .
Figure 13.Simulation results of different reactive power.(a) Capacitor voltage of SM1-SM5; (b) Waveform of power delivered at the output and both the active and reactive power.

Figure 12 .
Figure 12.Simulation results of different unbalancing ratio of DC loads.(a) Capacitor voltage of SM1-SM5; (b) AC side current; (c) Waveform of power delivered at the output and both the active and reactive power.

Figure 13 .
Figure 13.Simulation results of different reactive power.(a) Capacitor voltage of SM1-SM5; (b) Waveform of power delivered at the output and both the active and reactive power.

Figure 13 .
Figure 13.Simulation results of different reactive power.(a) Capacitor voltage of SM1-SM5; (b) Waveform of power delivered at the output and both the active and reactive power.

Figure 14 .
Figure 14.Photo of the CHB rectifier for the experiment.Figure 14.Photo of the CHB rectifier for the experiment.

Figure 14 .Table 9 .
Figure 14.Photo of the CHB rectifier for the experiment.Figure 14.Photo of the CHB rectifier for the experiment.Table 9. Parameters of the study system of Figure 1b.Parameter Name Parameter Value Sub-unit capacitor voltage rating 40 V Sub-unit number N 3 Sub-unit capacitor value C 5 mF Grid-connection inductor L 6 mH AC voltage frequency f 50 Hz Carrier frequency 2000 Hz

Figure 17 .
Figure 17.Waveform of sub-unit capacitor voltage and inductor current for changing inductor current.

Figure 17 .
Figure 17.Waveform of sub-unit capacitor voltage and inductor current for changing inductor current.

Figure 17 .
Figure 17.Waveform of sub-unit capacitor voltage and inductor current for changing inductor current.

Figure 17 . 20 Figure 18 .
Figure 17.Waveform of sub-unit capacitor voltage and inductor current for changing inductor current.Energies 2019, 12, x FOR PEER REVIEW 18 of 20

Figure 18 .
Figure 18.Waveform of sub-unit capacitor voltage and inductor current for changing inductor current.

Table 1 .
Working states of chopper sub-module.

Table 2 .
Working states of H-bridge sub-module.

Table 4 .
Switch combinations of cascaded chopper structure using PD-PWM.

Table 3 .
Chopper SM output voltage and working states based on PD-PWM.

Table 4 .
Switch combinations of cascaded chopper structure using PD-PWM.

Table 6 .
Switch Combinations of Cascaded H-bridge Structure using PD-PWM.

Table 5 .
H-Bridge SM output voltage and working states based on PD-PWM.

Table 6 .
Switch Combinations of Cascaded H-bridge Structure using PD-PWM.

Table 7 .
Classification of operation conditions.
SM superposed with bias value "0.4" (SM for triangular carrier signal in vertical coordinate III area) is in fastest charging state; SM superposed with bias "0" and bias "0.8" (SM for triangular carrier signal in vertical coordinate I area and V area) is in slowest charging state.SM superposed with value "0.4" (SM for triangular carrier signal in vertical coordinate III area) is in fastest discharging state; SM superposed with bias "0" and bias "0.8" (triangular carrier signal in vertical coordinate I area and V area) is in slowest discharging state.

Table 7 .
Classification of operation conditions.
L > 04.2.Realization of Proposed Dynamic Carrier Bias Allocation Method for CHBTo maintain the DC-link voltage of SM balance, there are two mechanisms: the loop bias distribution (LBD) method and the enhanced dynamic bias allocation method based on DC voltage MIN/MAX value comparison. U U

Table 8 .
Parameters of the study System of Figure 1b.

Table 8 .
Parameters of the study System of Figure 1b.

Table 10 .
Comprehensive comparison with other various control strategy

Table 10 .
Comprehensive comparison with other various control strategy.