Integrated Control and Modulation for Three-Level NPC Rectifiers

This paper uses a novel approach for the control of three-level neutral-point-clamped (NPC) rectifiers in order to tackle the capacitor voltage balance problem. A distinctive feature of the new control approach is that it is based on a model which is written in terms of the duty ratios for each phase at each level. Hence, the system model presents nine duty cycle variables. Despite the fact that this formulation is different from the usual ones, it is shown that the control problem of currents and dc-link voltage can be formulated in a similar way to conventional methods. Furthermore, the control of the capacitor voltage balance can be expressed by means of equations that are decoupled from the currents and dc-link voltage dynamics, which results in a specific controller for the voltage balancing that does not affect the previous dynamics. A key point of the proposed approach is that part of the modulation stage is implicit in the formulation. Two particular controllers are compared in this paper. The first one fulfills the different control objectives at the expense of a large number of commutations. This problem is overcome in a new proposed controller, which presents similar performance and a satisfactory number of commutations. Experimental results are performed showing the effectiveness compared with a modified virtual space vector modulation with capacitor voltage balance capabilities.


Introduction
In the field of energy conversion systems, the advantages that multilevel power electronic converters offer are well known.Bidirectional power flow, increase of the output voltage magnitude, robustness, etc. are only some of the advantages that have made multilevel converters popular in medium and high power applications in the industry [1][2][3].Some of the different types of topologies of these converters are neutral-point-clamped, cascaded H-bridge or flying-capacitor [1,2,4].A Neutral-point-clamped (NPC) converter, which was proposed for the first time in [5], is one of the most used multilevel converter topologies.During normal operation, the voltage that drops across each capacitor must be balanced otherwise, it can result in poor output voltage quality, affecting the performance of the control or even damaging the semiconductor devices.Therefore, NPC converters present an additional objective apart from the usual control objectives in power converters [6] that is the voltage balance between capacitors, which is the main focus in this paper.
Over the last few years, numerous techniques have been developed to correct the voltage unbalance.Some of them use additional circuitry [7][8][9], but this would lead to an increase in cost, losses and complexity in hardware.Other authors use different control techniques with algorithms of varying difficulty [10][11][12][13][14][15].One of these control techniques [13] uses a modification of virtual space vector [16] (denoted as mVSVPWM in this paper).In [13], the voltage reference vector is obtained by creating virtual vectors where the possible switching states are weighted to generate currents that benefit the voltage balance.
Regarding the modelling, it is usual to work with averaged models where the discrete values of the gating elements are considered as continuous signals [1,17].In order to implement the control laws obtained with such models, a discretization stage, usually called modulation, needs to be accomplished [18].Modulation plays an important role in the overall system performance since properties such as number of commutations and harmonic distortion of currents and voltages are affected by the way modulation is carried out.Modulation methods can be classified into three main groups [19]: pulse width modulation (PWM) [20,21], pseudo-modulation [22] and closed-loop control methods with implicit modulator [23][24][25].
This paper presents a new approach to deal with the control of three-level NPC converters, which is based on [26].In this paper, the circuit model is formulated in terms of the duty ratios of each phase at each level.In this way, there are nine duty cycle variables (three duty cycles per phase) instead of just three (one duty cycle per phase).This formulation is not new, e.g., a similar model, based on d-q transformation, was presented in [27] to design an LQR controller for an NPC inverter by linearization using a small-signal model.In [26], it is shown that this formulation allows to explicitly consider, in the control design stage, the extra degree of freedom associated with the injection of homopolar component.The increase in the number of variables does not make the design significantly more difficult since, with an appropriate change of variables, the dc-link voltage and active and reactive power control problems can be formulated in a similar way to other usual approaches.As a result, the voltage balance controller can be easily designed at the same time that an important part of modulation is not needed.For this, the proposed approach can be considered as a control method with part of the modulation stage included in the control formulation, therefore, in what follows it would be called "Integrated Control and Modulation" (ICM).The main advantage of the proposed control law is its simplicity in implementation compared to modified versions of space vector modulation (SVM) [16] that also tackle the capacitor voltage unbalance but it still presents some advantages with respect to CB-PWM approaches.This is due to the fact that the modulation stage is simplified without losing part of the flexibility of SVM [28,29].Once the nine duties are computed, the way they are sequenced can be chosen freely, splitting them up or shifting them among the different phases.This freedom allows the user to achieve secondary control objectives similarly to SVM such as common-mode voltage reduction or avoidance of extra switching losses.For the sake of a fair comparison, this article will use a simple triangular-shaped sequence similar to that of CB-PWM approaches.Furthermore, the problem formulation for power, current and dc-link voltage control is the same as when using other conventional approaches, such as model-based direct power control (DPC) [30][31][32][33] or proportional-resonant controller (PR) for currents [34,35].
The drawback of the proposed approach in [26] is that it may lead to an unnecessary increase in the number of commutations.This is due to the fact that, unless some of the duty cycle variables turn out to be zero, the resultant switching signals will commute among all the levels for the three phases every sampling period.This is the case of the first control law considered in this paper (ICM1), whereas with the dc-link voltage, current or power control can be accomplished by switching each phase between two levels [36] when the voltage balance problem is not considered.In this paper, by using a remaining degree of freedom associated with the injection of homopolar component, some commutations are avoided compared to ICM1 presenting a second controller (ICM2) who explodes this capability.The output waveform of ICM2, as it will be shown later on in experiments, is similar to those approaches which inject a third harmonic signal into the output voltage to increase the fundamental signal range without overmodulating [37].Therefore, ICM2 also has this property inherent without the need of extra computations.
Both control laws are validated by means of experiments and compared with a control technique based on a modified virtual space vector modulation (mVSVPWM) [13], which includes capacitor voltage balance capabilities.Therefore, the main contributions of this paper in comparison with [26] are the inclusion of a new approach (ICM2) along with experimental verification of both approaches.
The next section is devoted to presenting the converter considered in this paper, as well as its dynamic model.Section 3 presents the controller design for fulfilling the three control objectives: regulation of the currents and the dc-link voltage and capacitor voltage balance.Section 4 proposes two variants for the selection of the remaining degrees of freedom resulting in two different controllers, ICM1 and ICM2.Section 5 presents experimental results.The paper closes with a section of conclusions.

Dynamic Model of the System
The configuration of the converter used in this paper is a three-phase three-level NPC converter in rectifier mode with a resistive load, as shown in the scheme of Figure 1.The electrical power grid is considered as a three-phase voltage source, where the phase voltages are represented by v sa , v sb and v sc .The converter is connected to the grid through an inductive filter where inductances have the same value L.
On the dc-link side, capacitors have the same value C and their voltages are denoted by v c1 and v c2 .Connected to the converter terminals there is a resistive load R. The total dc-link voltage is defined as

Considered System Model
The model considered in this paper is described in [26], which is based on a model presented in [27].This model uses the equations in αβγ coordinates by introducing the power-invariant form of the Clarke Transform.Furthermore, the switching signals have been replaced by their respective duty ratios in each level [27,38], d ij with i = α, β, γ and j = p, o, n, where p is the positive level when switches S i 1 and S i 2 are closed, o is the zero level when switches S i 1 and S i 2 are closed and n is the negative level when switches S i 1 and S i 2 are closed.This formulism yields where v d is the dc-link capacitor voltage difference defined by v d = v c1 − v c2 .The control inputs d αp , d αn , d βp and d βn are the duty ratios in αβγ coordinates.Control inputs d γp and d γn do not appear in the model, as mentioned in [26], because they are multiplied by i γ , whose value is zero for a balanced system.Similarly, variables d io do not appear in this model but their values can be retrieved at the final stage of the controller using the following constraints: Phase currents i α and i β can be expressed in terms of powers as where p and q are the instantaneous active and reactive powers of the system, respectively.In this way, ( 3) and ( 4) could be expressed as where variables v dc and v d are expressed in terms of the instantaneous power p and q.

Controller Design
With the purpose of dealing with the three control objectives (currents, dc-link voltage and capacitor voltage balance control), the system dynamic model ( 1)-( 4) presented previously is considered to design the controllers in this section.It can be seen that the proposed modeling allows to cope with the capacitor voltage balance problem while it does not affect the current and dc-link voltage controllers.

Total DC-Link Voltage Controller
In order to maintain constant the dc-link voltage and close to its reference (v r dc ), as usual, a PI controller is used [26,30,39], where constants k dc p and k dc i are controller tuning parameters.

Current Controller
Observing Equations ( 1) and ( 2), two virtual control variables can be defined as Introducing these variables into the currents dynamic model and assuming that the value of variable v d is small enough to be neglected, These expressions are equivalent to those current dynamics of the conventional two-level converter [26].Therefore, by the use of the change of variables ( 13) and ( 14), the added difficulty inherent for the adopted formulation disappears, at least at this stage.Additionally, introducing the references for the active (p r ) and reactive power (q r ) into ( 8) and ( 9), the current references can be retrieved (i r α , i r β ).Once these values are known, a non-ideal proportional-resonant controller [35], tuned at the grid frequency, is used to make the phase currents to track their references.In this way, the tracking error (i r α − i α , i r β − i β ) inputs the resonant controller, providing the value for control variables (u 1 , u 2 ).
where k p and k r are the proportional and resonant control parameters; ω c is the cut-off frequency of the low-pass filter implemented into the resonant part; and ω is the resonant frequency-tuned at the grid frequency ω g .

Voltage Balance Controller
The objective of the voltage balance controller is to keep the state variable v d close to zero, avoiding the unbalance of the dc-link capacitor voltages, and it is based on the definition of two new virtual control variables Introduction of (19) and ( 20) into (11) yields It is important to highlight that the definition of u 3 and u 4 causes a decoupling of the virtual control variables for control purposes.Note that u 1 and u 2 are designed to regulate the state variables p and q, whereas u 3 and u 4 can be used to regulate v d (21).This is an important benefit of the proposed control approach.
Taking into account (21), the proposed control laws [26] are defined as follows where positive constants k d and k di are customary tuning parameters.The reference for v d is denoted by v r d , which is set to zero to ensure a balanced distribution of the dc-link voltage across capacitors C 1 and C 2 .
By introducing ( 22) and ( 23) into ( 21), the voltage balance dynamics become linear: whose stability is assured provided that parameters k d and k d i are positive.A complete schematic block diagram of all controllers is illustrated in Figure 2.

Modulation Strategy
The controller presented in the previous section provides, at each sampling time, the values for u 1 , u 2 , u 3 and u 4 .The corresponding values for d αp , d αn , d βp and d βn can be obtained solving the system of Equations ( 13), ( 14), ( 19) and (20) yielding In order to compute the actual duty ratios d ij , i = a, b, c; j = p, n, the Clarke transformation can be used where d γp and d γn are remaining degrees of freedom.Obviously, the remaining duty ratios, d ao , d bo and d co can be computed using ( 5)-( 7).

First Proposal, ICM1
The first variant, ICM1, was proposed in [26].In this variant, d γp and d γn are chosen to be constant and can be considered as tuning parameters.In [26], guidelines are given in order to avoid saturation problems.This approach is a simple way to accomplish the modulation but it presents an important drawback: except by chance, none of the d ij will result in zero.This implies that, in each sampling time, each phase commutes among the three levels, which can be considered too many commutations compared with other controllers, even those including voltage balancing.This fact could yield large switching losses.

Second Proposal, ICM2
In order to avoid the large number of commutations, a new variant is proposed.This variant takes advantage of the two degrees of freedom associated with d γp and d γn by imposing, at each sampling period, one d ip and one d in to be zero.The two phases for which one of the duty ratios has to be zero need to be chosen carefully, as it is explained below, taking into account that the duty cycles in abc coordinates have to be in the interval [0, 1].The result is that these two phases only switch between two levels while the remaining phase commutes among the three levels.
In order to select these phases, the procedure checks if setting one of the d ij , i = a, b, c; j = p, n to zero yields to the fulfillment of the constraints 0 ≤ d ij ≤ 1 for the rest of duty cycle variables.Starting with the case d ap = 0, Equation ( 29) for j = p can be considered as a set of equations, where d αp , d βp are known, d ap = 0 and d bp , d cp and d γp are the unknowns.The resultant system of equations can be solved in order to check if this case is feasible, that is, if d bp and d cp are in the interval [0, 1].Repeating to the other phases, three different cases have to be analyzed for j = p and other three cases for j = n.The associated equations are Case 1: Case 2: Case 3: where j = p, n.The resultant duty ratios for the considered sampling instant are the corresponding ones to the feasible cases, that is, cases where all the duty cycles are in the interval [0, 1].It will be shown below that, at every instant, there exists at least one (and apart from some border cases, only one) feasible case.
Regarding the computation burden of this approach, after retrieving ( 25)-( 28), the calculation of the duty ratios d ij can be achieved by checking the constraints d ij ∈ [0, 1] for the 3 × 2 = 6 cases.For this, (30)- (35) have to be used twice (for levels p and n).This last stage implies the computation of 20 multiplications and 8 sums as well as 24 comparisons.
Alternatively, a different approach can be used to choose the correct case at every sampling instant with the help of Figure 3.This figure depicts the straight lines that are the boundaries of constraints 0 ≤ d ij ≤ 1 using expressions (30)- (35).Consequently, the shaded regions represent the fulfillment of these constraints for each one of the three cases above.As for each level j = p, n there is one d ij that it is equal to zero, there are four of such lines for each case, instead of six.It can be seen that the three shadowed areas do not overlap (except at their borders) and that they cover a whole hexagon.An interesting fact is that this hexagon is related to the well-known hexagon of Space Vector Modulation (SVM), but in this case, there are two such hexagons (one for j = p and one for j = n).The interest of Figure 3 is twofold: (1) it shows that, provided the converter does not work in overmodulation region, one of the three cases is always feasible, and (2) Figure 3 can be used as an alternative method to choose the correct case: the working sector can be computed as usual in SVM and once the appropriate case is selected, the corresponding formulae can be applied.
In summary, the ICM2 algorithm, whose data input and output are depicted in Figure 4, can be implemented in two alternative and equivalent ways that only differ in the computational burden, which in alternative B depends on the method used for the computation of the sextant: Alternative A:

•
For levels p and n: -Computation of Equations ( 30)- (35) and selection of the case that fulfills the constraints 0 ≤ d ij ≤ 1.This procedure gives directly the resultant duty cycles.

•
For levels p and n: -Computation of the sextant inside the hexagon of Figure 3.This step is similar to the corresponding one in SVM (but it must be computed twice, one for level p and one for level n).The sextant gives the corresponding case.-Computation of the duties using the corresponding Equations of ( 30)- (35).
It can be noted that the computational complexity is lower in both ICM1 and ICM2 with respect to SVM strategies that include control of the voltage balance, such as [13].

Experimental Verification
This section presents the experimental results obtained in the laboratory for the two approaches presented in this paper and the one used as a comparative (mVSVPWM) [13].To this end, the three-level NPC converter shown in Figure 5 has been used.It has been configured as rectifier and it has the circuit and control parameters provided in Table 1.A first-order low-pass filter has also been added to the proportional part of the total dc-link voltage controller, as it is recommended in [33], tuned at 5 KHz in order to reduce the harmonics presence.In order to show the control system behavior under different conditions, several stages with different resistive load values and reference voltages have been implemented.Starting with R = 120 Ω and v r dc = 700 V, a step in the load is applied to make R = 60 Ω at t = 0.8 s, then variable v r dc is modified from 700 to 800 V progressively from t = 1.5 s to t = 2.2 s, and finally the load is changed back to 120 Ω at t = 3.8 s.During the whole experiment, the instantaneous reactive power reference (q r ) has been assumed to be zero in order to guarantee unity power factor.
Figure 6 shows a comparative of the phase currents, system power and switching states of one phase for the three approaches under analysis in this paper.Regarding balancing capabilities, the capacitor voltage evolution starting from an unbalanced condition for the three approaches is depicted in Figure 7.To provide a more accurate analysis of the phase current distortion, a harmonic decomposition of phase a current (the blue one depicted in the left graph of Figure 6) is plotted in Figure 8 along with its total harmonic distortion (THD) value.The three approaches achieve a proper power tracking and balancing capabilities from unbalanced conditions, although, some differences can be noted.As it can be seen, approach mVSVPWM offers a similar outcome in terms of current distortion compared to the ICM1 one whereas the ICM2 approach entails a reduction in the current distortion (see current ripple in Figure 6 and THD values in Figure 8).On the other side, the time it takes for the modulation approach to balance the capacitor from the same unbalanced condition varies increasingly as mVSVPWM is fastest, ICM2 is in the second place and ICM1 is in last position.Despite that, the actual balancing time for ICM1 and ICM2 approaches are still acceptable for real applications.Both approaches have tunable parameters (k d , k di ) that can be increased in the case the application requires a faster balancing solution at the expenses of worsening the transients because of saturation issues, resulting in a trade-off between balancing speed and transient behaviour.
In regard to the number of commutations, the main differences can be noted in the switching states of Figure 6.In this term, ICM1 yields 800 commutations-jumps from one level to another-per grid period at 10 KHz of switching frequency; ICM2 yields 532, which is two thirds of ICM1 commutations; while mVSVPWM yields 375.Therefore, ICM2 presents an improvement in terms of current distortion when compared with ICM1 and mVSVPWM whereas ICM2 presents a commutation reduction when compared only with ICM1.The discussed features are presented in Table 2.
Regarding the computational burden, the execution times for ICM1 and ICM2 (using alternative A) are respectively 67% and 61% less than the time spent for the equivalent stage by the mVSVPWM technique [13], showing the simplicity of the presented methods compared to mVSVPWM.Moreover, the generation of the IGBT gating signals is simpler in the case of ICM1 and ICM2 compared to mVSVPWM as only several comparisons with a carrier wave are required.

Concluding Remarks
In this paper, the control of a three-level NPC rectifier has been addressed using a modeling approach that considers averaged duty cycle variables for the different levels in each phase.It has been shown that the associated extra degree of freedom can be used to balance the capacitor voltages.At the same time, it is shown that the design of the outer controllers (current and dc-link voltage controllers) is not affected by this approach.
In this way, the control law presented in [26] (ICM1) has been revisited and modified (ICM2) in order to reduce the main problem associated with the proposed approach: the high number of commutations and, therefore, losses.Furthermore, experiments have been made with a three-level NPC rectifier.The results obtained for the designed controllers have been quite satisfactory.
The main novelty of these two control laws is that, in spite of being based on an averaged model, control and modulation are integrated in the same stage.In this way, the controller yields directly the duty cycles for each phase in each level.Therefore, an algorithmic and computational simplification is achieved.
Experiments have been performed showing the benefits of the control laws presented in this paper and a comparison has been made with mVSVPWM [13], obtaining similar results in terms of THD for ICM1.On the other hand, the new approach ICM2 reduces the number of commutations at the same time that it reduces the high-order harmonics components, improving the THD value and the overall efficiency in comparison with ICM1.Both approaches accomplish the control objectives as they reduce the computational time of the control stage compared to mVSVPWM [13].

Figure 2 .
Figure 2. Complete schematic block diagram of the controllers.

Figure 3 .
Figure 3. Graphical representation of the limits of each case.

Figure 4 .
Figure 4. Data input and output of ICM1 and ICM2.

Figure 5 .
Figure 5. Experimental prototype of the three-level NPC rectifier.

Figure 6 .
Figure 6.Experimental results: (Left) Phase currents at steady state with v dc = 800 V, R = 60 Ω for the mVSVPWM (denoted as VSV in the figure legend), ICM1 and ICM2; (Center) evolution of the instantaneous power (p) and its reference (p r ) along different operating conditions for the three modulation approaches considered; (Right) switching states at steady state with v dc = 800 V, R = 60 Ω for the three approaches.

Figure 7 .
Figure 7. Experimental results: evolution of the capacitor voltages starting from an unbalanced condition, considering mVSVPWM (VSV in the figure), ICM1 and ICM2.

Figure 8 .
Figure 8. Experimental results: Harmonic spectrum and total harmonic distortion (THD) value of phase a current for the three approaches considered: mVSVPWM, ICM1 and ICM2.

Table 1 .
Circuit and control parameters.

Table 2 .
Main features of the considered approaches.