A Gate Driver Based on Variable Voltage and Resistance for Suppressing Overcurrent and Overvoltage of SiC MOSFETs

Abstract: A SiC MOSFET is a suitable replacement for a Si MOSFET due to its lower on-state resistance, faster switching speed, and higher breakdown voltage. However, due to the parasitic parameters and the low damping in the circuit, the turn-on overcurrent and turn-off overvoltage of a SiC MOSFET become more severe as the switching speed increases. These effects limit higher frequency applications of SiC MOSFET. Based on the causes of overcurrent and overvoltage of SiC MOSFET, a novel gate driver with the variable driving voltage and variable gate resistance is proposed in this paper to suppress the overcurrent and overvoltage of SiC MOSFETs. The proposed gate driver can realize the variation in driving voltage and gate resistance during switching transitions. It not only suppresses the overcurrent and overvoltage of SiC MOSFETs, but also has little effect on switching loss. The working principle of the proposed gate driver is analyzed in this paper. Finally, experimental verification on a double-pulse test platform is performed to verify the effectiveness of the proposed gate driver.


Introduction
Silicon carbide (SiC) MOSFETs have the advantages of high breakdown electric field, fast drift saturation of carriers, good thermal stability, and high thermal conductivity [1][2][3][4][5].These advantages of SiC MOSFETs can improve the performance of electronic converters.The switching frequency of power electronic converters based on SiC MOSFETs can even reach MHz, and the power density has been greatly improved because of the good switching characteristics of SiC MOSFETs [6][7][8][9].However, the turn-on overcurrent and turn-off overvoltage of SiC MOSFETs become more severe as the switching speed increases due to the parasitic parameters and the low damping in the circuit, which limits the switching frequency of SiC MOSFETs and even damages the devices [7][8][9][10][11][12][13][14].Therefore, it is necessary to reduce the turn-on overcurrent and turn-off overvoltage of SiC MOSFETs.At present, there are three methods to reduce the turn-on overcurrent and turn-off overvoltage of SiC MOSFETs.The first method is adding an RCD snubber circuit in the switching device or the main power loop [15,16].This method of increasing an RCD snubber circuit can suppress the turn-off overvoltage effectively, but the energy stored in the external capacitor will be released through the device channel when the device is turned on, which could increase the turn-on overcurrent and turn-on loss.The second method is the use of a DC-side snubber, this method can decouple a portion of parasitic inductance from the power loop by paralleling a decoupling capacitor in the bridge circuit.However, the parasitic inductance will resonate with the high-frequency decoupling capacitor if the decoupling capacitor is not large enough.The suppression effect is not good when the high-frequency decoupling capacitor is large enough to avoid low-frequency oscillation [14].The third method to suppress the overvoltage and overcurrent is increasing the gate resistor for slowing the switching speed, but switching loss is greatly increased as a result [1,17,18].Therefore, a two-stage gate driver based on a variable resistor is proposed in the literature [19].However, a two-stage gate driver only based on a variable resistor cannot achieve lower switching loss.Additionally, a multilevel gate driver based on a switched voltage is proposed [20]; its principle is based on a monotonic gate voltage.The multilevel gate driver can suppress the overvoltage and overcurrent, but the switching loss increases greatly.
A novel gate driving circuit based on variable driving voltage and variable gate resistance topology is proposed in this paper to suppress the overvoltage and overcurrent of SiC.The proposed gate driver can not only suppress the overvoltage and overcurrent of SiC MOSFETs, but also reduce the switching loss when compared with gate drivers presented in the literature.The causes of overvoltage and overcurrent of SiC MOSFETs are analyzed in detail in Section 2. Section 3 provides the topology and operation principle of the proposed gate driver.A double-pulse test platform based on the proposed gate driver is set up in Section 4 to verify the correctness and effectiveness of the proposed gate driver.

Overvoltage and Overcurrent of SiC MOSFETs
Figure 1 shows a double-pulse circuit considering the parasitic parameters.The circuit shown in Figure 1 can also be used to analyze the switching characteristics of Buck, Boost, Buck-Boost, Half Bridge, and Full Bridge circuits.In Figure 1, the input voltage V DC and the output current I o are constant.Q 1 is a SiC MOSFET.The parasitic parameters are the gate-source junction capacitance C GS , gate-drain junction capacitance C GD , drain-source junction capacitance C DS , gate parasitic inductance L G , common-source parasitic inductance L CS and internal gate resistance R G1 .R G2 is the external gate resistor and v P is the driving signal of Q 1 .
decoupling capacitor is large enough to avoid low-frequency oscillation [14].The third method to suppress the overvoltage and overcurrent is increasing the gate resistor for slowing the switching speed, but switching loss is greatly increased as a result [17][18][19].Therefore, a two-stage gate driver based on a variable resistor is proposed in the literature [20].However, a two-stage gate driver only based on a variable resistor cannot achieve lower switching loss.Additionally, a multilevel gate driver based on a switched voltage is proposed [21]; its principle is based on a monotonic gate voltage.The multilevel gate driver can suppress the overvoltage and overcurrent, but the switching loss increases greatly.
A novel gate driving circuit based on variable driving voltage and variable gate resistance topology is proposed in this paper to suppress the overvoltage and overcurrent of SiC.The proposed gate driver can not only suppress the overvoltage and overcurrent of SiC MOSFETs, but also reduce the switching loss when compared with gate drivers presented in the literature.The causes of overvoltage and overcurrent of SiC MOSFETs are analyzed in detail in Section 2. Section 3 provides the topology and operation principle of the proposed gate driver.A double-pulse test platform based on the proposed gate driver is set up in Section 4 to verify the correctness and effectiveness of the proposed gate driver.

Overvoltage and Overcurrent of SiC MOSFETs
Figure 1 shows a double-pulse circuit considering the parasitic parameters.The circuit shown in Figure 1 can also be used to analyze the switching characteristics of Buck, Boost, Buck-Boost, Half Bridge, and Full Bridge circuits.In Figure 1, the input voltage VDC and the output current Io are constant.Q1 is a SiC MOSFET.The parasitic parameters are the gate-source junction capacitance CGS, gate-drain junction capacitance CGD, drain-source junction capacitance CDS, gate parasitic inductance LG, common-source parasitic inductance LCS and internal gate resistance RG1.RG2 is the external gate resistor and  is the driving signal of Q1.
The freewheeling diode D uses a SiC JBS diode.The parasitic parameters inside the package are: junction capacitance CF and its on-resistance RF.LC, LD, LG, and LBUS represent the parasitic inductance of the branches where they are located (including parasitic inductances on the package and PCB connection lines).The freewheeling diode D uses a SiC JBS diode.The parasitic parameters inside the package are: junction capacitance C F and its on-resistance R F .L C , L D , L G , and L BUS represent the parasitic inductance of the branches where they are located (including parasitic inductances on the package and PCB connection lines).
Figure 2 shows the switching waveforms of Q 1 : the gate-source voltage v GS , the drain current i D , the drain-source voltage v DS , and the switching waveform of freewheeling diode voltage v F .The switching waveforms of a switching cycle can be divided into ten stages.

Causes of Turn-On Overcurrent
Stage 3, Turn-on overcurrent stage.When the  of the SiC MOSFET is equal to Io, the freewheeling diode D is able to block the voltage.The junction capacitance CF is charged, and the charging current flows through Q1 and causes  to have an overcurrent.Meanwhile, the junction capacitances CGS and CDS of the SiC MOSFET are discharged, the discharge current flows through its channel, and the channel current  also appears overcurrent.The equivalent circuit at this stage is shown in Figure 3a.The junction capacitance CF, CGS, and CDS are equivalent to current sources, and the Q1 channel is equivalent to a controlled current source.
The overcurrent of  is shown in Equation (1), and the overcurrent of  is shown in Equation (2).
In the above Equation,  /dt is the voltage variation rate of  , and  /dt is the voltage variation rate of  .According to Equation (1) and Equation (2), the overcurrent of Q1 is mainly determined by  /dt and  /dt, and the relationship shown in Equation (3) exists at this stage.

(
) In Equation (3), Vmil is the Miller voltage of Q1.Since the voltage VGS changes slightly at this stage, it can be considered as a constant.The turn-on overcurrent can be reduced by reducing the turn-on driving voltage VGS and increasing the external gate resistance RG2 according to Equation (3).
Stage 4, Current-oscillating stage.After the diode voltage  reaches the input voltage VDC, the SiC MOSFET can be equivalent to the on-state resistance RDS.The junction capacitance CF oscillates with the parasitic inductance of the power loop LBUS to consume the energy stored in CGS, CDS, CF before time t2.The equivalent circuit at this stage is shown in Figure 3b.

Causes of Turn-On Overcurrent
Stage 3, Turn-on overcurrent stage.When the i D of the SiC MOSFET is equal to I o , the freewheeling diode D is able to block the voltage.The junction capacitance C F is charged, and the charging current flows through Q 1 and causes i D to have an overcurrent.Meanwhile, the junction capacitances C GS and C DS of the SiC MOSFET are discharged, the discharge current flows through its channel, and the channel current i CH also appears overcurrent.The equivalent circuit at this stage is shown in Figure 3a.The junction capacitance C F , C GS , and C DS are equivalent to current sources, and the Q 1 channel is equivalent to a controlled current source.

Causes of Turn-Off Overvoltage
Stage 8, Turn-off overvoltage stage.After the drain-source voltage  is equal to VDC, D turns on.Q1 and D commutate, the rapid d /dt creates a voltage drop in the parasitic inductance LP.The voltage drop is superimposed on the drain-source of Q1 and a turn-off overvoltage appears.The equivalent circuit of this stage is shown in Figure 3c, and the overvoltage can be calculated by The overcurrent of i D is shown in Equation ( 1), and the overcurrent of i CH is shown in Equation (2).
In the above Equation, dv F /dt is the voltage variation rate of v F , and dv DS /dt is the voltage variation rate of dv DS .According to Equation (1) and Equation ( 2), the overcurrent of Q 1 is mainly determined by dv F /dt and dv DS /dt, and the relationship shown in Equation (3) exists at this stage.
In Equation ( 3), V mil is the Miller voltage of Q 1 .Since the voltage V GS changes slightly at this stage, it can be considered as a constant.The turn-on overcurrent can be reduced by reducing the turn-on driving voltage V GS and increasing the external gate resistance R G2 according to Equation (3).
Stage 4, Current-oscillating stage.After the diode voltage v F reaches the input voltage V DC , the SiC MOSFET can be equivalent to the on-state resistance R DS .The junction capacitance C F oscillates with the parasitic inductance of the power loop L BUS to consume the energy stored in C GS , C DS , C F before time t 2 .The equivalent circuit at this stage is shown in Figure 3b.

Causes of Turn-Off Overvoltage
Stage 8, Turn-off overvoltage stage.After the drain-source voltage v DS is equal to V DC , D turns on.Q1 and D commutate, the rapid di D /dt creates a voltage drop in the parasitic inductance L P .The voltage drop is superimposed on the drain-source of Q 1 and a turn-off overvoltage appears.The equivalent circuit of this stage is shown in Figure 3c, and the overvoltage can be calculated by Equation (4).At this stage, i D is approximately equal to i CH .Equation ( 5) can be derived according to the transconductance relationship of the SiC MOSFET. where Stage 9, Voltage-oscillating stage.When the i D drops to 0, the channel of the Q 1 is turned off.The C GD and C DS oscillate with the parasitic inductance L P to consume the energy stored in L P before time t 8 .The equivalent circuit in this stage is shown in Figure 3d.
Based on the above analysis, the parasitic inductance L P , transconductance g f , and dv GS /dt can determine the turn-off overvoltage.g f is a device parameter and it is not easy to change.Reducing the turn-off driving voltage amplitude −V SS and increasing the external gate resistance R G at this stage can suppress the turn-off overvoltage.

Proposed Gate Driving Circuit
Based on the analysis in Section 2, the turn-on overcurrent and turn-off overvoltage can be suppressed by reducing the driving voltage amplitude v P and increasing the external gate resistance R G .However, when this method is applied to the entire switching cycle, it will slow down switching speed in each stage.The switching loss will increase as a result.
Therefore, a novel gate driver based on the variable driving voltage and variable gate resistance topology for SiC MOSFETs is proposed in this paper.This proposed gate driver adopts different driving voltage and gate resistance during different switching stages.It can not only suppress the turn-on overcurrent and turn-off overvoltage but can also avoid serious switching loss.

Parameters Design of the Proposed Gate Driver
Figure 4 shows the structure of the proposed drive circuit.S 1 -S 4 are used to control the level of the driving voltage, and S A1 and S A2 are used to control the values of the gate resistance.R G3 and R G4 are smaller gate resistors, and R G5 and R G6 are larger gate resistors.The waveforms of the signals S 1 -S 4 and S A1 -S A2 , gate-source voltage v GS , drain current i D , drain-source voltage v DS , and freewheeling diode D voltage v F of the novel drive circuit are shown in Figure 5.
Energies 2019, 03, x FOR PEER REVIEW 5 of 14 driving voltage and gate resistance during different switching stages.It can not only suppress the turn-on overcurrent and turn-off overvoltage but can also avoid serious switching loss.

Parameters Design of the Proposed Gate Driver
Figure 4 shows the structure of the proposed drive circuit.S1-S4 are used to control the level of the driving voltage, and SA1 and SA2 are used to control the values of the gate resistance.RG3 and RG4 are smaller gate resistors, and RG5 and RG6 are larger gate resistors.The waveforms of the signals S1-S4 and SA1-SA2, gate-source voltage  , drain current  , drain-source voltage  , and freewheeling diode D voltage  of the novel drive circuit are shown in Figure 5.In order to suppress the overcurrent and overvoltage of SiC MOSFETs and avoid a serious increase in switching loss at the same time, the proposed gate driver needs to meet the following requirements: 1) Turn-on delay and current-rising stages.In order to achieve a faster turn-on speed to reduce turnon loss during these two stages, the gate resistance should be set as small as possible and the driving voltage during the two stages should be higher than normal, but the driving voltage cannot exceed the gate-source positive safety voltage (25V) of SiC MOSFET.
2) Turn-on overcurrent and current-oscillating stages.In order to reduce the d /dt, a larger gate resistance should be adopted during these two stages.The driving voltage of the SiC MOSFET should be reduced, but it cannot be lower than the recommended driving voltage (18 V). driving voltage and gate resistance during different switching stages.It can not only suppress the turn-on overcurrent and turn-off overvoltage but can also avoid serious switching loss.

Parameters Design of the Proposed Gate Driver
Figure 4 shows the structure of the proposed drive circuit.S1-S4 are used to control the level of the driving voltage, and SA1 and SA2 are used to control the values of the gate resistance.RG3 and RG4 are smaller gate resistors, and RG5 and RG6 are larger gate resistors.The waveforms of the signals S1-S4 and SA1-SA2, gate-source voltage  , drain current  , drain-source voltage  , and freewheeling diode D voltage  of the novel drive circuit are shown in Figure 5.In order to suppress the overcurrent and overvoltage of SiC MOSFETs and avoid a serious increase in switching loss at the same time, the proposed gate driver needs to meet the following requirements: 1) Turn-on delay and current-rising stages.In order to achieve a faster turn-on speed to reduce turnon loss during these two stages, the gate resistance should be set as small as possible and the driving voltage during the two stages should be higher than normal, but the driving voltage cannot exceed the gate-source positive safety voltage (25V) of SiC MOSFET.
2) Turn-on overcurrent and current-oscillating stages.In order to reduce the d /dt, a larger gate resistance should be adopted during these two stages.The driving voltage of the SiC MOSFET should be reduced, but it cannot be lower than the recommended driving voltage (18 V).In order to suppress the overcurrent and overvoltage of SiC MOSFETs and avoid a serious increase in switching loss at the same time, the proposed gate driver needs to meet the following requirements: 1) Turn-on delay and current-rising stages.In order to achieve a faster turn-on speed to reduce turn-on loss during these two stages, the gate resistance should be set as small as possible and the driving voltage during the two stages should be higher than normal, but the driving voltage cannot exceed the gate-source positive safety voltage (25V) of SiC MOSFET.
2) Turn-on overcurrent and current-oscillating stages.In order to reduce the dv DS /dt, a larger gate resistance should be adopted during these two stages.The driving voltage of the SiC MOSFET should be reduced, but it cannot be lower than the recommended driving voltage (18 V).
3) Turn-off delay and voltage-rising stages.When compared with the traditional gate driver with 0 V turn-off voltage, the turn-off speed is faster when the turn-off voltage is negative.In order to achieve a Energies 2019, 12, 1640 6 of 14 faster turn-off speed to reduce turn-off loss during these two stags, the turn-off voltage can be set to a negative voltage (<0 V, >−10 V), and a small gate resistance should be set.
4) Turn-off overvoltage and voltage-oscillating stages.In order to reduce di D /dt, the turn-off driving voltage no longer uses a negative voltage and a larger gate resistance should be set.

Working Principle of the Proposed Gate Driving Circuit
The working modes of the proposed driving circuit are as follows.Table 1 shows the driving voltage and gate resistor in each mode of the proposed driving circuit.
We assume that the driving circuit is in a stable state before time t 1 , S 3 and S 4 are in the on-state, the gate resistance is R G1 + R G4 + R G6 , Q 1 is in the off-state, and the freewheeling diode D freewheels.
Mode 1: At time t 1 , S 1 , S 4 , and S A1 are turned on and S 3 is turned off.The driving signal v P of Q 1 changes from 0 V to V GS , and the gate resistance becomes R G1 + R G4 .The smaller the R G4 , the faster the speed of these two stages.Therefore, R G4 can choose a 10 Ω resistor.At time t 3 , i D , rises to I o , freewheeling diode D turns off, and this mode ends.The equivalent circuit of this mode is shown in Figure 6a.In this mode, the turn-on delay time and current-rise time of the Q 1 are shortened.
Mode 2: At time t 3 , S 1 and S 2 are turned on, S 4 and S A1 are turned off; the driving signal v P of Q 1 becomes V GS + V SS , and the gate resistance becomes R G1 + R G3 + R G5 .During these two stages, V GS + V SS depends on V GS and V SS and cannot be changed.The larger the R G5 , the lower the turn-on overcurrent of Q 1 .However, the turn-off process does not end completely, and the turn-off loss will increase as R G5 increases.Therefore, the value of R G5 should be a tradeoff between the turn-on overcurrent and turn-on loss.At time t 6 , the turn-off signal of Q 1 arrives and this mode ends.The equivalent circuit is shown in Figure 6b.In this mode, the turn-on overcurrent and oscillation of Q 1 are suppressed.
Mode 3: S 2 , S 3 , and S A3 are turned on and S 1 is turned off at time t 6 .The driving signal v P of Q 1 changes from 0 V to V SS , and the gate resistance becomes R G1 + R G3 .The smaller the R G3 , the faster the speed of these two stages, and a 10 Ω resistor can be chosen as R G3 .At time t 8 , v DS rises to V DC , freewheeling diode D conducts, and this mode ends.The equivalent circuit of this mode is shown in Figure 6c.In this mode, the turn-off delay time and voltage-rising time of the Q 1 are shortened, and the turn-off loss decreases as a result.
Mode 4: At time t 6 , S 3 and S 4 are turned on, and S 2 and S A3 are turned off.The driving signal v P of Q 1 becomes 0 V, and the gate resistance becomes R G1 + R G4 + R G6 .The larger the R G6 , the lower the turn-off overvoltage of Q 1 .However, the turn-off process does not end completely, the turn-off loss will increase as R G6 increases.Therefore, the value of R G6 should be a tradeoff between the turn-off overvoltage and turn-off loss.At t 9 , the turn-on signal of Q 1 arrives and this mode ends.This mode equivalent circuit is shown in Figure 6d.In this mode, the turn-off overvoltage and oscillation of Q 1 are suppressed.

Experimental Verification
In order to verify the advantages of the gate driving circuit proposed in this paper, a doublepulse test platform based on the proposed gate driver was built.

Design of the Double-Pulse Test Platform
Figure 7 shows the double-pulse test platform based on the proposed gate driver.The doublepulse test platform is composed of a double-pulse circuit, a digital controller and the proposed gate driver.In the double-pulse circuit, the SiC MOSFET and diode are C2M0080120D and C4D20120A produced by Cree.Coaxial shunt produced by T & M Researcher is adopted to ensure the accuracy of current measurement.

Experimental Verification
In order to verify the advantages of the gate driving circuit proposed in this paper, a double-pulse test platform based on the proposed gate driver was built.

Design of the Double-Pulse Test Platform
Figure 7 shows the double-pulse test platform based on the proposed gate driver.The doublepulse test platform is composed of a double-pulse circuit, a digital controller and the proposed gate driver.In the double-pulse circuit, the SiC MOSFET and diode are C2M0080120D and C4D20120A produced by Cree.Coaxial shunt produced by T & M Researcher is adopted to ensure the accuracy of current measurement.Considering that the maximum turn-on driving voltage of the SiC MOSFET is 25 V and the maximum turn-off driving voltage is −10 V, the recommended driving voltage is 20 V to −5 V. Therefore, the proposed drive circuit has a VGS of 24 V and a VSS of −5 V.This not only meets the requirements of the proposed driver, but also ensures that the on-state resistance of the SiC MOSFET is small during the conducting stage.In the driving loop, gate parasitic inductance LG, commonsource parasitic inductance LCS, gate-source junction capacitance CGS and external gate resistance RG form an LCR resonant circuit, as shown in Figure 8.The overvoltage and oscillation may occur in the gate-source voltage  .The gate-source voltage  can be calculated according to the Equation ( 6).In order to avoid gate-source voltage oscillation, the external gate resistance RG needs to satisfy inequality (7).The sum of LCS and LG of the double-pulse circuit is approximately 25 nH, CGS of a C2M0080120D is about 1.2 nF.Therefore, 10 Ω resistor is selected for RG3 and RG4 (7) In the proposed gate driver, a larger resistor should be selected for RG5 and RG6 to reduce the overshoot of the SiC MOSFET in Stage 3 and Stage 8.However, the larger RG5 and RG6 are, the larger the switching loss is.Therefore, it is necessary to balance the overshoot and turn-on loss to select RG5 and RG6, a 50 Ω resistor are selected for RG5 and RG6.The driving parameters of the proposed gate diver are shown in Table 2. Considering that the maximum turn-on driving voltage of the SiC MOSFET is 25 V and the maximum turn-off driving voltage is −10 V, the recommended driving voltage is 20 V to −5 V. Therefore, the proposed drive circuit has a V GS of 24 V and a V SS of −5 V.This not only meets the requirements of the proposed driver, but also ensures that the on-state resistance of the SiC MOSFET is small during the conducting stage.In the driving loop, gate parasitic inductance L G , common-source parasitic inductance L CS , gate-source junction capacitance C GS and external gate resistance R G form an LCR resonant circuit, as shown in Figure 8.The overvoltage and oscillation may occur in the gate-source voltage v GS .The gate-source voltage v GS can be calculated according to the Equation ( 6).Considering that the maximum turn-on driving voltage of the SiC MOSFET is 25 V and the maximum turn-off driving voltage is −10 V, the recommended driving voltage is 20 V to −5 V. Therefore, the proposed drive circuit has a VGS of 24 V and a VSS of −5 V.This not only meets the requirements of the proposed driver, but also ensures that the on-state resistance of the SiC MOSFET is small during the conducting stage.In the driving loop, gate parasitic inductance LG, commonsource parasitic inductance LCS, gate-source junction capacitance CGS and external gate resistance RG form an LCR resonant circuit, as shown in Figure 8.The overvoltage and oscillation may occur in the gate-source voltage  .The gate-source voltage  can be calculated according to the Equation (6).In order to avoid gate-source voltage oscillation, the external gate resistance RG needs to satisfy inequality (7).The sum of LCS and LG of the double-pulse circuit is approximately 25 nH, CGS of a C2M0080120D is about 1.2 nF.Therefore, 10 Ω resistor is selected for RG3 and RG4 (7) In the proposed gate driver, a larger resistor should be selected for RG5 and RG6 to reduce the overshoot of the SiC MOSFET in Stage 3 and Stage 8.However, the larger RG5 and RG6 are, the larger the switching loss is.Therefore, it is necessary to balance the overshoot and turn-on loss to select RG5 and RG6, a 50 Ω resistor are selected for RG5 and RG6.The driving parameters of the proposed gate diver are shown in Table 2.In order to avoid gate-source voltage oscillation, the external gate resistance R G needs to satisfy inequality (7).The sum of L CS and L G of the double-pulse circuit is approximately 25 nH, C GS of a C2M0080120D is about 1.2 nF.Therefore, 10 Ω resistor is selected for In the proposed gate driver, a larger resistor should be selected for R G5 and R G6 to reduce the overshoot of the SiC MOSFET in Stage 3 and Stage 8.However, the larger R G5 and R G6 are, the larger the switching loss is.Therefore, it is necessary to balance the overshoot and turn-on loss to select R G5 and R G6 , a 50 Ω resistor are selected for R G5 and R G6 .The driving parameters of the proposed gate diver are shown in Table 2.
In order to verify the effectiveness of the proposed gate driver, this paper gives the results of a comparative test performed between the proposed gate driver and traditional gate drivers.The traditional gate driver used different driving parameters, as shown in Table 3.
The PCB of the proposed gate driver is shown in Figure 9. Six nonisolated driver chips (UCC27531) produced by TI were selected as S 1 -S 4 and S A1 -S A2 .Two isolation chips (ISO7230M) produced by TI are used to ensure effective isolation between the control circuit and the main power circuit.V GS and −V SS are provided by the auxiliary power WRE0512S-3WR2 and WRF0505S-3WR2, respectively.To reduce the space, the SMD resistors of 0603 package are selected as gate resistance.The driving signals for S 1 -S 4 and S A1 -S A2 are provided by a TMS320F28335 digital signal processor.In order to verify the effectiveness of the proposed gate driver, this paper gives the results of a comparative test performed between the proposed gate driver and traditional gate drivers.The traditional gate driver used different driving parameters, as shown in Table 3.The PCB of the proposed gate driver is shown in Figure 9. Six nonisolated driver chips (UCC27531) produced by TI were selected as S1-S4 and SA1-SA2.Two isolation chips (ISO7230M) produced by TI are used to ensure effective isolation between the control circuit and the main power circuit.VGS and −VSS are provided by the auxiliary power WRE0512S-3WR2 and WRF0505S-3WR2, respectively.To reduce the space, the SMD resistors of 0603 package are selected as gate resistance.The driving signals for S1-S4 and SA1-SA2 are provided by a TMS320F28335 digital signal processor.When using the proposed gate driver, the time of Stage 1-2 and Stage 6-7 must be solved to determine the switching points in Figure 5.The time of these four stages can be obtained by the LTspice simulation or the datasheet of the SiC MOSFET provided by the manufacturer.However, the double-pulse test is the most accurate method to solve the time.This paper used the double-pulse test to solve the time of these four stages.In order to achieve faster switching speed, the proposed gate driver and traditional gate driver have the same driving parameters during these four stages.When using the proposed gate driver, the time of Stage 1-2 and Stage 6-7 must be solved to determine the switching points in Figure 5.The time of these four stages can be obtained by the LTspice simulation or the datasheet of the SiC MOSFET provided by the manufacturer.However, the double-pulse test is the most accurate method to solve the time.This paper used the double-pulse test to solve the time of these four stages.In order to achieve faster switching speed, the proposed gate driver and traditional gate driver have the same driving parameters during these four stages.
Energies 2019, 12, 1640 10 of 14 Therefore, when the double-pulse test adopts the traditional gate driver, the time of these four stages can be easily measured.Table 4 gives the time of the four stages with traditional driver 1 .Table 5 shows the test equipment used for the double-pulse test platform.

Test Results of the Turn-on Process
The turn-on waveforms of the gate-source voltage v GS , drain current i D , drain-source voltage v DS , and switching loss based on different gate drivers are given in Figure 10, and the experiment was conducted under an input voltage of 600 V and an output current of 21 A.
Energies 2019, 03, x FOR PEER REVIEW 10 of 14 Therefore, when the double-pulse test adopts the traditional gate driver, the time of these four stages can be easily measured.Table 4 gives the time of the four stages with traditional driver 1 .Table 5 shows the test equipment used for the double-pulse test platform.

Test Results of the Turn-on Process
The turn-on waveforms of the gate-source voltage vGS, drain current  , drain-source voltage  , and switching loss based on different gate drivers are given in Figure 10, and the experiment was conducted under an input voltage of 600 V and an output current of 21 A. The experimental comparison results of the turn-on process are shown in Table 6.The experimental comparison results of the turn-on process are shown in Table 6.   Figure 12 shows the experimental test results with different gate drivers for respective input voltage and output current of 400 V/11 A, 500 V/16 A, 600 V/21 A. According to the test results, the traditional gate driver with the driving parameters 24 V/10 Ω and −5 V/10 Ω has the highest turn-on overcurrent, highest turn-off overvoltage, fastest switching speed, and lowest switching loss.Although the traditional gate driver with driving parameters 19 V/50 Ω and 0 V/50 Ω suppress the turn-on overcurrent and turn-off overvoltage of the SiC MOSFET, the switching loss increases rapidly.
By comparison, the proposed gate driver can suppress the turn-on overcurrent and turn-off overvoltage of the SiC MOSFET effectively and has little effect on switching loss.

Conclusions
This paper analyzed the causes of the turn-on overshoot current, turn-off overvoltage, and switching oscillation of SiC MOSFETs.The analysis results verified that the turn-on overcurrent and turn-off overvoltage can be suppressed by reducing the amplitude of the driving voltage vP and increasing the external gate resistance.Based on the theoretical analysis, this paper proposed a novel gate driver based on the variable driving voltage and variable gate resistance topology for SiC MOSFETs.The proposed gate driver was tested under different working conditions to verify its suppression effect on the turn-on overcurrent and turn-off overvoltage of SiC MOSFETs.The By comparison, the proposed gate driver can suppress turn-on overcurrent and turn-off overvoltage of the SiC MOSFET effectively and has little effect on switching loss.

Conclusions
This paper analyzed the causes of the turn-on overshoot current, turn-off overvoltage, and switching oscillation of SiC MOSFETs.The analysis results verified that the turn-on overcurrent and turn-off overvoltage can be suppressed by reducing the amplitude of the driving voltage v P and increasing the external gate resistance.Based on the theoretical analysis, this paper proposed a novel gate driver based on the variable driving voltage and variable gate resistance topology for SiC MOSFETs.The proposed gate driver was tested under different working conditions to verify its suppression effect on the turn-on overcurrent and turn-off overvoltage of SiC MOSFETs.The experimental test results show that the proposed gate driver can suppress the turn-on overcurrent and turn-off overvoltage of SiC MOSFETs effectively and has little effect on switching loss.
The proposed gate driver can effectively suppress the overvoltage and overcurrent of SiC MOSFETs when compared with the conventional gate drivers.However, it requires five additional digital signals to drive S 1 -S 4 and S A1 -S A2 .In the future, the manufacturer of the gate driver can integrate the proposed gate drive circuit into an integrated gate driver chip to achieve simple control of the proposed gate driver.This is of great significance to promote the wide use of SiC MOSFETs in high-frequency applications.

Figure 1 .
Figure 1.Double-pulse circuit considering the parasitic elements.

Figure 2
Figure 2 shows the switching waveforms of Q1: the gate-source voltage  , the drain current  , the drain-source voltage  , and the switching waveform of freewheeling diode voltage  .The switching waveforms of a switching cycle can be divided into ten stages.The turn-on transient includes: Stage 1 (turn-on delay stage), Stage 2 (current-rising stage), Stage 3 (turn-on overcurrent stage), and Stage 4 (current-oscillating stage).The turn-off transient includes: Stage 6 (turn-off delay stage), Stage 7 (voltage-rising stage), Stage 8 (turn-off overvoltage stage), and Stage 9 (voltage-oscillating stage).Stage 5 and Stage 10 are the stable stages after the switching transient.Since this paper mainly

Figure 1 .
Figure 1.Double-pulse circuit considering the parasitic elements.

Figure 2 .
Figure 2. Switching waveforms of a SiC MOSFET and a freewheeling diode.

Figure 4 .
Figure 4. Double-pulse circuit based on the proposed gate driver.

Figure 5 .
Figure 5. Switching waveforms based on the proposed gate driver.

Figure 4 .
Figure 4. Double-pulse circuit based on the proposed gate driver.

Figure 4 .
Figure 4. Double-pulse circuit based on the proposed gate driver.

Figure 5 .
Figure 5. Switching waveforms based on the proposed gate driver.

Figure 5 .
Figure 5. Switching waveforms based on the proposed gate driver.

Figure 7 .
Figure 7. Double-pulse test platform based on the proposed gate driver.

Figure 7 .
Figure 7. Double-pulse test platform based on the proposed gate driver.

Figure 7 .
Figure 7. Double-pulse test platform based on the proposed gate driver.

Figure 9 .
Figure 9. Printed circuit board (PCB) of the proposed gate driver.

Figure 9 .
Figure 9. Printed circuit board (PCB) of the proposed gate driver.

Figure 10 .
Figure 10.Switching waveforms based on different gate drivers: (a) Turn-on current waveforms, (b) Turn-on voltage waveforms, (c) Gate driving waveforms, and (d) Turn-on loss waveforms.

Figure 10 .
Figure 10.Switching waveforms based on different gate drivers: (a) Turn-on current waveforms, (b) Turn-on voltage waveforms, (c) Gate driving waveforms, and (d) Turn-on loss waveforms.

Figure 12
Figure12shows the experimental test results with different gate drivers for respective input voltage and output current of 400 V/11 A, 500 V/16 A, 600 V/21 A. According to the test results, the traditional gate driver with the driving parameters 24 V/10 Ω and −5 V/10 Ω has the highest turn-on overcurrent, highest turn-off overvoltage, fastest switching speed, and lowest switching loss.Although the traditional gate driver with driving parameters 19 V/50 Ω and 0 V/50 Ω can suppress the turn-on overcurrent and turn-off overvoltage of the SiC MOSFET, the switching loss increases rapidly.

Figure 12 .
Figure 12.Experimental results under the different working conditions: (a) Overshoot current, (b) Overshoot voltage, (c) Turn-on loss, and (d) Turn-off loss.

Figure 12 .
Figure 12.Experimental results under the different working conditions: (a) Overshoot current, (b) Overshoot voltage, (c) Turn-on loss, and (d) Turn-off loss.
Stage 8 (turn-off overvoltage stage), and Stage 9 (voltage-oscillating stage).Stage 5 and Stage 10 are the stable stages after the switching transient.Since this paper mainly analyzes the causes of the overcurrent and overvoltage of SiC MOSFETs, the section only analyzes Stage 3, Stage 4, Stage 8, and Stage 9 in detail.

Table 1 .
Driving voltage and gate resistor in each mode.

Table 2 .
Driving parameters of the proposed gate diver.

Table 3 .
Driving parameters of traditional gate drivers.

Table 2 .
Driving parameters of the proposed gate diver.

Table 3 .
Driving parameters of traditional gate drivers.

Table 5 .
Test equipment for the double-pulse test platform.

Table 5 .
Test equipment for the double-pulse test platform.

Table 7 .
Experimental results of turn-off process based on different gate drivers.

Table 7 .
Experimental results of turn-off process based on different gate drivers.