A Family of Bidirectional DC–DC Converters for Battery Storage System with High Voltage Gain

: In low power energy storage systems, to match the voltage levels of the low-voltage battery side and high-voltage direct current (DC) bus, a high voltage gain converter with bidirectional operation is required. In this system, the cost effectiveness of the design is a critical factor; therefore, the system should be designed using a small number of components. This paper proposes a set of bidirectional converters with high voltage gain range based on the integration of the boost converter with a ´Cuk converter, single ended primary inductor converter (Sepic), and buck-boost converter. The proposed converters consist of a small number of components with a high voltage gain ratio. Detailed comparisons are made with respect to the operating mode, number of components, voltage, and current ripple and efﬁciency. The efﬁciency of proposed converters are higher than the conventional converters in entire power range, and 6% higher efﬁciency can be achieved in large duty cycle by calculating loss analysis. To verify performances of the proposed converters, three 200-W prototypes of the converters are developed under the same experimental conditions. The results revealed that converter I exhibits the highest efﬁciency in the boost mode (92%) and buck mode (92.2%). The experimental results are shown to verify the feasibility and performances of the set of converters.


Introduction
Energy storage systems (ESS) with DC-DC converters operating in bidirectional is indispensable in microgrids, electric vehicles (EVs), and transportation systems based on the renewable energy [1,2].Bidirectional DC-DC converters are essential for the transfer and conversion of the electrical energy of the storage units, which operate the charge and discharge processes.Hence, bidirectional converters are the vital elements for the realization of efficient energy management.In general, the voltage of the storage units is relatively low due to safety problems.Therefore, a converter operating in bidirectional is available to connect the storage elements to the dc bus [3,4].The realization of highly efficient converters with large conversion ratios and high power densities is a significant challenge in the power electronics field.
With respect to the high voltage conversion ratio bi-direction DC-DC converters, they can be divided into isolated converters and non-isolated converters.According to the conventional bidirectional converters with transformer [5][6][7], this type of converter benefits from a simple structure and easy to operate.However, the leakage inductor loss due to the high-frequency transformer results in a low converter efficiency.For most transformerless bidirectional converters [8][9][10][11][12][13], although the high frequency loss is lower, the voltage gain ratio is relatively low.In addition, there are more active components in several non-isolated converters.For example, the Ćuk converter, SEPIC converter, and Zeta converter can also be changed into double direction form; however, the inherent structure of structure of these converters determined to be inefficient at high duty cycles [14][15][16].In references [17] and [18][19][20], DC-DC converters operating in bidirectional with high conversion ratio are proposed.Practically, there have more power switches in these converters which led to increasing the conduction losses and the cost efficiency, lead to decrease the efficiency.In reference [21], a novel buck-boost converter without transformer is proposed.The converter has only one power switch is utilized.However, for this converter, three inductors are applied to the topology, which may result in a low power density.In reference [22], a novel quasi-Z-source DC-DC converter is presented for EVs, which attained a high voltage conversion ratio and low voltage stress across the power switches.However, the ripple rate on the inductance is relatively high.
To overcome these problems, converters based on the integration of the boost converter with the Ćuk, Sepic, and buck-boost converters are presented in [23][24][25].This attained a high voltage gain ratio and low voltage stress across the power switches.However, the converters operate only in unidirectional mode, and furthermore, the voltage and current stresses on the switches are not analyzed in detail.Therefore, a set of DC-DC converters operating in bi-direction with high voltage conversion ratio based on [23][24][25] are proposed in this paper.
In order to analyze the proposed converters, detailed comparisons are made with respect to the operating mode, number of components, voltage and current ripple and efficiency.The voltage ripple of the proposed converters is relatively low, which increases design flexibility for the passive component.In addition, the loss and efficiency of the proposed converters and the conventional converters are compared by calculation under the same conditions.The calculation results shown that the efficiency of proposed converters is higher than the conventional converters in the entire power range, especially in large duty cycle, because the proposed converter is less affected by parasitic elements.For experimental validation, three 200-W prototypes are built under the same experimental conditions.The experimental results demonstrate a 92.2% peak efficiency for the buck mode and 92% peak efficiency for the boost mode.

Bidirectional DC-DC Converters with Wide Voltage Conversion Ratio
The structure of the proposed converters are presented from Figures 1-3.The proposed converters consist of three power switches Q1, Q2, and Q3; capacitors C1, C2, and C3 (I and II), in addition, there are two inductors L1 and L2 in these converters.The proposed converters are analyzed based on the assumption that the converters operate in continuous conduction mode (CCM), and that all the components are analyzed in the ideal condition.

Construction of the Converter I
The main theoretical waveforms of the proposed converter I in CCM are presented in Figure 4a,b, and the steady-state analyses with respect to the switching states of the converter I are shown as follows.
(1) Boost mode of the converter I: When the converter I operates in the boost mode, the power flows from the battery side to the dc bus side.In this mode, the switch Q1 is shown as the main power switch, and Q2 and Q3 are shown as the synchronous rectifiers.The gate signal of Q1 is complementary to Q2 and Q3; thus, d1 = 1 − d2 = 1 − d3 = dBoost.The topological states are described in Figure 5a,b.
[t0-t1]: When the circuit operates in this case.Switch Q1 is turned ON, and switches Q2 and Q3 are turned OFF, as described in Figure 5a, the battery voltage flows through inductor L1, while inductor L2 and C3 are charging through C2.With reference to Figure 5a, in addition, by applying the Kirchhoff voltage law (KVL) and Kirchhoff current law (KCL) to the circuit, the formulas below are obtained for this state.
where UL1, UL2 represent the voltage on the inductors.UC1, UC2 and UC3 are the voltage on the capacitors.Uhigh and Ulow are shown as the voltage on the DC bus side and battery side.Ihigh and Ilow are shown as the current on the DC bus side and battery side.These symbols are applicable to all of the converters in this paper.

Construction of the Converter I
The main theoretical waveforms of the proposed converter I in CCM are presented in Figure 4a,b, and the steady-state analyses with respect to the switching states of the converter I are shown as follows.
(1) Boost mode of the converter I: When the converter I operates in the boost mode, the power flows from the battery side to the dc bus side.In this mode, the switch Q1 is shown as the main power switch, and Q2 and Q3 are shown as the synchronous rectifiers.The gate signal of Q1 is complementary to Q2 and Q3; thus, d1 = 1 − d2 = 1 − d3 = dBoost.The topological states are described in Figure 5a,b.
[t0-t1]: When the circuit operates in this case.Switch Q1 is turned ON, and switches Q2 and Q3 are turned OFF, as described in Figure 5a, the battery voltage flows through inductor L1, while inductor L2 and C3 are charging through C2.With reference to Figure 5a, in addition, by applying the Kirchhoff voltage law (KVL) and Kirchhoff current law (KCL) to the circuit, the formulas below are obtained for this state.
where UL1, UL2 represent the voltage on the inductors.UC1, UC2 and UC3 are the voltage on the capacitors.Uhigh and Ulow are shown as the voltage on the DC bus side and battery side.Ihigh and Ilow are shown as the current on the DC bus side and battery side.These symbols are applicable to all of the converters in this paper.

Construction of the Converter I
The main theoretical waveforms of the proposed converter I in CCM are presented in Figure 4a,b, and the steady-state analyses with respect to the switching states of the converter I are shown as follows.
Energies 2019, 12, x FOR PEER REVIEW 4 of 21 [t1-t2]: By contrast, the second topological state is depicted in Figure 5b.In this case, the input voltage and the indictor L1 are discharged to capacitor C2 in series.Moreover, inductor L2 is also discharged to C1 through Q3, and C2 is charged through Q2.The output voltage is boosting by connecting the capacitors C1 and C2 in stack.With reference to Figure 5b, by applying the same principle, the formulas below are derived for this state.(1) Boost mode of the converter I: When the converter I operates in the boost mode, the power flows from the battery side to the dc bus side.In this mode, the switch Q 1 is shown as the main power switch, and Q 2 and Q 3 are shown as the synchronous rectifiers.The gate signal of Q 1 is complementary to Q 2 and Q 3 ; thus,   - By employing the volt-second balance theory of inductors L1 and L2 on the basis of ( 1) and ( 3), the voltage gain rate MBoost of suggested converter I in CCM can be expressed as Moreover, the voltage stresses across capacitors C1 and C2 can be written as [t 0 -t 1 ]: When the circuit operates in this case.Switch Q 1 is turned ON, and switches Q 2 and Q 3 are turned OFF, as described in Figure 5a, the battery voltage flows through inductor L 1 , while inductor L 2 and C 3 are charging through C 2 .With reference to Figure 5a, in addition, by applying the Kirchhoff voltage law (KVL) and Kirchhoff current law (KCL) to the circuit, the formulas below are obtained for this state.
where U L1 , U L2 represent the voltage on the inductors.U C1 , U C2 and U C3 are the voltage on the capacitors.U high and U low are shown as the voltage on the DC bus side and battery side.I high and I low are shown as the current on the DC bus side and battery side.These symbols are applicable to all of the converters in this paper.
[t 1 -t 2 ]: By contrast, the second topological state is depicted in Figure 5b.In this case, the input voltage and the indictor L 1 are discharged to capacitor C 2 in series.Moreover, inductor L 2 is also discharged to C 1 through Q 3 , and C 2 is charged through Q 2 .The output voltage is boosting by connecting the capacitors C 1 and C 2 in stack.With reference to Figure 5b, by applying the same principle, the formulas below are derived for this state.
By employing the volt-second balance theory of inductors L 1 and L 2 on the basis of (1) and (3), the voltage gain rate M Boost of suggested converter I in CCM can be expressed as Moreover, the voltage stresses across capacitors C 1 and C 2 can be written as By employing the ampere-second balance law to the capacitors on the basis of Equation (2) and Equation (4), the average value of the inductor currents I L1 and I L2 can be achieved as (2) Buck mode of the converter I: When the proposed converter I is applied to the buck mode, this is reverse to the boost mode, in which the gate signal of Q 1 is complementary to Q 2 and Q 3 ; thus, The topological stages are depicted in Figure 6a,b.
topological stages are depicted in Figure 6a,b.
[t0-t1]: When Q1 is turned OFF, and Q2 and Q3 are turned ON.The switching state is presented in Figure 6a.As for this state, L1, L2, and C3 are charged by C1 and C2, respectively, through Q2 and Q3.The following formulas are derived for this state.[t1-t2]: In this state, switching state is opposed to previous operation.The switching state is presented in Figure 6b.In this case, C3 and L2 are in series connection to charge C2 by Q1.Moreover, L1 also discharges to C0 through Q1, on the basis of Figure 6b.The formulas below are then calculated for this case.

BUCK MODE
-- [t 0 -t 1 ]: When Q 1 is turned OFF, and Q 2 and Q 3 are turned ON.The switching state is presented in Figure 6a.As for this state, L 1 , L 2 , and C 3 are charged by C 1 and C 2 , respectively, through Q 2 and Q 3 .The following formulas are derived for this state.
[t 1 -t 2 ]: In this state, switching state is opposed to previous operation.The switching state is presented in Figure 6b.In this case, C 3 and L 2 are in series connection to charge C 2 by Q 1 .Moreover, L 1 also discharges to C 0 through Q 1 , on the basis of Figure 6b.The formulas below are then calculated for this case.
Taking into account the volt-second balance law on L 1 and L 2 according to Equation (8) and Equation (10), the boost conversion M Boost of the proposed converter I in CCM can be obtained as Energies 2019, 12, 1289 Moreover, it is concluded that the capacitor voltage can be deduced as Using the ampere-second balance law of capacitors with Equation ( 9) and Equation ( 11), the average inductor currents I L1 and I L2 of inductors L 1 and L 2 can be obtained as (3) Voltage and current stresses of the power switches (converter I): Voltage stress across the power switches: In accordance with the above analysis, as shown in Figures 5 and 6.In addition, by employing the Kirchhoff voltage law (KVL) to the switches, it can be derived that.
By using above analysis and the Kirchhoff voltage law (KVL) to the switches, the voltage stress on the switches can be obtained as

Construction of Presented Converter II
The main theoretical waveforms of the converter II in CCM are identical with the converter I.The steady-state analyses with respect to the operating direction of the converter II are shown as below.
(1) Boost mode of the converter II: Similar to converter I, converter II also has two modes in the boost mode.The operating conditions of the switches are the same as those of converter I. Detailed analysis is presented in [23], when the power switch Q 1 is ON, and Q 2 and Q 3 are turned OFF.The symbolic representation is the same as the converter I.In light of Figure 7a, by using the KVL and KCL laws to the circuit, the following equations based on this state can be formed as when the switching state is opposed to previous operation.As shown in Figure 7b.It can be concluded that By using the ampere-second balance law of capacitors with Equations ( 18) and ( 20), the average inductor currents IL1 and IL2 on the inductors L1 and L2 can be expressed as (2) Buck mode of the Converter II: Similar to converter I, converter II also has two modes in the buck mode.The operating conditions of the switches are same as converter I.
[t0-t1]: This operating mode is effective when the power switch Q1 is OFF and Switches Q2 and Q3 are ON.The inductors L1 and L2 are in charging mode while capacitor C3 is discharging.In accordance with Figure 8a, by using the KVL and KCL laws to the circuit, the formulas below are derived for this case By applying the volt-second balance law to L 1 and L 2 according to Equations ( 17) and ( 19), the voltage gain M Boost of the proposed converter II in CCM can be obtained as Moreover, the voltage stresses across capacitors C 1 and C 2 can be expressed as By using the ampere-second balance law of capacitors with Equations ( 18) and ( 20), the average inductor currents I L1 and I L2 on the inductors L 1 and L 2 can be expressed as (2) Buck mode of the Converter II: Similar to converter I, converter II also has two modes in the buck mode.The operating conditions of the switches are same as converter I.
[t 0 -t 1 ]: This operating mode is effective when the power switch Q 1 is OFF and Switches Q 2 and Q 3 are ON.The inductors L 1 and L 2 are in charging mode while capacitor C 3 is discharging.In accordance with Figure 8a, by using the KVL and KCL laws to the circuit, the formulas below are derived for this case Energies  [t1-t2]: The switching state is reverse to the previous state.Both inductors are in discharge mode, and Capacitors C1 and C3 are charged by the current that flows through the inductor L2.Similarly, from Figure 8b, the following equations is derived.
According to Equations ( 24) and ( 26), the voltage conversion ratio MBoost and voltage stresses on the capacitors of the proposed Converter II in CCM can be expressed as ) According to Equations ( 25) and ( 27), average currents IL1 and IL2 on inductors L1 and L2 can be obtained as [t 1 -t 2 ]: The switching state is reverse to the previous state.Both inductors are in discharge mode, and Capacitors C 1 and C 3 are charged by the current that flows through the inductor L 2 .Similarly, from Figure 8b, the following equations is derived.
According to Equations ( 24) and ( 26), the voltage conversion ratio M Boost and voltage stresses on the capacitors of the proposed Converter II in CCM can be expressed as According to Equations ( 25) and ( 27), average currents I L1 and I L2 on inductors L 1 and L 2 can be obtained as (3) Voltage and current stresses of the power switches (converter II): It can be deduced that the voltage and current stress of the power switches about converter II are identical with converter I, which is shown below Energies 2019, 12, 1289 9 of 19

Construction of the Proposed Converter III
The main theoretical waveforms of proposed converter III in CCM are presented in Figure 9a,b, and the steady-state analyses with respect to the operating modes of converter III are shown below.
(2) Buck mode of the converter III: This is reverse to the boost mode, the gate signal of Q1 is complementary to Q2 and Q3; thus, d3 = 1 − d1 = 1 − d2 = dBuck.The topological states are presented in detail in Figure 11a,b.
[t0-t1].When switch Q3 is ON, and Switches Q1 and Q2 are OFF, the switching state is presented in Figure 11a.DC bus voltage is charging the inductors L1 and L2, and the output capacitor Co discharging energy to the load.Consequently, it can be calculated that [t1-t2].In this state, switching state is opposed to previous operation.The equivalent current flow circuit is shown in Figure 11b.The battery voltage, inductors L1 and L2 are discharging energy to the output capacitor Co and the load.Therefore, voltage stresses across inductors L1 and L2 can be expressed as By using the same theory to L1 and L2, the voltage gain can be expressed as (1) Boost mode of the converter III: The switching states are depicted in Figure (2) Buck mode of the converter III: This is reverse to the boost mode, the gate signal of Q1 is complementary to Q2 and Q3; thus, d3 = 1 − d1 = 1 − d2 = dBuck.The topological states are presented in detail in Figure 11a,b.
[t0-t1].When switch Q3 is ON, and Switches Q1 and Q2 are OFF, the switching state is presented in Figure 11a.DC bus voltage is charging the inductors L1 and L2, and the output capacitor Co discharging energy to the load.Consequently, it can be calculated that [t1-t2].In this state, switching state is opposed to previous operation.The equivalent current flow circuit is shown in Figure 11b.The battery voltage, inductors L1 and L2 are discharging energy to the output capacitor Co and the load.Therefore, voltage stresses across inductors L1 and L2 can be expressed as By using the same theory to L1 and L2, the voltage gain can be expressed as When switches Q 1 and Q 2 are turned ON, and switch Q 3 is turned OFF.By the detailed about Reference [24], the voltages stresses across L 1 and L 2 can be expressed as When the switching state is opposed to previous operation.From reference [24], the voltage stresses across L 1 and L 2 can be expressed as Applying the volt-second balance law to L 1 and L 2 , the voltage gain can be expressed as Energies 2019, 12, 1289 10 of 19 According to the switching state as shown in Figure 10a,b, and the KVL.The voltage across Q 1 , Q 2 , and Q 3 can be expressed as Similarly, according to the switching state as shown in Figure 10a,b, in addition to the KCL, the current across Q 1 -Q 3 can be expressed as (2) Buck mode of the converter III: This is reverse to the boost mode, the gate signal of Q 1 is complementary to Q 2 and Q 3 ; thus, The topological states are presented in detail in Figure 11a,b.
According to the switching state of the buck mode, as shown in Figure 11a,b, in addition to the KVL, the voltage stress can be expressed as Similarly, in the light of the switching state of the buck mode, as shown in Figure 11a,b, in addition to the KCL, the current stress can be derived as

Voltage and Current Ripple Calculation of the Proposed Converters
In terms of the conventional Boost converter, it can be concluded that the current ripple (ΔiL) on the inductance is calculated by where f is the switching frequency, and L is the inductance.
In addition, the output voltage ripple (∆vc) can be obtained from the output capacitor.
where R is the output resistance, C is the output capacitance.According to the above analysis, the voltage ripple on the output voltage and current ripple on the inductances L1 and L2 about proposed converter III are equal to the boost converter because of the similar topological states.
As for converter I and II, it can be concluded from the previous analysis, the output capacitors are connected in stack, so the voltage ripple ratio of the converter I and II is half of the boost converter (1/2∆vc).That means converter I and II are easier to select the output capacitor due to the small voltage ripple.
In terms of the current ripple on the inductance, it is equal to the boost converter because of the connectively style for the inductor is the same with the boost converter.[t 0 -t 1 ].When switch Q 3 is ON, and Switches Q 1 and Q 2 are OFF, the switching state is presented in Figure 11a.DC bus voltage is charging the inductors L 1 and L 2 , and the output capacitor C o discharging energy to the load.Consequently, it can be calculated that [t 1 -t 2 ].In this state, switching state is opposed to previous operation.The equivalent current flow circuit is shown in Figure 11b.The battery voltage, inductors L 1 and L 2 are discharging energy to the output capacitor C o and the load.Therefore, voltage stresses across inductors L 1 and L 2 can be expressed as By using the same theory to L 1 and L 2 , the voltage gain can be expressed as According to the switching state of the buck mode, as shown in Figure 11a,b, in addition to the KVL, the voltage stress can be expressed as Energies Similarly, in the light of the switching state of the buck mode, as shown in Figure 11a,b, in addition to the KCL, the current stress can be derived as

Voltage and Current Ripple Calculation of the Proposed Converters
In terms of the conventional Boost converter, it can be concluded that the current ripple (∆i L ) on the inductance is calculated by where f is the switching frequency, and L is the inductance.
In addition, the output voltage ripple (∆v c ) can be obtained from the output capacitor.
where R is the output resistance, C is the output capacitance.According to the above analysis, the voltage ripple on the output voltage and current ripple on the inductances L 1 and L 2 about proposed converter III are equal to the boost converter because of the similar topological states.
As for converter I and II, it can be concluded from the previous analysis, the output capacitors are connected in stack, so the voltage ripple ratio of the converter I and II is half of the boost converter (1/2∆v c ).That means converter I and II are easier to select the output capacitor due to the small voltage ripple.
In terms of the current ripple on the inductance, it is equal to the boost converter because of the connectively style for the inductor is the same with the boost converter.

Comparisons with Conventional Converters
In general, the losses of the inductor, capacitor, and switch cause the parasitic effects on the converter.In these components, the inductor parasitic resistance has the greatest influence on the converter voltage conversion ratio.Therefore, when considering the influence of the inductance parasitic resistance, the voltage gain ratio of the conventional converter, and the proposed converters can be expressed as follows which D is the duty cycle, and r l represent as the inductor parasitic resistance, R is the load resistance.These three equations are derived by applying the volt-second balance law to inductors, if R/r l is set to 0.01, the voltage gain ratio can be obtained under different duty cycle.
The comparison between the voltage conversion ratio and duty cycle of the conventional converters and the proposed converters are shown in Figure 12.It can be seen that when considering the influence of parasitic components, voltage gain ratio sharply decrease at large duty cycle.However, under the same duty cycle, the voltage gain ratio of the proposed converters is higher than conventional converters.Therefore, under large duty cycle, the proposed converters have a better step-up voltage performance than the conventional converters. resistance.
These three equations are derived by applying the volt-second balance law to inductors, if R/rl is set to 0.01, the voltage gain ratio can be obtained under different duty cycle.
The comparison between the voltage conversion ratio and duty cycle of the conventional converters and the proposed converters are shown in Figure 12.It can be seen that when considering the influence of parasitic components, voltage gain ratio sharply decrease at large duty cycle.However, under the same duty cycle, the voltage gain ratio of the proposed converters is higher than conventional converters.Therefore, under large duty cycle, the proposed converters have a better step-up voltage performance than the conventional converters.

Efficiency and Power Loss Calculation
In order to compare the efficiency of the proposed converters with the traditional converters, the losses of the converters can be calculated by using the actual parameters of the components.The system efficiency can be attained by calculating the loss distribution.
Conduction and switching losses of the metal oxide semiconductor field effect transistor (MOSFETs) are defined as

Efficiency and Power Loss Calculation
In order to compare the efficiency of the proposed converters with the traditional converters, the losses of the converters can be calculated by using the actual parameters of the components.The system efficiency can be attained by calculating the loss distribution.
Conduction and switching losses of the metal oxide semiconductor field effect transistor (MOSFETs) are defined as where R ds is the conduction resistance, t r and t f represent the rise time and fall time of the switch.The copper loss and the core loss of the inductor can be calculated as where R win is the ac resistance of the windings.k i , α, and β are empirical constants determined by the core material characteristic.k i = 0.33, α = 1.98, and β = 1.64.f, B, and V are operating frequency, flux density and volume of the core [26].By considering the dielectric characteristic of capacitors, the loss of capacitors is given by Equation ( 51), where tan δ(f ) is the dissipation factor of capacitors and I indicate the current stress on the capacitors [26].
Thus, the total loss can be calculated as P T_L = P loss_mos f et + P core_L + P c_L + P loss_cap + P extra_L (52) which P extra_L represent the extra loss of the converters.Based on the above analysis, the efficiency of conventional converters and proposed converters with different duty cycle is calculated and presented in Figure 13.which Pextra_L represent the extra loss of the converters.Based on the above analysis, the efficiency of conventional converters and proposed converters with different duty cycle is calculated and presented in Figure 13.The efficiency comparison between proposed converters and traditional converters are shown in Figure 13.The efficiency of the converters decreases gradually with the increase of the duty cycle.It is noted that the efficiency of the traditional converters is lower than efficiency of the proposed converters in the case of a large duty cycle.Under the large duty cycle, due to the influence of parasitic elements, voltage conversion ratio and efficiency about traditional converters is rapidly falling off.It is obtained that efficiency of the proposed converters is 6% higher than the conventional converters when the converters operate in large duty cycle.
From Table 1, each topology has three power switches.With respect to Converter III, the voltage stress on the high voltage side switch is relatively high than Converters I and II.However, Converter III is also suitable for high voltage gain applications because of the input voltage is relatively low compared with the output voltage.In addition, the current stress on the switches are lower than converter I and II.With respect to Converter II, the voltage and current stress on the switches and voltage gain ratio are equal to those of Converter I.However, the input and output are not common ground, which can lead to an extra dv/dt issue between the battery side and dc voltage side.The detailed comparison of proposed converters and conventional converters is also listed in Table 1.The efficiency comparison between proposed converters and traditional converters are shown in Figure 13.The efficiency of the converters decreases gradually with the increase of the duty cycle.It is noted that the efficiency of the traditional converters is lower than efficiency of the proposed converters in the case of a large duty cycle.Under the large duty cycle, due to the influence of parasitic elements, voltage conversion ratio and efficiency about traditional converters is rapidly falling off.It is obtained that efficiency of the proposed converters is 6% higher than the conventional converters when the converters operate in large duty cycle.
From Table 1, each topology has three power switches.With respect to Converter III, the voltage stress on the high voltage side switch is relatively high than Converters I and II.However, Converter III is also suitable for high voltage gain applications because of the input voltage is relatively low compared with the output voltage.In addition, the current stress on the switches are lower than converter I and II.With respect to Converter II, the voltage and current stress on the switches and voltage gain ratio are equal to those of Converter I.However, the input and output are not common ground, which can lead to an extra dv/dt issue between the battery side and dc voltage side.The detailed comparison of proposed converters and conventional converters is also listed in Table 1.
Voltage Ripple 1 Switch voltage stress in Boost mode. 2 Switch voltage stress in Buck mode. 3 Switch voltage stress on Q 1 and Q 2 . 4 Switch voltage stress on Q 3 .

Experimental Results in the Boost/Buck Mode
To verify the theoretical analysis of the proposed converters, three 200-W prototypes are developed in the laboratory, as shown in Figure 14.The parameters of the test prototypes are presented in Table 2.A double loop proportional-integral (PI) control, (inner current control loop and outer voltage control loop), as shown in Figure 15, is applied to the experiment.
Under the test conditions V in = 40 V, V o = 250 V, f s = 25 KHz, and P o = 200 W; experimental results with respect to converter I are presented in Figure 16.
The voltage stress waveform of Q 1 , Q 2 and Q 3 in the boost mode are presented in Figure 16a.It can be seen that the voltage stresses on Q 1 -Q 3 are approximately 150 V, which indicates that the voltage stresses on Q 1 -Q 3 are equal to V high /(1 + D).Under the same situation, Figure 16c shown the inductors current under the boost mode.

Experimental Results in the Boost/Buck Mode
To verify the theoretical analysis of the proposed converters, three 200-W prototypes are developed in the laboratory, as shown in Figure 14.The parameters of the test prototypes are presented in Table 2.A double loop proportional-integral (PI) control, (inner current control loop and outer voltage control loop), as shown in Figure 15, is applied to the experiment.The voltage stress waveform of Q1, Q2 and Q3 in the boost mode are presented in Figure 16a.It can be seen that the voltage stresses on Q1-Q3 are approximately 150 V, which indicates that the voltage stresses on Q1-Q3 are equal to Vhigh/(1 + D).Under the same situation, Figure 16c shown the inductors current under the boost mode.
The voltage stress waveforms of Q2 and Q3, and Q1 in buck mode are presented in Figure 16b.It can be revealed that the voltage stresses on Q1-Q3 are approximately 150 V, which indicates that the voltage stresses on Q1-Q3 are equal to Vhigh/(1 + D).Under the same conditions, Figure 16d shown the inductors current under the buck mode.
According to the previous analysis, in boost mode and buck mode, the current ripple rates of L1 and L2 are lower than those of the converters in [22], which makes it easier to design inductance.
Under the same experimental conditions, Converters II and III are evaluated in regard to the input and output voltages, voltage stress on the switches, and current stress on the inductors.Based on their similar characteristics, Converters I and II have similar waveforms.With respect to Converter III, the results of the experiment are presented in Figure 17.
The voltage stress waveforms of Q1 and Q2, and Q3 in the boost mode are presented in Figure 17a.The voltage stresses on Q1-Q2 are 150 V, which indicates that the voltage stresses on Q1-Q3 are equal to (Vo + Vin)/2.On the other hand, the voltage stress on Q3 is 300 V, which indicates that the voltage stresses on Q3 are equal to Vo + Vin.Under the same situation, Figure 17c shown the inductors current under the boost mode.
The voltage stress waveforms of Q2 and Q3, and Q1 in buck mode are presented in Figure 17b.The voltage stresses on Q1-Q2 are 150 V, which indicates that the voltage stresses on Q1-Q2 are equal to (Vo + Vin)/2.On the contrary, the voltage stress on Q3 is 300 V, which indicates that the voltage stresses on Q3 are equal to Vo + Vin.Under the same conditions, Figure 17d shown the inductors current under the buck mode.
It can be seen that the current ripple rate about inductors L1 and L2 are identical because of the same operating mode.The voltage stress waveforms of Q 2 and Q 3 , and Q 1 in buck mode are presented in Figure 16b.It can be revealed that the voltage stresses on Q 1 -Q 3 are approximately 150 V, which indicates that the voltage stresses on Q 1 -Q 3 are equal to V high /(1 + D).Under the same conditions, Figure 16d shown the inductors current under the buck mode.
According to the previous analysis, in boost mode and buck mode, the current ripple rates of L 1 and L 2 are lower than those of the converters in [22], which makes it easier to design inductance.
Under the same experimental conditions, Converters II and III are evaluated in regard to the input and output voltages, voltage stress on the switches, and current stress on the inductors.Based on their similar characteristics, Converters I and II have similar waveforms.With respect to Converter III, the results of the experiment are presented in Figure 17.
The voltage stress waveforms of Q 1 and Q 2 , and Q 3 in the boost mode are presented in Figure 17a.The voltage stresses on Q 1 -Q 2 are 150 V, which indicates that the voltage stresses on Q 1 -Q 3 are equal to (V o + V in )/2.On the other hand, the voltage stress on Q 3 is 300 V, which indicates that the voltage stresses on Q 3 are equal to V o + V in .Under the same situation, Figure 17c shown the inductors current under the boost mode.
The voltage stress waveforms of Q 2 and Q 3 , and Q 1 in buck mode are presented in Figure 17b.The voltage stresses on Q 1 -Q 2 are 150 V, which indicates that the voltage stresses on Q 1 -Q 2 are equal to (V o + V in )/2.On the contrary, the voltage stress on Q 3 is 300 V, which indicates that the voltage stresses on Q 3 are equal to V o + V in .Under the same conditions, Figure 17d shown the inductors current under the buck mode.
It can be seen that the current ripple rate about inductors L 1 and L 2 are identical because of the same operating mode.

Measured Efficiency Analysis of the Converters
To analyze the performances of the proposed converters, the efficiencies of experimental under different input voltage are presented in Figure 18.From the Figure 18, it can be revealed that the maximum efficiencies of converter I in boost mode and buck mode are 92% and 92.2%, respectively.In addition, converter II has similar efficiency rates with converter I because the two prototypes have identical components count and similar topological states.With respect to Converter III, it exhibits a lower efficiency because the high-voltage stress on the switch.Efficiency comparison between calculated results and experiment results are shown in Figure 19, when the proposed converters operating in boost mode, the calculated efficiency is similar with the experiment results, which confirm the correctness of the formula calculation of Equations ( 48)-( 52) and verify the accuracy of experiment results.In the case of high voltage gain ratio, the experimental results are lower than the calculation results.Because the calculated results are approximate value, and the temperature changes of switches and other components have an influence on the experiment efficiency.However, these changes are ignored in the case of calculation.

Measured Efficiency Analysis of the Converters
To analyze the performances of the proposed converters, the efficiencies of experimental under different input voltage are presented in Figure 18.From the Figure 18, it can be revealed that the maximum efficiencies of converter I in boost mode and buck mode are 92% and 92.2%, respectively.In addition, converter II has similar efficiency rates with converter I because the two prototypes have identical components count and similar topological states.With respect to Converter III, it exhibits a lower efficiency because the high-voltage stress on the switch.

Measured Efficiency Analysis of the Converters
To analyze the performances of the proposed converters, the efficiencies of experimental under different input voltage are presented in Figure 18.From the Figure 18, it can be revealed that the maximum efficiencies of converter I in boost mode and buck mode are 92% and 92.2%, respectively.In addition, converter II has similar efficiency rates with converter I because the two prototypes have identical components count and similar topological states.With respect to Converter III, it exhibits a lower efficiency because the high-voltage stress on the switch.Efficiency comparison between calculated results and experiment results are shown in Figure 19, when the proposed converters operating in boost mode, the calculated efficiency is similar with the experiment results, which confirm the correctness of the formula calculation of Equations ( 48)-( 52) and verify the accuracy of experiment results.In the case of high voltage gain ratio, the experimental results are lower than the calculation results.Because the calculated results are approximate value, and the temperature changes of switches and other components have an influence on the experiment efficiency.However, these changes are ignored in the case of calculation.Efficiency comparison between calculated results and experiment results are shown in Figure 19, when the proposed converters operating in boost mode, the calculated efficiency is similar with the experiment results, which confirm the correctness of the formula calculation of Equations ( 48)-( 52) and verify the accuracy of experiment results.In the case of high voltage gain ratio, the experimental results are lower than the calculation results.Because the calculated results are approximate value, and the temperature changes of switches and other components have an influence on the experiment efficiency.However, these changes are ignored in the case of calculation.

Power Loss Distribution Analysis of Proposed Converters
The power loss analysis are calculated under the experiment condition with Ulow = 120 V, Uhigh = 250 V, and Po = 200 W.When the suggested converters operate in boost mode, the comparison of loss analysis is presented in Figure 20a.According to analyzing results of the power losses distribution, the maximum power loss is calculated as 20.95 W, which is due to Converter III.It can be convinced that the dominant sources of power losses are due to the switching losses, which account for 25%, 26%, and 30% of the total losses, respectively.In case of the presented converters operate in buck mode, the loss distribution is presented in Figure 20b.By analyzing the distribution of power losses, the maximum power loss is found to be 20.4W, which is due to Converter III.It can be maintained that the dominant sources of power losses are due to the switching losses.

Power Loss Distribution Analysis of Proposed Converters
The power loss analysis are calculated under the experiment condition with U low = 120 V, U high = 250 V, and P o = 200 W.When the suggested converters operate in boost mode, the comparison of loss analysis is presented in Figure 20a.According to analyzing results of the power losses distribution, the maximum power loss is calculated as 20.95 W, which is due to Converter III.It can be convinced that the dominant sources of power losses are due to the switching losses, which account for 25%, 26%, and 30% of the total losses, respectively.In case of the presented converters operate in buck mode, the loss distribution is presented in Figure 20b.By analyzing the distribution of power losses, the maximum power loss is found to be 20.4W, which is due to Converter III.It can be maintained that the dominant sources of power losses are due to the switching losses.

Power Loss Distribution Analysis of Proposed Converters
The power loss analysis are calculated under the experiment condition with Ulow = 120 V, Uhigh = 250 V, and Po = 200 W.When the suggested converters operate in boost mode, the comparison of loss analysis is presented in Figure 20a.According to analyzing results of the power losses distribution, the maximum power loss is calculated as 20.95 W, which is due to Converter III.It can be convinced that the dominant sources of power losses are due to the switching losses, which account for 25%, 26%, and 30% of the total losses, respectively.In case of the presented converters operate in buck mode, the loss distribution is presented in Figure 20b.By analyzing the distribution of power losses, the maximum power loss is found to be 20.4W, which is due to Converter III.It can be maintained that the dominant sources of power losses are due to the switching losses.

Conclusions
In this study, three novel bidirectional DC-DC converters without transformers and with high voltage gains are developed.The set of converters benefit from a high voltage conversion ratio in the boost and buck modes.Detailed comparisons are made with respect to the operating mode, number
. The topological states are described in Figure5a,b.

Figure 12 .
Figure 12.Voltage gain ratio comparison between proposed converters and conventional converters with parasitic resistance.

Figure 12 .
Figure 12.Voltage gain ratio comparison between proposed converters and conventional converters with parasitic resistance.

Figure 13 .
Figure 13.Efficiency comparison of the proposed converters and traditional converters.(a) traditional converters; (b) proposed converters.

Figure 13 .
Figure 13.Efficiency comparison of the proposed converters and traditional converters.(a) traditional converters; (b) proposed converters.

Figure 14 .
Figure 14.Experimental setup of proposed Converter I.

Figure 15 .
Figure 15.Bidirectional power flow control strategy of proposed converters.

Q 1 Q 2 Q 3 Figure 14 .
Figure 14.Experimental setup of proposed Converter I.

Figure 14 .
Figure 14.Experimental setup of proposed Converter I.

Figure 16 .
Figure 16.Experimental results: (a) voltage stress across Q 1 -Q 3 in boost mode, (b) voltage stress across Q 1 -Q 3 in buck mode, (c) inductor current in boost mode, and (d) inductor current in buck mode.

Figure 17 .
Figure 17.Experimental results: (a) voltage stress across Q1-Q3 in boost mode, (b) voltage stress across Q1-Q3 in buck mode, (c) inductor current in boost mode, and (d) inductor current in buck mode.

Figure 17 .
Figure 17.Experimental results: (a) voltage stress across Q 1 -Q 3 in boost mode, (b) voltage stress across Q 1 -Q 3 in buck mode, (c) inductor current in boost mode, and (d) inductor current in buck mode.

Figure 17 .
Figure 17.Experimental results: (a) voltage stress across Q1-Q3 in boost mode, (b) voltage stress across Q1-Q3 in buck mode, (c) inductor current in boost mode, and (d) inductor current in buck mode.

Figure 18 .
Figure 18.Efficiencies of proposed converters in boost and buck modes with U high = 250 V, U low = 40-130 V, and P o = 200 W.

Figure 19 .
Figure 19.Efficiency comparison between calculated results and experiment results.

Figure 19 .
Figure 19.Efficiency comparison between calculated results and experiment results.

Figure 20 .
Figure 20.Calculated power loss distributions with U low = 120 V, U high = 250 V, and P o = 200 W: (a) boost mode and (b) buck mode.

Table 1 .
Comparison of proposed converters and conventional converters.

Table 1 .
Comparison of proposed converters and conventional converters.

Table 2 .
Parameters of the test converter.

Table 2 .
Parameters of the test converter.