TRAC : A Thermal Resistance Advanced Calculator for Electronic Packages †

This paper presents a novel simulation tool named thermal resistance advanced calculator (TRAC). Such a tool allows the straightforward definition of a parametric detailed thermal model of electronic packages with Manhattan geometry, in which the key geometrical details and thermal properties can vary in a chosen set. Additionally, it can apply a novel model-order reduction-based approach for the automatic and fast extraction of a parametric compact thermal model of such packages. Furthermore, it is suited to automatically determine the joint electron device engineering council (JEDEC) thermal metrics for any choice of parameters in a negligible amount of time. The tool was validated through the analysis of two families of quad flat packages.


Introduction
In the last two decades many efforts have been made to improve the way semiconductor vendors deliver thermal data of electronic components to their customers.This has led to the introduction of boundary condition independent (BCI) compact thermal models (CTMs) of the components [1].However, nowadays customers prefer to request joint electron device engineering council (JEDEC) thermal metrics [2] to vendors instead of BCI CTMs.Consequently, some vendors have expressed the need for an approach suited to achieve these metrics for any product in the package families they sell in a fully automatic way and in a small amount of time.Unfortunately, each product of a package platform differs from the others for the values of selected geometrical dimensions and thermal properties that can vary in an a-priori known set.
The current Delphi-like approach to the extraction of BCI CTMs does not seem suitable for meeting these needs due to the following reasons:

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Delphi BCI CTMs can only consider fixed values of geometrical dimensions and thermal properties; • often they are not as accurate as requested; • their extraction can be very time-consuming, and most of the effort is spent for coping with boundary conditions (BCs) that are not relevant for the extraction of JEDEC thermal metrics; • they cannot be used for electronic components with multiple heat sources (HSs) [1].
Some of the authors have recently developed novel approaches [3][4][5][6][7][8][9] relying on model-order reduction (MOR) to the extraction of various families of CTMs.For the specific case of parametric CTMs (pCTMs) [4], the proposed MOR-based technique starts from the detailed thermal model (DTM) of an electronic component, some parameters of which (geometrical dimensions and thermal properties) are assumed to vary in a chosen set, either finite or infinite.Then it fully automatically extracts a BCI pCTM, which depends on the assigned set of parameters and ensures a selected level of accuracy.The obtained pCTM does not lose information with respect to the original DTM, since it allows entirely reconstructing the space-time distribution of temperature rise in the modeled electronic component from its few degrees of freedom (DoFs).
The aim of this paper is to extend [10], where a simulation tool for electronic packages, referred to as thermal resistance advanced calculator (TRAC), was presented.TRAC allows a straightforward definition of a steady-state parametric DTM (pDTM) of a package with Manhattan geometry, and is also equipped with the option of using a pCTM extracted from the pDTM.Moreover, it is suited to automatically calculate the JEDEC thermal metrics of any product of the assigned family of packages from the above parametric models in a very low (pDTM) or negligible (pCTM) amount of time.By virtue of such appealing features, TRAC can be particularly helpful for vendors and customers in the semiconductor industry.
The first TRAC release described in [10] was developed to simulate a family of exposed pad (epad) quad flat packages (QFPs), the key parameters of which, namely, the package type and size, the number of leads, the epad size, the die attach material and the die dimensions, were assumed to vary in an assigned set.The improved version proposed here makes use of an advanced variant [9] of the order-reduction algorithm in [4] for deriving the pCTM from the pDTM; additionally, it also allows (i) describing quad flat no-leads packages (QFNs); and (ii) defining a rectangular dissipation region with arbitrary size and position over the die.
The paper is articulated as follows.In Section 2, the thermal metrics and the pDTM of the package families under test are introduced.Section 3 details the extraction of the pCTM.Section 4 discusses the numerical results obtained with both the pDTM and pCTM.Conclusions are then drawn in Section 5.

Parametric Detailed Thermal Model
The steady-state thermal behavior of a family of electronic components with Manhattan geometry can be straightforwardly modeled by assigning:

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a sequence of parallelepipeds of chosen size and position, including the one representing the dissipation region, hereinafter referred to as HS; • the thermal conductivity of all materials; • the BCs.
For the QFPs and QFNs that can be handled by the latest TRAC version, the size and positions of parallelepipeds, as well as the thermal conductivities, correspond to parameters to be selected in a chosen set.A rectangular HS with arbitrary size, position, and dissipated power can be defined on the top surface of the die.
TRAC is suited to automatically compute the JEDEC metrics ϑ JA , Ψ JB , Ψ JCtop , ϑ JB , ϑ JCtop , ϑ JCbottom [2] in 4 ambients, which differ in terms of thermal path followed by the heat generated within the HS to emerge from the die; more specifically: the ambient to evaluate ϑ JCbottom requires a cold plate in intimate contact with the package backside; for the computation of ϑ JCtop the plate is located over the top surface; in the ambient for determining ϑ JB , a cold ring surrounds the package; no cooling systems are exploited in the ambient common to ϑ JA , Ψ JB , Ψ JCtop .In all ambients, the board over which the package is mounted is thermally modeled with a single finely-meshed parallelepiped with a thermal conductivity adjusted to account for the aggregate effect of metal traces and vias, the detailed representation of which would have unnecessarily made the thermal problem much more complex.As shown in Figure 1, the metrics are calculated from the temperatures probed in four positions, namely: (1) the point of the die where the peak ("junction") temperature is reached; (2) the center of the top of the case; (3) the center of the bottom of the case; and (4) at the foot of the package lead half way along the side of the package (QFP) or within 1 mm of the package body (QFN).ϑ JA is computed from (1) and the ambient temperature; Ψ JB from (1) and (4); Ψ JCtop from (1) and (2); ϑ JB from (1) and (4); ϑ JCtop from (1) and (2); ϑ JCbottom from (1) and (3).As far as the metric ϑ JCtop is concerned, a calibrated layer was interposed between the epad and the high-conductivity cold plate to emulate the epad-plate contact resistance.For all other metrics, the heat emerging from the die flows through the low-conductivity board, and the contact resistance epad-board was not accounted for, since it plays a negligible role.
As far as the BCs are concerned, specific values of heat transfer coefficients are applied to all surfaces of any structure (i.e., package and ambient) under test for each ambient; such values were preliminarily calibrated by comparing the JEDEC metrics simulated with commercial numerical programs with the experimental counterparts (see e.g., [2] for the measurement procedures) for a broad variety of package families.
For each parallelepiped, a mesh step size can be defined for each axis direction; as a result, a Cartesian mesh is automatically extracted.A finite integration technique (FIT) discretization [11] of the heat conduction problem is then generated in the form where ϑ(p) is the N × 1 vector with the DoFs of the temperature rise distribution, K(p) is the N-order stiffness matrix, G(p) is a N × n power density matrix, p is the p × 1 parameter vector varying in a set P, and P is the n × 1 vector containing the powers P i (with i = 1, . . ., n) dissipated by the n independent HSs in the structure.These equations define the pDTM.

Parametric Compact Thermal Model
From the achieved pDTM, a pCTM can be extracted in a pre-processing stage.An N × q matrix U is determined, which allows approximating the N × 1 temperature rise vector in the form for all p P, in which θ(p) is a q × 1 vector with q « N. The pCTM is derived from Equation (1) using Equation ( 2) and the Galerkin's projection.In this way it results in are approximated by the technique described by some of the Authors in [9], which allows applying a fully generic transformation to the reference package; this improves the merely Cartesian transformation [4] adopted for the previous TRAC version presented in [10].This system of equations, defining the pCTM, has formally the same structure of the system of equations defining the pDTM, but benefits from a significantly reduced complexity since q « N.Such a pCTM is updated at each iteration of the parametric MOR method, as in Algorithm 1.The iterations are stopped when, for novel values of the parameter vector p, the relative residual ξ does not exceed the assigned value Ξ, so that the pCTM does not vary any longer.In Algorithm 1, at step 1, the elements of p P are chosen equal to the values of the parameters defining the specimen in the family of packages for which the JEDEC thermal metrics must be computed.This strategy minimizes the time needed to evaluate the metrics for this case.
At step 2, the relative residual is determined as V being the N-order diagonal matrix with the measures of the N volumes introduced in the FIT discretization.
At step 3, the solution of Equations ( 1) is ensured by a multigrid iterative solver, with a computational complexity linearly increasing with the dimension N of the problem.
At step 4, the U matrix is updated by appending a column orthonormal to the columns of the initial U matrix in the • V norm, such that the columns of the final U matrix span ϑ(p).
At step 5, the updated U matrix is used for reconstructing the pCTM.Exploiting the fact that the last column of U is changed, the update of the pCTM does not require recomputing the whole model.

Numerical Results
The latest TRAC release allows describing and simulating the families of epad QFPs and QFNs, although the tool can be extended to other electronic components with relatively little effort.In particular, the package thickness [low-profile QFP (LQFP) and thin QFP (TQFP) types are considered, the thicknesses of which are 1.4 and 1 mm, respectively] and size, the number of leads, the epad size, the type of glue, the three dimensions of the die, as well as the HS size and position, are defined by twelve (QFP) or fourteen (QFN) parameters.The parameters can be easily selected through a user-friendly graphical interface, which also checks whether the whole parameter set corresponds to a package manufactured by the vendor.Some examples are as follows: the horizontal die dimensions can vary in a continue range between a minimum and a maximum value, the latter fixed by project rules to ensure the attachment between die and epad; the QFP die thickness can be chosen among 100, 280, 375 (value selected for the numerical results shown later), and 580 µm; the glue types used to attach die and pad, which differ in terms of thickness and thermal conductivity (the type with conductivity amounting to 6 W/mK was chosen).
Figure 1 shows the 3-D schematic representation of two specimens of the LQFP and QFN families.157 The inherent symmetry of the packages under test allowed meshing and simulating only a 158 quarter of each structure, thus reducing the computational burden; the missing portions were 159 virtually restored by applying adiabatic BCs (i.e., zero heat flux) over the planes of symmetry.

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A preliminary convergence analysis of the spatial mesh discretization of the constructed pDTMs 161 was performed for chosen packages; more specifically, the calculated thermal metrics were  The inherent symmetry of the packages under test allowed meshing and simulating only a quarter of each structure, thus reducing the computational burden; the missing portions were virtually restored by applying adiabatic BCs (i.e., zero heat flux) over the planes of symmetry.
A preliminary convergence analysis of the spatial mesh discretization of the constructed pDTMs was performed for chosen packages; more specifically, the calculated thermal metrics were monitored by increasing the DoFs until a negligible mesh sensitivity was observed.Then the discretization leading to only <0.1% inaccuracy was selected not to face the computational effort required by extremely fine meshes, this choice being also justified by the higher uncertainty of the experimental data.Figure 2 illustrates the convergence analysis performed for an LQFP with a 10 × 10 mm 2 package, a 4.5 × 4.5 mm 2 epad, and a 2 × 2 mm 2 die; as can be seen, the mesh leading to ϑ JA = 28.87K/W (1.487 × 10 6 DoFs for a quarter of the structure) was chosen to avoid the huge number of DoFs (>50 × 10 6 ) required to obtain a negligibly more accurate ϑ JA value.157 The inherent symmetry of the packages under test allowed meshing and simulating only a 158 quarter of each structure, thus reducing the computational burden; the missing portions were 159 virtually restored by applying adiabatic BCs (i.e., zero heat flux) over the planes of symmetry.

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A preliminary convergence analysis of the spatial mesh discretization of the constructed pDTMs 161 was performed for chosen packages; more specifically, the calculated thermal metrics were 162 monitored by increasing the DoFs until a negligible mesh sensitivity was observed.Then the 163 discretization leading to only <0.1% inaccuracy was selected not to face the computational effort 164 required by extremely fine meshes, this choice being also justified by the higher uncertainty of the 165 experimental data.Figure 2 illustrates the convergence analysis performed for an LQFP with a 10 × 166 10 mm 2 package, a 4.5 × 4.5 mm 2 epad, and a 2 × 2 mm 2 die; as can be seen, the mesh leading to ϑJA =  The accuracy of the JEDEC thermal metrics computed by TRAC using the pDTM is witnessed by a comparison with a finite volume (FV) commercial software.This is shown in Figure 3, which reports the metrics ϑ JA , ϑ JB , and ϑ JCtop (the others were not represented not to overcrowd the graphs) for a 10 × 10 mm 2 LQFP and a 14 × 14 mm 2 TQFP (Figure 3a), as well as for a 6 × 6 mm 2 QFN (Figure 3b).The slight discrepancy between TRAC and the FV software must be attributed: (i) to the different mesh styles of the compared tools; and (ii) to the fineness degree adopted in both of them, which was not extremely high to prevent unnecessarily long CPU times.As can be seen, the thermal metrics decrease with increasing the die size (i.e., the HS size) due to the lower dissipated power density and the enhanced lateral heat spreading.
Energies 2019, 12, x FOR PEER REVIEW 6 of 10 The accuracy of the JEDEC thermal metrics computed by TRAC using the pDTM is witnessed 174 by a comparison with a finite volume (FV) commercial software.This is shown in Figure 3, which 175 reports the metrics ϑJA, ϑJB, and ϑJCtop (the others were not represented not to overcrowd the graphs) 176 for a 10 × 10 mm 2 LQFP and a 14 × 14 mm 2 TQFP (Figure 3a), as well as for a 6 × 6 mm 2 QFN (Figure   Figure 4 reports the metrics ϑ JA and ϑ JCtop as a function of die size for 10 × 10 mm 2 LQFPs and TQFPs commonly sharing a 6 × 6 mm 2 epad.It is inferred that the impact of the package thickness is significant only for ϑ JCtop (for TQFPs, a 25-35% reduction of this metric is observed with respect to LQFPs), since in this case the heat generated in the die flows toward the cold plate placed on the top crossing the whole package; a marginal influence is instead found for all other metrics (including ϑ JA ), where the heat propagates mostly downward.
Lastly, using another available glue type with a reduced thermal conductivity (2 W/mK) for the die-epad attach was found to increase the downward-heat metrics by 15-25%, while ϑ JCtop remains almost unaffected.
Differently from the previous tool version [10], where the power dissipation region was forced to coincide with the whole die, in the latest TRAC release it is also possible to select an HS with arbitrary size and position within the die, thus allowing the representation of more realistic conditions.Figure 5 shows the metric ϑ JA as a function of HS size, the HS being centered in the die (which offers the possibility of meshing and simulating one quarter of the structure), for a 10 × 10 mm 2 LQFP with a 4.5 × 4.5 mm 2 epad and a 2 × 2 mm 2 die; the assigned dissipated power amounts to 1 W regardless of the HS size.As expected, ϑ JA markedly increases with reducing the HS size, which implies a growth in power density.This analysis allows concluding that a correct representation of the HS geometry (which depends on the specific application) is of utmost importance for an accurate evaluation of the thermal metrics of electronic packages.

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Lastly, a pCTM of any of the derived pDTMs, ensuring accuracy better than 0.5% in the 212 reconstruction of the thermal field, was extracted in less than 20 minutes on an iMac with a 3.5 GHz Intel

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Core i7 according to Algorithm 1; the resulting pCTMs enjoy less than 70 DoFs (to be compared with a 214  Lastly, a pCTM of any of the derived pDTMs, ensuring accuracy better than 0.5% in the reconstruction of the thermal field, was extracted in less than 20 min on an iMac with a 3.5 GHz Intel Core i7 according to Algorithm 1; the resulting pCTMs enjoy less than 70 DoFs (to be compared with a few millions for the pDTMs).It is worth noting that the steady-state thermal simulation corresponding to a given set of parameters requires 10-20 s for the pDTM (depending on the package), 30-60 s for the FV commercial software, and less than 0.2 s using the pCTM in TRAC.A comparison of the results from the pDTM and the pCTM is shown in Figure 6 for various QFPs.
few millions for the pDTMs).It is worth noting that the steady-state thermal simulation corresponding to 215 a given set of parameters requires 10-20 seconds for the pDTM (depending on the package), 30-60 seconds 216 for the FV commercial software, and less than 0.2 seconds using the pCTM in TRAC.A comparison of the 217 results from the pDTM and the pCTM is shown in Figure 6 for various QFPs.

Conclusions
In this paper, a tool denoted as TRAC has been presented.TRAC determines the steady-state thermal behavior of electronic packages with Manhattan geometry, the key geometrical and material parameters of which vary in an assigned range.The latest TRAC release allows the straightforward definition of pDTMs, as well as the automatic and fast (about 20 min) extraction of pCTMs in a pre-processing stage, for two families of packages.In addition, it automatically provides the JEDEC thermal metrics corresponding to selected packages, thereby favoring an easy evaluation of the influence of the key parameters (e.g., die size, package thickness, die-epad attach material).Compared to a FV commercial software, a simulation performed by TRAC using a pDTM takes about 1 / 3 of the CPU time, while the adoption of a pCTM leads to almost instantaneous results without any loss of accuracy.Moreover, TRAC is equipped with a user-friendly graphical interface that simplifies the choice of parameters and thus the construction of the geometry and mesh of the corresponding package.Owing to its features, TRAC can be used by semiconductor vendors with a two-fold aim: (1) to let customers effortlessly evaluate the thermal metrics of the packages they want to purchase through, for example, a web application; and (2) to support the design of more complex electronic systems.
TRAC variants suited to simulate other package families, handle multiple heat sources, and carry out dynamic thermal analyses are currently under development.

Figure 1 .
Figure 1.Specimens of the LQFP (a) and QFN (b) families sharing the same size of package (6 × 6

162Figure 2 .
Figure 2. JEDEC thermal metric ϑJA as a function of the number of DoFs, as evaluated through the

Figure 1 .
Figure 1.Specimens of the LQFP (a) and QFN (b) families sharing the same size of package (6 × 6

167 28 .Figure 2 .
Figure 2. JEDEC thermal metric ϑJA as a function of the number of DoFs, as evaluated through the

Figure 2 .
Figure2.JEDEC thermal metric ϑ JA as a function of the number of DoFs, as evaluated through the pDTM for a quarter of the 10 × 10 mm 2 LQFP with a 4.5 × 4.5 mm 2 pad and a 2 × 2 mm 2 die.The selected discretization is indicated.
extremely high to prevent unnecessarily long CPU times.As can be seen, the thermal metrics 180 decrease with increasing the die size (i.e., the HS size) due to the lower dissipated power density and 181 the enhanced lateral heat spreading.

Figure 3 .Figure 4
Figure 3.Some JEDEC thermal metrics against die size, as determined from the pDTM (blue) and a

Figure 4 .
Figure 4. JEDEC thermal metrics ϑJA and ϑJCtop vs. die size evaluated with the pDTM; results obtained

Figure 5 .
Figure 5. JEDEC thermal metric ϑJA vs. HS size for a square HS centered in the die, as evaluated

Figure 4 .
Figure 4. JEDEC thermal metrics ϑ JA and ϑ JCtop vs. die size evaluated with the pDTM; results obtained for 10 × mm 2 LQFPs (blue circles) are compared with the TQFP counterparts (orange triangles); in both cases, a 6 × 6 mm 2 epad is considered.

Figure 6 .
Figure 6.Comparison of the JEDEC thermal metric ϑJA provided by both a pDTM and a pCTM for

Figure 6 .
Figure 6.Comparison of the JEDEC thermal metric ϑ JA provided by both a pDTM and a pCTM for various QFPs.

Author Contributions:
Methodology, L.C.; Software, L.C. and S.R.; Validation, D.G., A.M., and C.M.V.; Investigation, L.C., S.R., and V.d.; Writing-Original Draft Preparation, V.d. and S.R.; Writing-Review & Editing, V.d. and S.R.; Supervision, C.M.V. Funding: This research received no external funding.Conflicts of Interest: The authors declare no conflict of interest.Nomenclature ϑ JA (K/W) junction to ambient thermal resistance Ψ JB (K/W) thermal characterization parameter to report the difference between junction temperature and the temperature of the board measured at the top surface of the board Ψ JCtop (K/W) thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface of the component package ϑ JB (K/W) junction to board thermal resistance