Reference-Free Dynamic Voltage Scaler Based on Swapping Switched-Capacitors

This paper introduces a reference-free, scalable, and energy-efficient dynamic voltage scaler (DVS) that can be reconfigured for multiple outputs. The proposed DVS employs a novel swapping switched-capacitor (SSC) technique, which can generate target output voltages with higher resolution and smaller ripple voltages than the conventional voltage scalers based on switched-capacitors. The proposed DVS consists of a cascaded 2:1 converter based on swapping capacitors, which is essential to achieve both very small voltage ripple and fine-grain conversion ratios. One of the serious drawbacks of the conventional voltage scalers is the need for external reference voltages to maintain the target output voltage. The proposed SSC; however, eliminates the needs for any reference voltages. This significant benefit is achieved by the self-charging ability of the SSC, which can recharge all its capacitors to the configured voltage by simply swapping the two capacitors in each stage. The proposed SSC-DVS was designed with a resolution of 16 output levels and implemented using a 130 nm CMOS (Complementary Metal Oxide semiconductor) process. We conducted measured results and post-layout simulations with an input voltage of 1.5 V to produce an output voltage range of 0.085–1.4 V, which demonstrated a power efficiency of 85% for a load current of 550 µA with a voltage ripple of as low as 2.656 mV for a 2 KΩ resistor load.

Nowadays, switched-capacitor voltage converters are the most popular architectures due to their process compatibility, high efficiency, and small area when integrated on-chip. Although inductor-based DC-DC converters have been commonly used in classical applications, they almost always require off-chip inductors, which makes them unsuitable for on-chip voltage scalers supplying multiple power domains. Implementing on-chip inductors incurs excessive chip areas for present process technologies. It also requires a special process to achieve an on-chip inductor with a high-quality factor, which increases both the complexity and the cost.
C. Huang et al. [7] demonstrated effective methods that can improve the quality factor of the inductor based on a packaged bond-wire-based inductive converter. This approach; however, requires special bonding wires that makes its fabrication impractical. On the other hand, conventional voltage converters based on switched-capacitors offer energy efficiency with only limited switching frequency and specific output voltages. Operating such voltage converters in non-optimal conditions often 1.
Two inputs V 1 and V 2 are applied to the SSC-DVS input ports to generate the average value V out = V 1 +V 2 2 . 2.
In phase 1, the bottom capacitor, C B , delivers the charges to the load circuit, and thus the amount of C B 's charge decreases. Therefore, the voltage across C B decreases while the voltage across C T increases over time. When at the middle of switching time T S 2 , the controller switches to phase 2. 3.
In phase 2, the controller reconfigures the cell by swapping C B and C T . Then C B 's positive terminal is connected to V 1 , while its negative terminal is connected to V out , as illustrated by Figure 1c. On the other hand, C T 's positive terminal is connected to V out while its negative terminal is connected to V 2 , as illustrated by Figure 1c. 4.
In phase 2, C T supplies the load.

5.
When T S , the controller switches back to phase 1, and the above steps are repeated.
terminal is connected to V1, while its negative terminal is connected to Vout, as illustrated by Figure 1c. On the other hand, CT's positive terminal is connected to Vout while its negative terminal is connected to V2, as illustrated by Figure 1c. 4. In phase 2, CT supplies the load. 5. When TS, the controller switches back to phase 1, and the above steps are repeated. Figure 2 shows the architecture of an n-bit SSC-DVS which generates 2 n levels of output voltages. Figure 3 illustrates the detailed circuit schematic of the n-bit SSC-DVS.

SSC-DVS Architecture
To quantify the proposed SSC-DVS, the SSC-DVS was implemented using metal-insulatormetal (MIM) capacitors. We chose MIM capacitors because they provide a relatively large capacitance for unit space and usually exhibit acceptable process variation. The other integrated capacitors, such as poly-insulator-poly (PIP) or metal-oxide-metal (MOM) structures, in contrast, exhibit more parasitic than MIMs [18,19]. Figure 4 illustrates the transmission gate structure of the switches that were used in the implemented circuit. The transmission gate consisted of NMOS (N-type Metal Oxide Semiconductor) and PMOS (P-type Metal Oxide Semiconductor) devices, and their body switches. The body switches can reduce the leakage current using the body switching technique [20,21]. The aspect ratio of the transmission-gate transistors were = = .
, which were selected based on the maximum target output current, while the aspect ratio of the body switch transistors were = = .
. Figure 5a depicts a small example of n = 2 when the target voltages were Vout1 = 750 mV and Vout2 = 375 mV. To explain the operation of the proposed architecture: In phase 1 (φ1) in Figure 6a, the vertical switches in stage 1 (S11, S31, S51, and S71) and stage 2 (S12, S32, S52, and S72) were ON; while the  Figure 2 shows the architecture of an n-bit SSC-DVS which generates 2 n levels of output voltages. Figure 3 illustrates the detailed circuit schematic of the n-bit SSC-DVS. horizontal switches in stage 1(S21, S41, S61, and S81) and stage 2 (S22, S42, S62, and S82) were OFF. In phase 2 (φ2) in Figure 6b, the vertical switches were OFF and the horizontal switches were ON. To generate, for example, conversion ratios of and , we applied D1D2 = (00)2 to connect the V1 and V2 inputs of the first stage to Vin and GND, respectively, leading to = = .

SSC-DVS Architecture
Then, inputs V1 and V2 of the second stage were connect to Vout1 and GND, respectively, producing = = .
= . Figure 6a,b show φ1 and φ2 phases, used to configure the switches of the swapping process to generate conversion ratios of and .   In the second configuration of Figure 7, we applied D1D2 = (01)2 to generate conversion ratios of and . Figure 7 shows phases φ1 and φ2 to configure the switches of the swapping process to generate conversion ratios of and . We connected inputs V1 and V2 of the first stage to Vin and GND, respectively, resulting in = = . Then inputs V1 and V2 of the second stage were connected to Vout1 and Vin, respectively, giving = = .
= . With Vin of To quantify the proposed SSC-DVS, the SSC-DVS was implemented using metal-insulator-metal (MIM) capacitors. We chose MIM capacitors because they provide a relatively large capacitance for unit space and usually exhibit acceptable process variation. The other integrated capacitors, such as poly-insulator-poly (PIP) or metal-oxide-metal (MOM) structures, in contrast, exhibit more parasitic than MIMs [18,19]. Figure 4 illustrates the transmission gate structure of the switches that were used in the implemented circuit. The transmission gate consisted of NMOS (N-type Metal Oxide Semiconductor) and PMOS (P-type Metal Oxide Semiconductor) devices, and their body switches. The body switches can reduce the leakage current using the body switching technique [20,21]. The aspect ratio of the transmission-gate transistors were W L n = W L p = 20 µm 0.13 µm , which were selected based on the maximum target output current, while the aspect ratio of the body switch transistors were 2 (φ2) in Figure 6b, the vertical switches were OFF and the horizontal switches were ON. To generate, for example, conversion ratios of and , we applied D1D2 = (00)2 to connect the V1 and V2 inputs of the first stage to Vin and GND, respectively, leading to = = .
Then, inputs V1 and V2 of the second stage were connect to Vout1 and GND, respectively, producing = = . = . Figure 6a,b show φ1 and φ2 phases, used to configure the switches of the swapping process to generate conversion ratios of and .   In the second configuration of Figure 7, we applied D1D2 = (01)2 to generate conversion ratios of and . Figure 7 shows phases φ1 and φ2 to configure the switches of the swapping process to generate conversion ratios of and . We connected inputs V1 and V2 of the first stage to Vin and GND, respectively, resulting in = = . Then inputs V1 and V2 of the second stage were connected to Vout1 and Vin, respectively, giving = = .
= . With Vin of Figure 5a depicts a small example of n = 2 when the target voltages were V out1 = 750 mV and V out2 = 375 mV. To explain the operation of the proposed architecture: In phase 1 (ϕ 1 ) in Figure 6a, the vertical switches in stage 1 (S 11 , S 31 , S 51 , and S 71 ) and stage 2 (S 12 , S 32 , S 52 , and S 72 ) were ON; while the horizontal switches in stage 1(S 21 , S 41 , S 61 , and S 81 ) and stage 2 (S 22 , S 42 , S 62 , and S 82 ) were OFF. In phase 2 (ϕ 2 ) in Figure 6b, the vertical switches were OFF and the horizontal switches were ON.
To generate, for example, conversion ratios of 1 2 and 1 4 , we applied D 1 D 2 = (00) 2 to connect the V 1 and V 2 inputs of the first stage to V in and GND, respectively, leading to V out1 = V in +GND 2 = 1 2 V in . Then, inputs V 1 and V 2 of the second stage were connect to V out1 and GND, respectively, producing Figure 6a,b show ϕ 1 and ϕ 2 phases, used to configure the switches of the swapping process to generate conversion ratios of 1 2 and 1 4 . In the second configuration of Figure 7, we applied D 1 D 2 = (01) 2 to generate conversion ratios of 1 2 and 3 4 . Figure 7 shows phases ϕ 1 and ϕ 2 to configure the switches of the swapping process to generate conversion ratios of 1 2 and 3 4 . We connected inputs V 1 and V 2 of the first stage to V in and GND, respectively, resulting in V out1 = V in +GND 2 = 1 2 V in . Then inputs V 1 and V 2 of the second stage were connected to V out1 and V in , respectively, giving V out2 = V out1 +GND With V in of 1.5 V, hence, the above SSC-DVS could generate 375 and 750 mV when D 1 D 2 = (010) 2 , while producing 750 and 1.125 mV when D 1 D 2 = (01) 2 .

Analytic Model
This section provides steady-state analysis for target output voltages of the proposed SSC-DVS. It also derives the current model of the proposed architecture while calculating its energy efficiency.

Steady-State Output Voltage
The output of the proposed SSC-DVS was connected in parallel with an output capacitor to reduce the voltage ripple. Error! Reference source not found. shows the simulation results of the effect of the output capacitor size on the voltage ripple. Here, VRipplen corresponded to Voutn where 1 < n < 4. The voltage ripple was measured for all the four outputs of 4-bit SSC-DVS. For example, Error! Reference source not found. shows that the voltage ripple gave a maximum value of 2.16 mV for CL of 500 pF, whereas it gave a minimum value of 0.199 mV for CL of 4 nF.
In phase 1 (φ1), the bottom flying capacitor CB delivered the charges to both the output capacitor and the load resistor. The n-bit SSC-DVS provided n output voltages. Each output voltage could be described by Equation (1). The conversion ratio (CR) of K output voltage could be expressed by Equation (4).
Here, Voutn is the output voltage of the n stage, Dn is the digital configuration bit of n stage to select the top voltage V1 or bottom voltage V2, is the binary code (decimal value) which consists of K digital bits , ⋯ (D1 is the MSB (Most Significant Bit)), and K is the number of stages in the range of 1 ≤ K ≤ n. The following examples explain the voltage equations. A 6-bit SSC-DVS with 1.5 V input voltage generated 2 6 = 64 voltage levels with a voltage step of . ≈ 23.44 mV, while it generated multiple outputs up to 6 outputs simultaneously. Figure 8 shows a 6-bit SSC-DVS example with two different configurations Bcode = (010110)2 and Bcode = (001100)2. Table 1 shows the conversion ratios for the generated output voltage levels. In Figure 8, the top port of the first stage was connected to the Vin, while the bottom port was connected to GND with "0". Hence, the Vout1 equals the average of the two inputs of the first stage leading to = = . = 0.75 mV.
Then, Vout1 was supplied to the top port of the second stage, while the bottom port was connected to Vin due to the second bit "1" in Bcode = (010110)2. Hence, = = . . = 1.125 V. In this way, the steady-state output voltage of each stage could be determined by selecting a configuration code.      while it generated multiple outputs up to 6 outputs simultaneously. Figure 8 shows a 6-bit SSC-DVS example with two different configurations Bcode = (010110)2 and Bcode = (001100)2. Table 1 shows the conversion ratios for the generated output voltage levels. In Figure 8, the top port of the first stage was connected to the Vin, while the bottom port was connected to GND with "0". Hence, the Vout1 equals the average of the two inputs of the first stage leading to = = . = 0.75 mV.
Then, Vout1 was supplied to the top port of the second stage, while the bottom port was connected to Vin due to the second bit "1" in Bcode = (010110)2. Hence, = = . . = 1.125 V. In this way, the steady-state output voltage of each stage could be determined by selecting a configuration code.

Analytic Model
This section provides steady-state analysis for target output voltages of the proposed SSC-DVS. It also derives the current model of the proposed architecture while calculating its energy efficiency.

Steady-State Output Voltage
The output of the proposed SSC-DVS was connected in parallel with an output capacitor to reduce the voltage ripple. Table 1 shows the simulation results of the effect of the output capacitor size on the voltage ripple. Here, V Ripplen corresponded to V outn where 1 < n < 4. The voltage ripple was measured for all the four outputs of 4-bit SSC-DVS. For example, Table 1 shows that the voltage ripple gave a maximum value of 2.16 mV for C L of 500 pF, whereas it gave a minimum value of 0.199 mV for C L of 4 nF. Table 1. Output capacitor size versus output voltage ripple for 4-bit SSC-DVS architecture. In phase 1 (ϕ 1 ), the bottom flying capacitor C B delivered the charges to both the output capacitor and the load resistor. The n-bit SSC-DVS provided n output voltages. Each output voltage could be described by Equation (1). The conversion ratio (CR) of K output voltage could be expressed by Equation (4).
Here, V outn is the output voltage of the n stage, D n is the digital configuration bit of n stage to select the top voltage V 1 or bottom voltage V 2 , B code K is the binary code (decimal value) which consists of K digital bits D 1 , D 2 · · · D K (D 1 is the MSB (Most Significant Bit)), and K is the number of stages in the range of 1 ≤ K ≤ n. The following examples explain the voltage equations. A 6-bit SSC-DVS with 1.5 V input voltage generated 2 6 = 64 voltage levels with a voltage step of 1.5 2 6 ≈ 23.44 mV, while it generated multiple outputs up to 6 outputs simultaneously. Figure 8 shows a 6-bit SSC-DVS example with two different configurations B code = (010110) 2 and B code = (001100) 2 . Table 2 shows the conversion ratios for the generated output voltage levels. In Figure 8, the top port of the first stage was connected to the V in , while the bottom port was connected to GND with "0". Hence, the V out1 equals the average of the two inputs of the first stage leading to V out1 = V in +GND 2 = 1.5+0 2 = 0.75 mV. Then, V out1 was supplied to the top port of the second stage, while the bottom port was connected to V in due to the second bit "1"

Analysis of Steady-State Current Flows in Each Stage
This subsection analyzes the current flow of SSC-DVS in two cases: A single-output case and a multi-output case.   Table 2. Two different configuration codes with conversion ratios and generated output voltages.

Analysis of Steady-State Current Flows in Each Stage
This subsection analyzes the current flow of SSC-DVS in two cases: A single-output case and a multi-output case.    Here, Iin is the input current and is the output current of the n-th stage. For the example of Figure 9a, which has Bcode= (010110)2 producing a conversion of , each output from stage 1 to stage 6, respectively, provided ·Iout6, ·Iout6, ·Iout6, ·Iout6, ·Iout6, and Iout6. Based on Equation (5), the total input current at the input port Vin was Iin = ·Iout6. Here Iout6 was the output current at the final output as illustrated in Figure 9a. The current Iin drawn from the Vin source could be calculated as Iin = + + + ·Iout6 by Equation (5). In the second example given in Figure 9b, the current for each SSC stage could be calculated in the same way as the first example using Equation (5). The total current at the input port Vin was Iin = ·Iout6, which was calculated by Equation (5) as Iin = + + ·Iout6. Figure 8 shows the current flows of the same 6-bit SSC-DVS, as the single-output case, above using the same configuration codes. It was; however, configured to generate multi-outputs simultaneously. Figure 8a,b show the current flows in each stage for codes Bcode = (010110)2 and Bcode = (001100)2, respectively. Equation (7) represents the current of the nth stage in terms of its load current and the input current taken by its next stage, which was the (n+1)th stage. The current drawn from the input I out n = I in CR n (5)

Multi-Output Case
Here, I in is the input current and I out n is the output current of the n-th stage. For the example of Figure 9a, which has B code = (010110) 2 producing a conversion of 27 64 , each output from stage 1 to stage 6, respectively, provided 1 32 ·I out6 , 1 16 ·I out6 , 1 8 ·I out6 , 1 4 ·I out6 , 1 2 ·I out6 , and I out6 . Based on Equation (5), the total input current at the input port V in was I in = 27 64 ·I out6 . Here I out6 was the output current at the final output V out 6 as illustrated in Figure 9a. The current I in drawn from the V in source could be calculated as I in = 1 64 + 1 32 + 1 8 + 1 4 ·I out6 by Equation (5). In the second example given in Figure 9b, the current for each SSC stage could be calculated in the same way as the first example using Equation (5). The total current at the input port V in was I in = 13 64 ·I out6 , which was calculated by Equation (5) as Figure 8 shows the current flows of the same 6-bit SSC-DVS, as the single-output case, above using the same configuration codes. It was; however, configured to generate multi-outputs simultaneously. Figure 8a,b show the current flows in each stage for codes B code = (010110) 2 and B code = (001100) 2 , respectively. Equation (7) represents the current I Sn of the nth stage in terms of its load current and the input current taken by its next stage, which was the (n+1)th stage. The current I in drawn from the input voltage source V in could be expressed by Equation (8). It was expressed by the half of the sum of the individual current for the stages that were supplied by V in . Equation (9) describes the current I in as a function of the output current and the conversion ratio of each stage where CR n is the conversion ratio of the n-th stage. By substituting Equation (10) in Equation (9), the I in could be expressed by Equation (11).

Multi-Output Case
Equation (12) to Equation (17) describe the current that was provided from each stage for the example of Figure 8.
In the 6-bit SSC-DVS example of Figure 8a, configured by B code = (010110) 2 , six output voltages were achieved simultaneously with conversion ratios of 1 2 , 3 4 , 3 8 , 11 16 , 27 32 , and 27 64 , respectively. Each SSC stage provided an output current for its own load and for the next stage as well. By substituting these conversion ratios in Equation (10) with V in = 1.5 V and all load resistances with R L1 = R L2 = · · · = R L6 = 2 KΩ, the estimated total input current drawn from V in source was I in ≈ 1.736 mA.
In the example of Figure 8b, a code B code = (001100) 2 was applied to produce six outputs with conversion ratios of 1 2 , 1 4 , 5 8 , 13 16 , 13 32 , and 13 64 , respectively. By substituting these conversion ratios in Equation (10) with the same conditions as in the previous example, the total input current drawn by the source was calculated as I in ≈ 1.177 mA. Figure 10 shows a comparison between error currents that came from each stage based on the simulation and calculation in the example of Figure 8a. Both the ideal and calculated currents were estimated using Equations (12)- (17). The ideal current employed these equations with the assumption of ideal V outn (no-load was connected), while the simulated current employed V outn obtained from simulations with load resistances of R L1 = R L2 = · · · = R L6 = 10 KΩ. It showed a maximum error of 2.6% between the simulated and ideal, while it showed a maximum error of 1.8% between the calculated and ideal. Figure 10 validates the correctness of the equations by proving that the equations well match the simulation results of the current per stages.
Energies 2019, 12, 625 10 of 23 error of 2.6% between the simulated and ideal, while it showed a maximum error of 1.8% between the calculated and ideal. Figure 10 validates the correctness of the equations by proving that the equations well match the simulation results of the current per stages.   Figure 11 shows the error current of calculated and simulated input currents, which were drawn from Vin for the example of Figure 8a when the load resistance was varied from 1 to 60 KΩ. The error current curve shows that the simulated and calculated currents matched well in general, with the largest difference of less than only 7.5%, which occurred when a heavy load was connected. Figure  11 shows that Equation (11) perfectly matched the simulation results when a light load was connected.

Efficiency Analysis
This subsection analyzes the energy efficiency of the proposed SSC-DVS architecture. We used the example of 1-bit SSC-DVS in Figure 1 again for simplicity. Figure 12 represents the charge transfer model for 1-bit SSC-DVS. Here, Ceq is the equivalent capacitance of the flying capacitance CT and CB, where Ceq = CT + CB. RP is the parasitic resistance. For simplicity, we assume that RP is negligible in the remaining analysis.
If the maximum voltage VCmax across Ceq is larger than the minimum output voltage Voutmin, the charges in Ceq gets shared with CL and also gets dissipated by RL until CL is fully charged and ICL becomes 0 A, as shown in Figure 13. Right after this process, capacitors Ceq and CL transfer part of  Figure 11 shows the error current of calculated and simulated input currents, which were drawn from V in for the example of Figure 8a when the load resistance was varied from 1 to 60 KΩ. The error current curve shows that the simulated and calculated currents matched well in general, with the largest difference of less than only 7.5%, which occurred when a heavy load was connected. Figure 11 shows that Equation (11) perfectly matched the simulation results when a light load was connected.
Energies 2019, 12, 625 10 of 23 error of 2.6% between the simulated and ideal, while it showed a maximum error of 1.8% between the calculated and ideal. Figure 10 validates the correctness of the equations by proving that the equations well match the simulation results of the current per stages.   Figure 11 shows the error current of calculated and simulated input currents, which were drawn from Vin for the example of Figure 8a when the load resistance was varied from 1 to 60 KΩ. The error current curve shows that the simulated and calculated currents matched well in general, with the largest difference of less than only 7.5%, which occurred when a heavy load was connected. Figure  11 shows that Equation (11) perfectly matched the simulation results when a light load was connected.

Efficiency Analysis
This subsection analyzes the energy efficiency of the proposed SSC-DVS architecture. We used the example of 1-bit SSC-DVS in Figure 1 again for simplicity. Figure 12 represents the charge transfer model for 1-bit SSC-DVS. Here, Ceq is the equivalent capacitance of the flying capacitance CT and CB, where Ceq = CT + CB. RP is the parasitic resistance. For simplicity, we assume that RP is negligible in the remaining analysis.
If the maximum voltage VCmax across Ceq is larger than the minimum output voltage Voutmin, the charges in Ceq gets shared with CL and also gets dissipated by RL until CL is fully charged and ICL becomes 0 A, as shown in Figure 13. Right after this process, capacitors Ceq and CL transfer part of

Efficiency Analysis
This subsection analyzes the energy efficiency of the proposed SSC-DVS architecture. We used the example of 1-bit SSC-DVS in Figure 1 again for simplicity. Figure 12 represents the charge transfer model for 1-bit SSC-DVS. Here, C eq is the equivalent capacitance of the flying capacitance C T and C B , where C eq = C T + C B . R P is the parasitic resistance. For simplicity, we assume that R P is negligible in the remaining analysis.

Charge Distribution Phase
Due to unbalanced initial voltages on Ceq and CL, when VCmax > Voutmin, Ceq delivers charges to CL and RL until CL is fully charged. By using the charge conservation principle, we can model the amount of charge delivered from Ceq to CL and RL by Equation (18). Let IRL represent the total load current drawn by the load circuit. For the sake of simplicity of proving the concept, we assume in this paper that the load current is constant regardless of the load's supply voltage changes. Hence, we can model the load circuit by a resistor RL.
Here, VCmin is the voltage of Ceq after the charge distribution process, while Voutmax is the voltage of CL after the charge distribution process. In addition, TCD is the time duration for the charge distribution process to reach the condition VCmin = Voutmax. The maximum output voltage can be expressed by Equation (19). The average output current IRL can be calculated by Equation (20) under the assumption that TCD is much smaller than the time constant of the circuit. If the maximum voltage V Cmax across C eq is larger than the minimum output voltage V outmin , the charges in C eq gets shared with C L and also gets dissipated by R L until C L is fully charged and I CL becomes 0 A, as shown in Figure 13. Right after this process, capacitors C eq and C L transfer part of their energy to the load resistor R L . Depending on the status of C L , we analyze the energy efficiency in two phases: (1) charge distribution phase, and (2) delivery phase.

Charge Distribution Phase
Due to unbalanced initial voltages on Ceq and CL, when VCmax > Voutmin, Ceq delivers charges to CL and RL until CL is fully charged. By using the charge conservation principle, we can model the amount of charge delivered from Ceq to CL and RL by Equation (18). Let IRL represent the total load current drawn by the load circuit. For the sake of simplicity of proving the concept, we assume in this paper that the load current is constant regardless of the load's supply voltage changes. Hence, we can model the load circuit by a resistor RL.
Here, VCmin is the voltage of Ceq after the charge distribution process, while Voutmax is the voltage of CL after the charge distribution process. In addition, TCD is the time duration for the charge distribution process to reach the condition VCmin = Voutmax. The maximum output voltage can be expressed by Equation (19). The average output current IRL can be calculated by Equation (20) under the assumption that TCD is much smaller than the time constant of the circuit.

Charge Distribution Phase
Due to unbalanced initial voltages on C eq and C L , when V Cmax > V outmin , C eq delivers charges to C L and R L until C L is fully charged. By using the charge conservation principle, we can model the amount of charge delivered from C eq to C L and R L by Equation (18). Let I RL represent the total load current drawn by the load circuit. For the sake of simplicity of proving the concept, we assume in this paper that the load current is constant regardless of the load's supply voltage changes. Hence, we can model the load circuit by a resistor R L .
Here, V Cmin is the voltage of C eq after the charge distribution process, while V outmax is the voltage of C L after the charge distribution process. In addition, T CD is the time duration for the charge distribution process to reach the condition V Cmin = V outmax . The maximum output voltage can be expressed by Equation (19). The average output current I RL can be calculated by Equation (20) under the assumption that T CD is much smaller than the time constant of the circuit.

Delivery Phase
In the delivery phase, capacitors C eq and C L transfer part of their charges to the load resistor R L in the remaining time of T 2 − T CD , where T 2 is half of the switching period. By applying the charge conservation principle, we can model the amount of charge delivered from C eq and C L to R L by Equation (21), while we can calculate the final voltage across the C eq and C L by Equation (22), assuming that R P is negligible like in subsection C.

Losses Analysis
In SC voltage converters there are two kinds of losses that are dependent or independent of the load current I RL . The losses that are dependent on the output current include SC loss and switch conduction loss. While the losses that are independent (current loss, I loss ) of the output current include the gate and bottom plate capacitor switching losses [22,23]. Figure 14 presents a model to calculate the total power loss in the proposed circuit. In Figure 14, the independent losses were modeled by a series resistance R S , while the independent losses were modeled by a shunt resistance R Sh . The total power losses in the proposed circuit can be expressed by Equation (23) P Loss = P R S + P R Sh (23)  The equivalent series resistance could be calculated by Equation (26), which was derived based on Equations (6) and (7) in reference [22]. While the equivalent shunt resistance could be calculated by Equation (27), which was derived based on Equations (10) and (11) in [22]. Here, M Cap is a constant related to the converter's output resistance and it determined based on the converter topology (e.g., for the SSC M Cap = 4). F sw is the switching frequency, R on is the switch resistance density, which is measured in Ω·m, W Sw is the total width of all transistors, and M Sw is a constant which is determined by the converter's topology (e.g., for the SSC M Sw = 16). M bott is a constant related to the converter's topology (e.g., for the SSC M bott = 2), C bott is the bottom plate capacitance, and C gate is the gate capacitance density in F/m of the switches.
Based on Equations (19) and (22) we could calculate the average output voltage; thus, we could estimate the power that delivered to the load P out . We could, also, calculate the power loss by the proposed SSC by using Equation (20) and Equations (23)-(27). Thus, we could calculate the efficiency by Equation (28) as well. η = P out P out + P loss (28) Table 3 shows the simulation and calculation results of the power efficiency for the 1-bit SSC-DVS example shown in Figure 1. Schematic-level circuit simulations were conducted with two different loads, of 2 and 10 KΩ. We measured the maximum voltage across C eq for both stages from simulation, then we calculated the average output voltage using Equations (19) and (22). Table 3 validates the accuracy of Equations (19), (22), and (28) in estimating the output voltage and efficiency. Table 3 shows that the results calculated by our analytical model (Equations (19)-(28)) closely matched the simulation results. The difference in the output voltage and efficiency, respectively, was less than 1 mV and less than 0.05%.

Experimental Environment
We have implemented a test chip of the proposed dynamic voltage scaler using a 130 nm CMOS process. The design, simulation, and implementation were carried out using the Spectre simulator tool of the Cadence Design Suite. Figure 15 shows the circuit schematic of the implemented 4-bit SSC-DVS that provides 16 voltage levels. We supplied V in of the SSC-DVS with 1.5 V, while connecting the output to a simple load circuit. The load circuit was modeled by a resistor, R L , of 2 KΩ in parallel with a load capacitor, C L , of 1 nF (twice the flying capacitors) to demonstrate the performance of the proposed voltage scaler. Figure 16a shows the layout design of the test chip, while Figure 16b shows the micro-photo of its fabricated silicon. Due to area limitation in the silicon, we implemented a small 4-bit SSC-DVS architecture with on-chip capacitors of a small size of 0.4 nF, with RC load of 1 nF and 2 KΩ.
1.35 V with 80 mV resolution. The voltage step of the output for this example circuit could be calculated by Equation (3) as 93.75 mV. The difference in Vout's step-size between the analysis result and the circuit schematic simulation was 11.23 mV, while the difference in Vout's step-size between the analysis result and the post-layout simulation was 13.75 mV. These differences were attributed to the voltage drop across the switches and parasitic components.  1.35 V with 80 mV resolution. The voltage step of the output for this example circuit could be calculated by Equation (3) as 93.75 mV. The difference in Vout's step-size between the analysis result and the circuit schematic simulation was 11.23 mV, while the difference in Vout's step-size between the analysis result and the post-layout simulation was 13.75 mV. These differences were attributed to the voltage drop across the switches and parasitic components.   Figure 17 shows the two simulation results that demonstrate 16 voltage levels. The circuit simulation, highlighted by black color, produced V out from 82.3 mV to 1.42 V with a resolution of 85 mV. On the other hand, the post-layout simulation, indicated by red color, generated V out of 16 output voltage levels from 80.76 mV to 1.35 V with 80 mV resolution. The voltage step of the output for this example circuit could be calculated by Equation (3) as 93.75 mV. The difference in V out 's step-size between the analysis result and the circuit schematic simulation was 11.23 mV, while the difference in V out 's step-size between the analysis result and the post-layout simulation was 13.75 mV. These differences were attributed to the voltage drop across the switches and parasitic components. Figure 18 illustrates the measured results of the proposed SSC-DVS. It shows accurate 16 output voltage levels from 45 mV to 1.424 V for V out4 , while it shows accurate eight output voltage levels from 117 mV to 1.242 V for V out3 . Figure 19 shows the measured settling time of the SSC-DVS. It shows 900 nS when the target output voltage was reconfigured from 465 to 550 mV, with an input supply of 1.5 V when the load current was 275 µA. It shows, also, a very small overshooting voltage of 5 mV.   Figure 18 illustrates the measured results of the proposed SSC-DVS. It shows accurate 16 output voltage levels from 45 mV to 1.424 V for Vout4, while it shows accurate eight output voltage levels from 117 mV to 1.242 V for Vout3. Figure 19 shows the measured settling time of the SSC-DVS. It shows 900 nS when the target output voltage was reconfigured from 465 to 550 mV, with an input supply of 1.5 V when the load current was 275 µA. It shows, also, a very small overshooting voltage of 5 mV. Figure 20 shows the post-layout simulation results of the load regulation when the load current changes. When the target output voltage was set to 1.031 V and the load current received a perturbation by digital control signals, we observed fluctuation of the output voltage. Figure 20 shows negative and positive transitions of the output voltage when the current changed from 50 to 495 µA and from 495 to 50 µA. The settling time for load regulation was 300 ns for the negative transition, while the settling time was 360 ns for the positive transition. Figure 21 shows the post-layout simulation result of the output voltage ripple for the above SSC-DVS test chip, which was obtained with a wide range of capacitor size. It can be observed that the voltage ripple ranged from 1.5 to 4.5 mV. This small ripple voltage was obtained thanks to the highlyefficient recharging operation of the swapping capacitors. It also shows that the voltage ripple further decreased when the capacitor size increased.    Figure 18 illustrates the measured results of the proposed SSC-DVS. It shows accurate 16 output voltage levels from 45 mV to 1.424 V for Vout4, while it shows accurate eight output voltage levels from 117 mV to 1.242 V for Vout3. Figure 19 shows the measured settling time of the SSC-DVS. It shows 900 nS when the target output voltage was reconfigured from 465 to 550 mV, with an input supply of 1.5 V when the load current was 275 µA. It shows, also, a very small overshooting voltage of 5 mV. Figure 20 shows the post-layout simulation results of the load regulation when the load current changes. When the target output voltage was set to 1.031 V and the load current received a perturbation by digital control signals, we observed fluctuation of the output voltage. Figure 20 shows negative and positive transitions of the output voltage when the current changed from 50 to 495 µA and from 495 to 50 µA. The settling time for load regulation was 300 ns for the negative transition, while the settling time was 360 ns for the positive transition. Figure 21 shows the post-layout simulation result of the output voltage ripple for the above SSC-DVS test chip, which was obtained with a wide range of capacitor size. It can be observed that the voltage ripple ranged from 1.5 to 4.5 mV. This small ripple voltage was obtained thanks to the highlyefficient recharging operation of the swapping capacitors. It also shows that the voltage ripple further decreased when the capacitor size increased.    Figure 20 shows the post-layout simulation results of the load regulation when the load current changes. When the target output voltage was set to 1.031 V and the load current received a perturbation by digital control signals, we observed fluctuation of the output voltage. Figure 20 shows negative and positive transitions of the output voltage when the current changed from 50 to 495 µA and from 495 to 50 µA. The settling time for load regulation was 300 ns for the negative transition, while the settling time was 360 ns for the positive transition.    Figure 22 shows the post-layout simulation result of the voltage ripple along with a wide range load resistance RL. It changed exponentially from 90 µV to 8.43 mV, a significantly smaller ripple voltage than previous designs reported in [9,13,15].  Figure 21 shows the post-layout simulation result of the output voltage ripple for the above SSC-DVS test chip, which was obtained with a wide range of capacitor size. It can be observed that the voltage ripple ranged from 1.5 to 4.5 mV. This small ripple voltage was obtained thanks to the highly-efficient recharging operation of the swapping capacitors. It also shows that the voltage ripple further decreased when the capacitor size increased.   Figure 22 shows the post-layout simulation result of the voltage ripple along with a wide range load resistance R L . It changed exponentially from 90 µV to 8.43 mV, a significantly smaller ripple voltage than previous designs reported in [9,13,15].   Figure 22 shows the post-layout simulation result of the voltage ripple along with a wide range load resistance RL. It changed exponentially from 90 µV to 8.43 mV, a significantly smaller ripple voltage than previous designs reported in [9,13,15].      Figure 24 shows the post-layout simulation result of the voltage ripple along with varying target output voltage V out . In this simulation, we applied V in = 1.5 V, F SW = 50 MHz, C = 50 pF, and R L = 2 KΩ. The voltage ripple changed almost linearly from 0.15 to 1.1 mV. Figure 18 shows that the measured output voltage ripple for the SSC-DVS test chip was 2.656 mV. This small ripple voltage demonstrated that the proposed SSC-DVS was highly efficient in minimizing voltage ripple.    Figure 18 shows that the measured output voltage ripple for the SSC-DVS test chip was 2.656 mV. This small ripple voltage demonstrated that the proposed SSC-DVS was highly efficient in minimizing voltage ripple. Figure 25 shows the efficiency of the proposed SSC-DVS obtained by post-layout simulations with varying capacitor size C. Figure 25a shows that it provided very high efficiency for most of the capacitor size, while it loss the efficiency down to 80% for the capacitor size below 1 pF. In order to maintain high efficiency in the case of small capacitors, we could use a higher switching frequency. Figure 26 presents the simulation results of the efficiency for varying the load resistance RL. In Figure 26, the schematic simulations showed high efficiency from 90% to 95% for heavy load cases, with RL < 25 KΩ. This efficiency was measured as 85% to 92% when tested with post-layout simulations. This difference between the schematic simulation and post-layout simulation was due to the parasitic capacitance and resistance considered in the post-layout simulation.  Figure 25a shows that it provided very high efficiency for most of the capacitor size, while it loss the efficiency down to 80% for the capacitor size below 1 pF. In order to maintain high efficiency in the case of small capacitors, we could use a higher switching frequency.  Figure 27 illustrates the circuit simulation and the post-layout simulation of the efficiency for varying switching frequency, FSW. The circuit simulation shows the efficiency increased exponentially from 30% at FSW = 1 MHz to 99% at FSW = 1 GHz. For higher FSW values, the efficiency saturated at 99%. In other words, the difference between the output voltage and the voltage across the bottom capacitor CB was very small. In contrast, at a very low switching frequency below 1 MHz, it exhibited a poor efficiency of 30%. This was due to slow charging and discharging operations for the bottom capacitor CB. We could keep the efficiency high by increasing the capacitor size, as shown in Figure  25b. On the other hand, in Figure 27, the post-layout simulation exhibited efficiency 10%-20% lower than the circuit simulation result for the frequency higher than 200 MHz. The lower efficiency could be explained by the fact that we used regular transistors, not radio frequency (RF) transistors for the test chip design, thus the post-layout simulation experienced higher parasitic values at high frequency.    Figure 26 presents the simulation results of the efficiency for varying the load resistance R L . In Figure 26, the schematic simulations showed high efficiency from 90% to 95% for heavy load cases, with R L < 25 KΩ. This efficiency was measured as 85% to 92% when tested with post-layout simulations. This difference between the schematic simulation and post-layout simulation was due to the parasitic capacitance and resistance considered in the post-layout simulation. Figure 27 illustrates the circuit simulation and the post-layout simulation of the efficiency for varying switching frequency, F SW . The circuit simulation shows the efficiency increased exponentially from 30% at F SW = 1 MHz to 99% at F SW = 1 GHz. For higher F SW values, the efficiency saturated at 99%. In other words, the difference between the output voltage and the voltage across the bottom capacitor C B was very small. In contrast, at a very low switching frequency below 1 MHz, it exhibited a poor efficiency of 30%. This was due to slow charging and discharging operations for the bottom capacitor C B . We could keep the efficiency high by increasing the capacitor size, as shown in Figure 25b. On the other hand, in Figure 27, the post-layout simulation exhibited efficiency 10%-20% lower than the circuit simulation result for the frequency higher than 200 MHz. The lower efficiency could be explained by the fact that we used regular transistors, not radio frequency (RF) transistors for the test chip design, thus the post-layout simulation experienced higher parasitic values at high frequency.    Figure 28 presents the efficiency of the proposed architecture when the temperature varied from −40 to 120 • C. It showed almost constant efficiency of 94% for the schematic simulation, while it showed 91% efficiency for the post-layout simulation. Therefore, the proposed SSC-DVS was well suited for applications operating under large temperature changes.   Figure 29 shows the measured efficiency of the proposed SSC-DVS versus the conversion ratio and output load current of the fourth stage (Iout4). The efficiency of more than 80% was obtained with an output load current of the fourth stage (Iout4) in the range of 50-550 µA. The efficiency values lower than the simulation results were primarily attributed to the slow transition of control signals as well as the parasitic circuit elements. We expect that the efficiency of the test chip could be improved to the level of post-layout simulations if we improved the control signals by adding buffer circuits.   Figure 28 presents the efficiency of the proposed architecture when the temperature varied from -40 to 120 °C. It showed almost constant efficiency of 94% for the schematic simulation, while it showed 91% efficiency for the post-layout simulation. Therefore, the proposed SSC-DVS was well suited for applications operating under large temperature changes.  Table 4 compares the key properties of the proposed SSC-DVS test chip with other switched-capacitor voltage converters recently published. The proposed 4-bit SSC-DVS showed 2 4 = 16 conversion ratios. The 4-bit recursive voltage converter of [14] shows 2 4 − 1 = 15 conversion ratios, while the 7-bit SAR of [9] can provide 117 conversion ratios. The designs reported in [15][16][17] show only one to three fixed conversion ratios. The proposed SSC-DVS showed an almost rail-rail output voltage range, and; thus, it could provide extremely low supply voltages to ultra-low power applications. The design of [9] provides a limited range of supply voltages that are larger than 0.45 V, while the designs reported in [15][16][17] provide an output voltage of only 0.5 V in or higher. Furthermore, the proposed SSC-DVS showed a smaller voltage ripple of 2.656 mV. For example, it showed around a 84% and 94% smaller voltage ripple than the recent voltage converters of [9,15], respectively. The measured results of the proposed SSC-DVS showed a peak efficiency of 85%, which was higher than the previous circuits reported in [9,16,17].

Comparison
The total size of its on-chip capacitors was 400 pF, while the total area of the SSC-DVS test chip was 0.334 mm 2 , including the on-chip flying capacitors and output RC load.

Conclusions
In this paper, a reference-free, scalable, and high efficiency, multi-output DVS architecture based on n-bit swapping switched-capacitor topology is proposed. It employs n-cascaded 2:1 swapping capacitor stages to generate 2 n conversion ratios with a resolution of V in 2 n . Its swapping switched-capacitor unit forms a structure of self-biasing, and; thus, ensures that the output voltage of each stage converges to the target voltage, which is determined by the digital code configuration. Thus, SSC-DVS does not require a power-hungry reference voltage generator and comparator feedback circuits, thus it can provide significantly higher energy efficiency than previous voltage converters. A 4-bit SSC-DVS was implemented into a test chip using a 130 nm MagnaChip CMOS process. Post-layout simulations were conducted with an input voltage of 1.5 V, switching frequency of 50 MHz, and a load circuit that modeled by a load resistor of 2 KΩ. The measurements and the realistic simulations, with all layout parasitic components, demonstrated that it achieved a stable 16 output voltage levels with a step size of 80 mV, and a ripple voltage as small as 2.656 mV. SSC-DVS exhibited a peak efficiency of 85% when it supplied a load current of 550 µA-a substantially higher energy efficiency compared with previous switch-capacitor converters.