Operation and Control of a Seven-Level V-Clamp Multilevel Converter

: Multilevel converters are well suited for high-power and high-quality power conversion. This paper presents a new seven-level V-clamp multilevel converter (VMC) with reduced clamping devices. All phases of the VMC share common DC-link capacitors and realize bidirectional power conversion without ﬂying capacitors. Each branch of the VMC sustains only a single-level voltage of the DC-link capacitors during its commutation process. Hence, the series switches can be controlled as simple as one switch and the dynamic voltage unbalancing issue is avoided. In this paper, the operation principle and the modulation method of the VMC are analyzed in detail. In addition, compensation control for non-ideal factors is designed to improve the output performance. The output fundamental distortion is compensated and the harmonics are reduced. Finally, a laboratory prototype of the seven-level VMC is set up to verify the feasibility of the presented topology and analysis.


Introduction
Featured with prominent AC output performance, low common-mode voltage and reduced switching stress, multilevel converters attract much attention from industry and academia since their emergence. They have found widespread applications in medium-/high-voltage fields, such as motor drive, power quality improvement, and high-voltage DC (HVDC) transmission, etc. [1][2][3][4]. Additionally, three-level or four-level converters are also considered for low-voltage fields to improve the power-density and power-quality [5,6].
Conventional multilevel topologies, such asthe neutral point clamped converter (NPCC), flying capacitor converter (FCC), cascaded H-bridge converter (CHBC), as well asthe modular multilevel converter (MMC), have been well studied and commercialized in the past decades [7]. However, when the voltage levels increase, the number of clamping diodes in the NPCC and flying capacitors (FCs) in the FCC rises tremendously [8,9]. Furthermore, the NPCC suffers from indirect clamping of the inner devices when the voltage level is higher than three [10]. The CHBC and MMC are easier to expand the voltage levels due to their modular design [11]. But the CHBC needs a phase-shifting transformer to provide isolated DC sources, which results in substantial investment and volume [12]. The MMC shows good prospects for HVDC transmission. But the complex controls (e.g., capacitor voltage balancing control and circulating current suppression control) and relative high primary investment make the MMC less attractive in medium-voltage applications [13].
The hybrid multilevel topologies are also reported recently to pursue the reduction of devices or improvement of DC-link voltage availability [1,4], such as active NPCC (ANPCC) [14], nested NPCC (NNPCC) [15], and boost ANPCC (Boost-ANPCC) [16]. However, a certain number of FCs are still required in the multiphase system, which imposes excessive cost and accommodation space on the converters [7]. Besides, the dynamic voltage unbalancing problem in series switches and multilevel voltage jumping of the output voltage may occur during the commutation process. It further results in permanent damage to the series switches and over-pressure on the insulation of the filter/motor [17].
In this paper, a new seven-level converter in which the clamping branches resemble a "V" shape, named as a V-clamp multilevel converter (VMC), is introduced [18]. With reduced clamping devices and no FCs, the VMC has a smaller footprint and simple control. Meanwhile, the issues of dynamic voltage unbalancing in series switches and multilevel voltage jumping of the output voltage are avoided with appropriate switching states' design.
This paper is organized as follows. In Section 2, the configuration and operation principle of the seven-level VMC are introduced. Its commutation process is described in Section 3. Then the modulation method is discussed in Section 4, and the sinusoidal pulse-width modulation (SPWM) is applied. In Section 5, the effects of non-ideal factors including dead-time, switching delay, and voltage drop of devices are analyzed in detail. In addition, a compensation control for the seven-level VMC is designed to improve its output performance. In Section 6, experimental results are presented to validate the presented theory and analysis. Finally, conclusions are summarized in Section 7. Figure 1 illustrates the configuration of the three-phase seven-level VMC. All phases share six common DC-link capacitors in series (C 1 , C 2 , C 3 , C 4 , C 5 , C 6 ), whose rated voltage is the single-level voltage (E = V dc /6). Considering "O" as the reference zero-point, the DC-link is evenly divided into seven levels, i.e., +3E, +2E, +E, 0, −E, −2E and −3E. and no FCs, the VMC has a smaller footprint and simple control. Meanwhile, the issues of dynamic voltage unbalancing in series switches and multilevel voltage jumping of the output voltage are avoided with appropriate switching states' design.

Topology Configuration
This paper is organized as follows. In Section 2, the configuration and operation principle of the seven-level VMC are introduced. Its commutation process is described in Section 3. Then the modulation method is discussed in Section 4, and the sinusoidal pulse-width modulation (SPWM) is applied. In Section 5, the effects of non-ideal factors including dead-time, switching delay, and voltage drop of devices are analyzed in detail. In addition, a compensation control for the seven-level VMC is designed to improve its output performance. In Section 6, experimental results are presented to validate the presented theory and analysis. Finally, conclusions are summarized in Section 7. Figure 1 illustrates the configuration of the three-phase seven-level VMC. All phases share six common DC-link capacitors in series (C1, C2, C3, C4, C5, C6), whose rated voltage is the single-level voltage (E = Vdc/6). Considering "O" as the reference zero-point, the DC-link is evenly divided into seven levels, i.e., +3E, +2E, +E, 0, −E, −2E and −3E.

Topology Configuration
In each phase leg, there are one power arm and six clamping branches, composed of 18 power switching devices (such as IGBT or MOSFET) and six diodes. All power components have the same rated voltage of E. The power arm is composed of S1, S2, S3, S4, S5, S6, S7, and S8. Meanwhile, S9, S10, and D1 form three forward clamping branches, which diode currents flow to the power arm. D2, S11, and S12 form three backward clamping branches, which diode currents flow to the DC-link. Corresponding nodes of the DC-link and the power arm are linked by these six clamping branches respectively, then the AC terminal potential can be clamped to any of the seven levels.
In the presented topology, series switches are applied to achieve higher withstand voltage. Then, S4 represents three series switches (S4a, S4b, and S4c) and so does S5. Likewise, S10 and S11 represent two series switches, D1 and D2 represent three series diodes, as seen in Figure 1.
D1b D1c S11a S11b S12 D2a D2b D2c  In each phase leg, there are one power arm and six clamping branches, composed of 18 power switching devices (such as IGBT or MOSFET) and six diodes. All power components have the same rated voltage of E. The power arm is composed of S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 . Meanwhile, S 9 , S 10 , and D 1 form three forward clamping branches, which diode currents flow to the power arm. D 2 , S 11 , and S 12 form three backward clamping branches, which diode currents flow to the DC-link. Corresponding nodes of the DC-link and the power arm are linked by these six clamping branches respectively, then the AC terminal potential can be clamped to any of the seven levels. In the presented topology, series switches are applied to achieve higher withstand voltage. Then, S 4 represents three series switches (S 4a , S 4b , and S 4c ) and so does S 5 . Likewise, S 10 and S 11 represent two series switches, D 1 and D 2 represent three series diodes, as seen in Figure 1.

Switching States Analysis
To ensure the availability of the seven-level VMC, the switching states analysis hereafter is given under the following operation principles:

1.
Series switches operate simultaneously. Then, the states of S 4a , S 4b , and S 4c are represented by S 4 . So does S 5 , S 10 , and S 11 . 2.
In order to prevent the short-circuit of capacitors, switches S 1 and S 9 , S 2 and S 10 , S 3 and S 5 , S 4 and S 6 , S 7 and S 11 , and S 8 and S 12 operate in a complementary way, respectively. 3.
To reduce the switching times, only one complementary switching pair should change in each commutation process.
Therefore, the switching states of the seven-level VMC are designed as Table 1. Where "1" represents the switching state is on, and "0" represents the switching state is off. The corresponding current paths of each state are illustrated in Figure 2, where the red line represents a positive phase current (i o > 0) and the blue line represents a negative phase current (i o < 0). Table 1. Switching states of the seven-level VMC. Table 2 presents the number of power components required in the three-phase seven-level VMC and other conventional multilevel converters, including the NPCC, FCC, CHBC and MMC. The rated voltages of capacitors, diodes, and power switches are all set as E here. It can be seen that, only one power source and six capacitors are required in the proposed topology and the NPCC. Moreover, the number of total required power components in the VMC is reduced from 132 to 78 in comparison with the NPCC.   Table 2 presents the number of power components required in the three-phase seven-level VMC and other conventional multilevel converters, including the NPCC, FCC, CHBC and MMC. The rated voltages of capacitors, diodes, and power switches are all set as E here. It can be seen that, only one power source and six capacitors are required in the proposed topology and the NPCC. Moreover, the number of total required power components in the VMC is reduced from 132 to 78 in comparison with the NPCC.

Commutation Process
One concern in the seven-level VMC is that the inconsistent switching actions of the series switches (S 4 , S 5 , S 10 , and S 11 ) may result in dynamic voltage unbalancing. But, since the output voltage of the converter only changes one level in each commutation process, the dynamic over-voltage would not appear in the presented topology.
For better understanding, the commutation process from state of +2E (seen as Figure 2b) to state of +E (seen as Figure 2c) is discussed in the following text. During this commutation process, S 2 is Energies 2019, 12, 4761 5 of 13 turned off firstly, then the series switches of S 10a and S 10b are turned on, the current paths are shown in Figure 3. It is also noted that the multilevel voltage jumping of the output voltage would not appear in the VMC. During the commutation process between any two adjacent levels, the output voltage depends on the current direction of io. When io > 0, the output voltage is connected to the lower level; and when io < 0, the output voltage is connected to the higher level. Thus, the output voltage keeps unchanged or only changes a single level in each commutation process.

Modulation Method
In this paper, phase disposition SPWM (PD-SPWM) is adopted in the VMC due to its low complexity and superior performance [19]. Figure 4 illustrates the PD-SPWM waveforms arrangement and the corresponding switching signals. Six triangular carriers (vtri1, vtri2, vtri3, vtri4, vtri5, and vtri6) are compared with a reference wave (vref) to get control signals for switches. The peak-to-peak value of each carrier is 1/3, the peak value of output voltage is Vo, then the modulation index m can be expressed as: The relationship between comparison results and switching signals are as follows: 1. When vref > vtri1, S1 is turned on and S9 is turned off. 2. When vref > vtri2, S2 is turned on and S10 is turned off. 3. When vref > vtri3, S3 is turned on and S5 is turned off. At a condition of i o < 0 (blue line), i o freewheels through the anti-paralleled diode of S 2 . The output voltage is +2E, and the total blocking voltage of S 10 is E. Thus, when switching actions of S 10a and S 10b are inconsistent, the last turned-on switch will withstand whole blocking voltage stress, which is E.
At a condition of i o > 0 (red line), i o freewheels through the diodes of S 10a and S 10b . The output voltage is +E, and the total blocking voltage of S 10 is 0. So the voltage stress of both S 10a and S 10b keeps to 0 during this commutation process.
Other commutation processes can be deducted similarly. To summarize, series switches only sustain E during their commutation process. Thus, the unbalancing voltage of the series switches caused by inconsistent switching actions will not exceed their rated voltage stress.
It is also noted that the multilevel voltage jumping of the output voltage would not appear in the VMC. During the commutation process between any two adjacent levels, the output voltage depends on the current direction of i o . When i o > 0, the output voltage is connected to the lower level; and when i o < 0, the output voltage is connected to the higher level. Thus, the output voltage keeps unchanged or only changes a single level in each commutation process.

Modulation Method
In this paper, phase disposition SPWM (PD-SPWM) is adopted in the VMC due to its low complexity and superior performance [19]. Figure 4 illustrates the PD-SPWM waveforms arrangement and the corresponding switching signals. Six triangular carriers (v tri1 , v tri2 , v tri3 , v tri4 , v tri5 , and v tri6 ) are compared with a reference wave (v ref ) to get control signals for switches. The peak-to-peak value of each carrier is 1/3, the peak value of output voltage is V o , then the modulation index m can be expressed as: The relationship between comparison results and switching signals are as follows: 1.
When v ref > v tri1 , S 1 is turned on and S 9 is turned off.

2.
When v ref > v tri2 , S 2 is turned on and S 10 is turned off.

3.
When v ref > v tri3 , S 3 is turned on and S 5 is turned off.

4.
When v ref > v tri4 , S 4 is turned on and S 6 is turned off.

5.
When v ref > v tri5 , S 11 is turned on and S 7 is turned off. 6.
When v ref > v tri6 , S 12 is turned on and S 8 is turned off. compared with a reference wave (vref) to get control signals for switches. The peak-to-peak value of each carrier is 1/3, the peak value of output voltage is Vo, then the modulation index m can be expressed as: The relationship between comparison results and switching signals are as follows: 1. When vref > vtri1, S1 is turned on and S9 is turned off. 2. When vref > vtri2, S2 is turned on and S10 is turned off. 3. When vref > vtri3, S3 is turned on and S5 is turned off.

Compensation Control Strategy
During each commutation process of the VMC, the dead-time is generally introduced to prevent the short-circuit of capacitors. Whereas, the dead-time, along with the switching delay and voltage drop of devices, will cause inevitable output distortion and finally deteriorate the system performance [20,21]. To solve this problem, a compensation control for the seven-level VMC is proposed in this section.

Non-Ideal Factors Analysis
The effects of the above-mentioned non-ideal factors in the VMC are discussed firstly. Referring to the analysis in Section 3, each phase can be decomposed to six half-bridge converters as the basic operation cells, as shown in Figure 5a. When the output voltage of converter changes between any two adjacent levels, it can be considered that the corresponding operation cell is shifting its higher level and lower level output. Where, S P /S N is the equivalent upper/lower switch. The output phase voltage is v o . V P and V N represent the higher level and lower level in the operation cell respectively, and Figure 5b illustrates the actual v o of the converter considering non-ideal factors. Where, G P_ref and G N_ref are the reference signals of S P and S N respectively, and G P_actual and G N_actual are the actual signals with dead-time. T is the switching period, and t r represents the duration of the positive reference signal. t d is dead-time, t on and t off are the switching turn-on and turn-off time, respectively. According to Figure 2, the expression of conduction voltage drop (V on ) is shown in Table 3, where V sat is the collector-emitter saturation voltage of switches, and V D is the diode forward voltage. Figure 5b illustrates the actual vo of the converter considering non-ideal factors. Where, GP_ref and GN_ref are the reference signals of SP and SN respectively, and GP_actual and GN_actual are the actual signals with dead-time. T is the switching period, and tr represents the duration of the positive reference signal. td is dead-time, ton and toff are the switching turn-on and turn-off time, respectively. According to Figure 2, the expression of conduction voltage drop (Von) is shown in Table 3, where Vsat is the collector-emitter saturation voltage of switches, and VD is the diode forward voltage.
For simplifying the calculation, V sat and V D are considered approximately equal here. Then the V on of each conduction path is the same and can be expressed as (3).
where V on0 represents the equivalent on-state threshold voltage of six switches, and r represents the equivalent on-resistance [5]. The direction of i o is defined as: From Figure 5b, the equivalent dead-time (t d_eq ) in one switching period can be expressed as: Based on the pulse area equal principle, the reference phase voltage (v o_ref ) and actual v o are shown as (6) and (7), respectively.
Then, the distortion of the output voltage (∆v o ) is obtained: To analyze the effects of non-ideal factors, define the instantaneous value of i o as: where I m is the amplitude of the phase current, ω is the phase angular frequency, and ϕ is the initial phase angle. From (3)-(9), the instantaneous value of ∆v o can be expressed as: It is noted that ∆v o (t) is the superposition of a square and a sinusoidal waves with a period of 2π, and they are both odd-symmetrical about axial of ωt = ϕ. Then (10) can be decomposed by Fourier transform: where As shown in (11), a fundamental variation and odd harmonics with decreasing amplitude are introduced to v o . Moreover, the value of K is independent of v o_ref , which means a serious distortion is introduced at the condition of a low modulation index. For the load voltage and current in the three-phase three-wire system as shown in Figure 1, the harmonics with 3n times of fundamental frequency are canceled out. Whereas, the fundamental variation and the harmonics with (6n ± 1) times of fundamental frequency still remain.

Compensation Control Strategy
According to the previous analysis, the non-ideal factors compensation control (NFCC) for the seven-level VMC is proposed, as shown in Figure 6. Current sensors are required to acquire the phase current. The compensation value (∆v ref ) is obtained in each switching cycle for the reference voltage (v ref ). In this way, the output distortion caused by non-ideal factors can be compensated. frequency are canceled out. Whereas, the fundamental variation and the harmonics with (6n ± 1) times of fundamental frequency still remain.

Compensation Control Strategy
According to the previous analysis, the non-ideal factors compensation control (NFCC) for the seven-level VMC is proposed, as shown in Figure 6. Current sensors are required to acquire the phase current. The compensation value ( ref v  ) is obtained in each switching cycle for the reference voltage (vref). In this way, the output distortion caused by non-ideal factors can be compensated.

Experiment Results
To verify the validity of the above-mentioned analysis and control strategy, a 7.2 kVA prototype of the three-phase seven-level VMC was designed and constructed as shown in Figure 7. Six cascaded DC power supplies with E = 120V are employed to provide DC-link input. In addition, three-phase resistors in series with inductor filter are connected in Y-style for the load of the converter. The values of Von0, r, ton, and toff can be obtained in the datasheet of switches and diodes. Other main system parameters are shown in Table 4.

Experiment Results
To verify the validity of the above-mentioned analysis and control strategy, a 7.2 kVA prototype of the three-phase seven-level VMC was designed and constructed as shown in Figure 7. Six cascaded DC power supplies with E = 120 V are employed to provide DC-link input. In addition, three-phase Energies 2019, 12, 4761 9 of 13 resistors in series with inductor filter are connected in Y-style for the load of the converter. The values of V on0 , r, t on, and t off can be obtained in the datasheet of switches and diodes. Other main system parameters are shown in Table 4. td, ton, toff

Experiment Results
To verify the validity of the above-mentioned analysis and control strategy, a 7.2 kVA prototype of the three-phase seven-level VMC was designed and constructed as shown in Figure 7. Six cascaded DC power supplies with E = 120V are employed to provide DC-link input. In addition, three-phase resistors in series with inductor filter are connected in Y-style for the load of the converter. The values of Von0, r, ton, and toff can be obtained in the datasheet of switches and diodes. Other main system parameters are shown in Table 4.   The experimental results are shown in Figures 8-12. Among them, Figures 8-11 illustrates the operation characteristics of the seven-level VMC without the NFCC. Figure 12 shows the comparison results for the NFCC.  The experimental results are shown in Figures 8-12. Among them, Figures 8-11 illustrates the operation characteristics of the seven-level VMC without the NFCC. Figure 12 shows the comparison results for the NFCC.  Figure 8 shows the output waveforms of vA and vAB. As can be seen, vA contains seven levels and vAB contains eleven levels at m = 0.86, the voltage of each level is 120 V. Each voltage ladder is clear, no multilevel voltage jumping is observed. In the zoom-in picture of vA, a voltage drop of the conduction path at state 0 can be observed. Von changes polarity with the direction of io, and its value increases with |io| from 4 V to 6.5 V.
FFT analysis of vA is illustrated in Figure 9. The total harmonic distortion (THD) is 24.4%, and most harmonics are distributed around the switching frequency. It is noted that the non-ideal factors cause a fundamental voltage loss of about 22 V (rated value is 310 V), and low order odd harmonics are also observed in the zoom-in picture. This distortion will be compensated after the NFCC is applied.    Voltage of S10a/S10b/S11a /S11b [100V/div] Figure 11. Voltage distribution of S10 and S11 (m = 0.86).
The voltage distribution of series switches S10, and S11 are shown in Figure 11. Each switch withstands static voltage of 60 V (E/2) and 120 V (E) respectively in one fundamental cycle. When the switches are turned off, the total blocking voltage of S10 or S11 is 120 V, so the dynamic voltage of the single switch caused by the switching inconsistencies will not exceed its rated value. Detailed waveforms are shown in the zoom-in picture, the voltage spike results from stray inductance are about 15 V.
The voltage distribution of series switches S10, and S11 are shown in Figure 11. Each switch withstands static voltage of 60 V (E/2) and 120 V (E) respectively in one fundamental cycle. When the switches are turned off, the total blocking voltage of S10 or S11 is 120 V, so the dynamic voltage of the single switch caused by the switching inconsistencies will not exceed its rated value. Detailed waveforms are shown in the zoom-in picture, the voltage spike results from stray inductance are about 15 V.
It can be seen from Figure 8 to Figure 11, the VMC operates well under the presented switching states and the modulation method. The dynamic voltage unbalancing in series switches and multilevel voltage jumping of the output voltage are avoided. Figure 12 illustrates the comparison results of io for the NFCC at both m = 0.2 and m = 0.86. The  compensated well by the NFCC, which means better waveforms and vector trajectory are achieved, as shown in Figure 12b,e.

Conclusions
A new seven-level V-clamp multilevel converter (VMC) is presented and implemented in this paper. From the analysis and experimental results, the following conclusions can be obtained: 1. The seven-level VMC reduces the clamping devices compared with conventional topologies. 2. With the switching states designed in this paper, the VMC is free of the issues on dynamic voltage unbalancing in series switches and multilevel voltage jumping in its output voltage. 3. With the proposed non-ideal factors compensation control, the output fundamental distortion is well compensated and the THD is reduced.
The theoretical and experimental validity of the seven-level VMC is demonstrated. This topology shows good potential for medium-voltage high-power applications.  Figure 8 shows the output waveforms of v A and v AB . As can be seen, v A contains seven levels and v AB contains eleven levels at m = 0.86, the voltage of each level is 120 V. Each voltage ladder is clear, no multilevel voltage jumping is observed. In the zoom-in picture of v A , a voltage drop of the conduction path at state 0 can be observed. V on changes polarity with the direction of i o , and its value increases with |i o | from 4 V to 6.5 V.
FFT analysis of v A is illustrated in Figure 9. The total harmonic distortion (THD) is 24.4%, and most harmonics are distributed around the switching frequency. It is noted that the non-ideal factors cause a fundamental voltage loss of about 22 V (rated value is 310 V), and low order odd harmonics are also observed in the zoom-in picture. This distortion will be compensated after the NFCC is applied. Figure 10 shows the voltage and current waveforms of the load. The high-frequency harmonics are attenuated by a filter, then good load voltage and current waveforms are achieved. The THD of the phase current is 2.24%.
The voltage distribution of series switches S 10 , and S 11 are shown in Figure 11. Each switch withstands static voltage of 60 V (E/2) and 120 V (E) respectively in one fundamental cycle. When the switches are turned off, the total blocking voltage of S 10 or S 11 is 120 V, so the dynamic voltage of the single switch caused by the switching inconsistencies will not exceed its rated value. Detailed waveforms are shown in the zoom-in picture, the voltage spike results from stray inductance are about 15 V.
It can be seen from Figure 8 to Figure 11, the VMC operates well under the presented switching states and the modulation method. The dynamic voltage unbalancing in series switches and multilevel voltage jumping of the output voltage are avoided. Figure 12 illustrates the comparison results of i o for the NFCC at both m = 0.2 and m = 0.86. The experimental results at m = 0.2 are provided in Figure 12a,c,e. The current waveforms, FFT analysis, and vector trajectory are illustrated respectively. Noted that, after the NFCC is applied, an obvious improvement of the waveform and vector trajectory can be observed in Figure 12a,e. In Figure 12c, the amplitude of the fundamental current increases from 91.0% to 100.1% of the rated value (3.6 A), the content of 5th and 7th harmonics are reduced, the THD decreases from 7.36% to 5.50%.
The comparison results at m = 0.86 are shown in Figure 12b,d,f. As seen in Figure 12d, the amplitude of the fundamental current increases from 95.1% to 99.4% of the rated value (15.5 A), and the THD decreases from 2.24% to 1.88%. The distortion caused by the non-ideal factors is compensated well by the NFCC, which means better waveforms and vector trajectory are achieved, as shown in Figure 12b,e.

Conclusions
A new seven-level V-clamp multilevel converter (VMC) is presented and implemented in this paper. From the analysis and experimental results, the following conclusions can be obtained:

1.
The seven-level VMC reduces the clamping devices compared with conventional topologies.

2.
With the switching states designed in this paper, the VMC is free of the issues on dynamic voltage unbalancing in series switches and multilevel voltage jumping in its output voltage.

3.
With the proposed non-ideal factors compensation control, the output fundamental distortion is well compensated and the THD is reduced.
The theoretical and experimental validity of the seven-level VMC is demonstrated. This topology shows good potential for medium-voltage high-power applications.