Development of an SDBC-MMCC-Based DSTATCOM for Real-Time Single-Phase Load Compensation in Three-Phase Power Distribution Systems

: This paper proposes a newly developed single-delta bridge-cell, modular multilevel cascade converter (SDBC-MMCC)-based distribution-level static synchronous compensator (DSTATCOM) for single-phase load compensation in three-phase, three-wire electric power distribution systems. Each main circuit arm of the DSTATCOM uses a modular multilevel cascade converter based on full-H-bridge (FHB) cells. The three main DSTATCOM arms are delta-connected to allow phase-independent operations for phase balancing and unity power factor correction of the single-phase load in three-phase, three-wire electric power distribution systems. By using the symmetrical components method, a feedforward compensation algorithm was employed for the DSTATCOM. A simulation of the DSTATCOM was performed for functioning veriﬁcation. Finally, a hardware test system was built by using a multi-DSP-based control system. The test results veriﬁed the e ﬀ ectiveness of the proposed SDBC-MMCC-based DSTATCOM in single-phase load compensation.


Introduction
In a three-phase electric power distribution system, a large power capacity of single-phase load (e.g., an electrical railway traction system) absorbs unbalanced (negative-sequence) load current and reactive power. The unbalanced load current produces an unbalanced voltage drop on the electric power distribution line. The resulting unbalanced voltage affects other sensitive loads connected to the distribution system. For example, AC rotary machines will induce extra losses, and rectifier loads will generate ripples in their DC links. Moreover, the unbalanced current will disturb the normal operation of an electric power generator. To keep good power quality, the unbalanced current from the single-phase load should be improved [1,2].
Traditionally, the delta connection of passive inductive/capacitive reactances, also known as a "Steinmetz compensator", was employed for single-phase load compensations in three-phase power systems [3][4][5]. The operation principle of the Steinmetz compensator has been used in many applications of unbalanced load compensations [6]. Presently, static var compensators (SVC) are widely used in the load compensations of high-power, single-phase traction systems [7][8][9]. The thyristor-controlled reactor with fixed capacitor (TCR-FC) type of SVC is applied in these traction systems. A drawback of the TCR-FC type of SVC is that it demands large space for installation. Two-level converters can also Figure 1 illustrates the study system for deriving the DSTATCOM compensation algorithm. A shunt type of DSTATCOM is installed for the on-site single-phase load compensation. The feedforward compensation algorithm detects the load power parameters, P L ab and Q L ab , and sends three reactive power compensation commands, Q ST * ab,bc,ca , to the DSTATCOM's main circuit arms. The three DSTATCOM arms independently regulate their reactive power inputs, then the synthesized DSTATCOM line current compensates the unbalanced single-phase load current. Consequently, the source currents are balanced with a unity power factor. Using the symmetrical components method, we derived the feedforward compensation algorithm. Figure 2 shows the phase-sequence circuits of Figure 1. systems. A drawback of the TCR-FC type of SVC is that it demands large space for installation. Twolevel converters can also be used for single-phase load compensations in three-phase power systems [10][11][12]. However, the power ratings of two-level converters are limited.
Recently, static synchronous compensators (STATCOMs) have been introduced as the nextgeneration shunt compensators [13][14][15][16]. Compared to traditional SVCs, STATCOMs have quicker response times, more compact structures, wider compensation ranges, and smaller installation space demand. Therefore, distribution-level static synchronous compensators (DSTATCOMs) are highly suitable for unbalanced load compensations in modern three-phase electric power distribution systems. Various types of converters can be employed to construct the main circuit of a DSTATCOM. Due to lower voltage stress and modular structure, single-delta bridge-cell, modular multilevel cascade converters (SDBC-MMCCs) are very suitable for the main circuits of DSTATCOMs in highvoltage and high-power applications [17][18][19][20]. Hence, the SDBC-MMCC-based DSTATCOMs can replace the SVCs in single-phase load compensations.
In this paper, a new concept of applying an SDBC-MMCC-based DSTATCOM for real-time single-phase load compensation in a three-phase, three-wire power distribution system is proposed. Applications of multilevel full-H-bridge (FHB) converters and staircase modulation in the DSTATCOM main circuit can achieve high-efficiency operation in practical applications. A feedforward compensation algorithm derived from the symmetrical components method was designed for the DSTATCOM, which was constructed using the MATLAB/SimuLink program for preliminary verification. Finally, a hardware prototype test system was built using a multi-TMS320F2812 digital signal processor (DSP)-based control system. Experimental results show that the proposed SDBC-MMCC-based DSTATCOM has a rapid response and a satisfactory compensation effect. This paper is a further development of the SDBC-MMCC-based DSTATCOM for three-phase unbalanced load compensation that we previously described [21]. In single-phase load compensation, the control algorithm of the DSTACOM is more compact, and the sizing of the DSTATCOM is more precisely defined. , to the DSTATCOM's main circuit arms. The three DSTATCOM arms independently regulate their reactive power inputs, then the synthesized DSTATCOM line current compensates the unbalanced single-phase load current. Consequently, the source currents are balanced with a unity power factor. Using the symmetrical components method, we derived the feedforward compensation algorithm. Figure 2 shows the phase-sequence circuits of Figure 1.  Three-phase, three-wire power distribution system with single-phase load and distribution-level static synchronous compensator (DSTATCOM).

DSTATCOM Load Compensation Algorithm
Equation (3) can be rewritten as rectangular forms, as indicated in Equations (4) and (5). The zero-sequence component of the load current is zero. Equation (6) gives the three arm currents of the DSTATCOM, where the relationship of is used. Equation (7) shows the DSTATCOM line currents. Using the symmetrical components transformation in Equation (8), Equation (9) shows the symmetrical components of the DSTATCOM line current in terms of the reactive power flows of the three DSTATCOM arms. For a DSTATCOM with a delta-connected main circuit, the zerosequence current, 0 ST I , in Equation (8) Equation (3) can be rewritten as rectangular forms, as indicated in Equations (4) and (5). The zero-sequence component of the load current is zero. Equation (6) gives the three arm currents of the DSTATCOM, where the relationship of V * ·I = P − jQ is used. Equation (7) shows the DSTATCOM line currents. Using the symmetrical components transformation in Equation (8), Equation (9) Energies 2019, 12, 4705

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As shown in Figure 2, for the single-phase load compensation, the DSTATCOM should compensate the entire negative-sequence component and imaginary part of the positive-sequence component currents generated by the single-phase load, as revealed in Equation (10) [21,22]. The source current only supplies the real part of the positive-sequence load current. As a result, with the assistance of the DSTATCOM compensation, the source current is balanced with a unity power factor.
Finally, combining Equations (4), (5) and (9), (10), we obtained the required load compensation algorithm of each DSTATCOM arm for real-time single-phase load compensation, as indicated by Equation (11). Equation (11) is very compact and suitable for the SDBC-MMCC-based DSTATCOM. The sizing of the DSTATCOM can easily be calculated using Equation (11). The DSTATCOM is treated as a reactive power load in the compensation. The reactive power flow of each DSTATCOM arm, which can be inductive or capacitive, is independently controlled by the compensation algorithm in Equation (11). By using power calculation definitions, P = ( T i·v dt)/T and Q = (− T i·v(π/2)dt)/T, in the time domain, Equation (12) shows another version of Equation (11) for the DSATCOM, where T is the period of the fundamental frequency. Equation (12) can easily be digitized and implemented in a digital controller. Finally, Equation (13) shows the three-phase source current with DSTATCOM compensation. Figure 3 shows a three-phase power distribution system, a single-phase load, and the proposed seven-level, SDBC-MMCC-based DSTATCOM as the test system in the paper. Each STATCOM arm consists of an internal voltage source, V ST , modulated by a seven-level, cascade full-H-bridge converter and a commutation reactor, X ST . In this study, each DSTATCOM arm is equivalent to a purely reactive power load.

DSTATCOM Main Circuit
The reactive power flows of these three DSTATCOM arms are regulated independently for the single-phase load compensation. The power inputs of each DSTATCOM arm in Figure 3 are expressed in Equations (14) and (15), respectively. An indirect phasor-domain power angle regulation method is used for the reactive power control in the DSTATCOM. For a reactive power demand, the DSTATCOM controller regulates the power angle, δ ST , to absorb or release the active power from the power source according to Equation (14). The active power flow charges or discharges the DC-link capacitors and then regulates the DC-link voltages. Finally, the cascaded DC-link voltages synthesize the internal voltage, V ST , then the DSTATCOM absorbs capacitive or inductive reactive power according to Equation (15). When the reactive power response is completed, the power angle returns to near-zero values. With the delta-connected main circuit, the three DSTATCOM arms achieve phase-independent operation. Hence, much like a traditional SVC, the DSTATCOM can easily compensate the unbalanced load current and correct the power factor caused by a single-phase load.  The reactive power flows of these three DSTATCOM arms are regulated independently for the single-phase load compensation. The power inputs of each DSTATCOM arm in Figure 3 are expressed in Equations (14) and (15), respectively. An indirect phasor-domain power angle regulation method is used for the reactive power control in the DSTATCOM. For a reactive power demand, the DSTATCOM controller regulates the power angle, ST δ , to absorb or release the active power from the power source according to Equation (14). The active power flow charges or discharges the DC-link capacitors and then regulates the DC-link voltages. Finally, the cascaded DClink voltages synthesize the internal voltage, ST V , then the DSTATCOM absorbs capacitive or inductive reactive power according to Equation (15). When the reactive power response is completed, the power angle returns to near-zero values. With the delta-connected main circuit, the three DSTATCOM arms achieve phase-independent operation. Hence, much like a traditional SVC, the DSTATCOM can easily compensate the unbalanced load current and correct the power factor caused by a single-phase load.
A typical staircase modulation scheme, depicted in Figure 4, enables the DSTATCOM main circuit to operate with high efficiency. Each level and internal voltage waveform of the DSTATCOM arm a-b in Figure 3 are also shown [21]. The internal voltage ST v shows a staircase waveform. The three switching angles, 1 θ -3 θ , should be determined to minimize the harmonics generated. The Figure 4 can be represented as a Fourier series, as detailed in Equation (16), where n is the harmonic order ( 1, 3, 5, 7,... n = ). Ideally, the harmonic order contains only odd-order components. Equation (17) shows the harmonic components in Equation (16). A typical staircase modulation scheme, depicted in Figure 4, enables the DSTATCOM main circuit to operate with high efficiency. Each level and internal voltage waveform of the DSTATCOM arm a-b in Figure 3 are also shown [21]. The internal voltage v ST shows a staircase waveform. The three switching angles, θ 1 -θ 3 , should be determined to minimize the harmonics generated. The internal voltage v ST in Figure 4 can be represented as a Fourier series, as detailed in Equation (16), where n is the harmonic order (n = 1, 3, 5, 7, . . .). Ideally, the harmonic order contains only odd-order components. Equation (17) shows the harmonic components in Equation (16).
Energies 2019, 12, x FOR PEER REVIEW 6 of 16 [ ] In Equation (17), setting n = 1 produces the fundamental component H (1), which consists of the DC-link voltage V dc and three switching angles, θ 1 -θ 3 . The fundamental component H(1) is used for the reactive power regulation. To eliminate the specified harmonic orders, a harmonic-minimizing method is used [23]. Assigning H(1) = 3V dc for the fundamental-component modulation and setting H(5) = H(7) = 0 for the 5th and 7th orders' harmonic cancellation produces Equation (18). Subsequently, solving Equation (18) results in the required switching angles, namely, θ 1 = 11.68 cos(θ 1 ) + cos(θ 2 ) + cos(θ 3 ) = 3π/4 cos(5θ 1 ) + cos(5θ 2 ) + cos(5θ 3 ) = 0 cos(7θ 1 ) + cos(7θ 2 ) + cos(7θ 3 ) = 0 (18) Figure 5 depicts the functional block diagram of the DSTATCOM controller proposed in this paper. As noted, the control algorithm using Equation (11) calculates the required reactive power values of the three DSTATCOM arms in real time. Three well-tuned proportional integral derivative (PID) feedback controllers in the inner loops regulate the reactive power inputs of the three DSTATCOM arms independently, as shown in Equation (19). The three output commands of the PID controllers, δ ST * ab,bc,ca , generate the gating signals, as shown in Figure 4 for these switching elements in the three DSTATCOM arms. With the proposed controller shown in Figure 5, the DSTATCOM completes the single-phase load compensation in real time. The DSTATCOM controller in Figure 5 requires a fast power detection method. Figure 6 schematizes the fast calculation method of active and reactive powers that applies the single-phase α − β reference axis method. Applying this fast calculation results in the load power values for Equation (11) Figure 6. Fast power calculation method.   Figure 5. The proposed DSTATCOM controller. Figure 6. Fast power calculation method. Figure 7 shows the simulation system, which was developed in the MATLAB/SimuLink program for a preliminary verification of the proposed DSTATCOM. A single-phase inductive load was used in the testing. First, the DSTATCOM main circuit was built according to Figure 3. In the simulation, the switch (SW) in Figure 7 was closed at t = 0.605 s to make a step response caused by the single-phase load. With the setting, the transient and steady-state performances of the DSTATCOM compensation were observed from the simulation results. Appendix A lists the system parameters.  Figure 7 shows the simulation system, which was developed in the MATLAB/SimuLink program for a preliminary verification of the proposed DSTATCOM. A single-phase inductive load was used in the testing. First, the DSTATCOM main circuit was built according to Figure 3. In the simulation, the switch (SW) in Figure 7 was closed at t = 0.605 s to make a step response caused by the single-phase load. With the setting, the transient and steady-state performances of the DSTATCOM compensation were observed from the simulation results. Appendix A lists the system parameters.  Figure 8a shows the transient load current response. With the assistance of the DSTATCOM, the three-phase source current was corrected to be balanced with a unity power factor, as shown in Figure 8b. Figure 8c depicts the synthesized line current of the DSTATCOM. Figures 8d and 8e show the power flows from the power source to the load, which reveal that the DSTATCOM very rapidly compensated the reactive power demand of the load. Figure  9 shows the compensation response in the DSTATCOM. Figure 9a is a recording of the internal voltage responses in the three DSTATCOM arms. When the single-phase load was switched in, the three DSTATCOM arms changed to phase-independent operation, as shown in Figure 9a Figure 8a shows the transient load current response. With the assistance of the DSTATCOM, the three-phase source current was corrected to be balanced with a unity power factor, as shown in Figure 8b. Figure 8c depicts the synthesized line current of the DSTATCOM. Figure 8d,e show the power flows from the power source to the load, which reveal that the DSTATCOM very rapidly compensated the reactive power demand of the load. Figure 9 shows the compensation response in the DSTATCOM. Figure 9a is a recording of the internal voltage responses in the three DSTATCOM arms. When the single-phase load was switched in, the three DSTATCOM arms changed to phase-independent operation, as shown in Figure 9a,b. Figure 9c-e reveal other DSTATCOM responses in the single-phase load compensation for reference.

Simulation Verification
The simulation results in Figures 8 and 9 clearly indicate that the proposed DSTATCOM discussed in this paper is suitable for single-phase load compensation. It is also observed that the unbalanced operation of the three DSTATCOM arms produce high-order harmonic currents. The harmonic currents tend to flow into the system and aggravate the electric power quality. An adequate front-end filter can be installed to lessen the harmonic current pollution. Increasing the cascade numbers of the FHB cells in the DSTATCOM main circuit can markedly reduce the high-order harmonic currents. with a unity power factor, as shown in Figure 8b. Figure 8c depicts the synthesized line current of the DSTATCOM. Figures 8d and 8e show the power flows from the power source to the load, which reveal that the DSTATCOM very rapidly compensated the reactive power demand of the load. Figure  9 shows the compensation response in the DSTATCOM. Figure 9a is a recording of the internal voltage responses in the three DSTATCOM arms. When the single-phase load was switched in, the three DSTATCOM arms changed to phase-independent operation, as shown in Figure 9a  The simulation results in Figures 8 and 9 clearly indicate that the proposed DSTATCOM discussed in this paper is suitable for single-phase load compensation. It is also observed that the unbalanced operation of the three DSTATCOM arms produce high-order harmonic currents. The harmonic currents tend to flow into the system and aggravate the electric power quality. An adequate  Figure 11 shows the hardware prototype test system constructed in the laboratory, and Appendix B lists the system parameters used. A single-phase load was used for verification testing in the physical experiment. The SDBC-MMCC-based DSTATCOM main circuit had a seven-level, transformerless configuration with a delta connection. In the hardware implementation of the DSTATCOM main circuit, insulated-gate bipolar transistors (IGBTs) were used. The DSTATCOM controller was a multi-TMS320F2812 DSP-based system with a sampling time of 0.52 ms to digitize the three PID controllers in Figure 5. The control program in the multi-DSP-based controller was first developed in C language on a host PC. The execution file was downloaded to the multi-DSP-based controller through Joint Test Action Group (JTAG) data links. Two multi-channel digital scopes were employed to record the transient responses of the DSTATCOM. During the DSTATCOM operation, some selected on-line calculation results in the controller were sent to the host PC for further evaluation.   Figure 11 shows the hardware prototype test system constructed in the laboratory, and Appendix B lists the system parameters used. A single-phase load was used for verification testing in the physical experiment. The SDBC-MMCC-based DSTATCOM main circuit had a seven-level, transformerless configuration with a delta connection. In the hardware implementation of the DSTATCOM main circuit, insulated-gate bipolar transistors (IGBTs) were used. The DSTATCOM controller was a multi-TMS320F2812 DSP-based system with a sampling time of 0.52 ms to digitize the three PID controllers in Figure 5. The control program in the multi-DSP-based controller was first developed in C language on a host PC. The execution file was downloaded to the multi-DSP-based controller through Joint Test Action Group (JTAG) data links. Two multi-channel digital scopes were employed to record the transient responses of the DSTATCOM. During the DSTATCOM operation, some selected on-line calculation results in the controller were sent to the host PC for further evaluation.   Figure 11 shows the hardware prototype test system constructed in the laboratory, and Appendix B lists the system parameters used. A single-phase load was used for verification testing in the physical experiment. The SDBC-MMCC-based DSTATCOM main circuit had a seven-level, transformerless configuration with a delta connection. In the hardware implementation of the DSTATCOM main circuit, insulated-gate bipolar transistors (IGBTs) were used. The DSTATCOM controller was a multi-TMS320F2812 DSP-based system with a sampling time of 0.52 ms to digitize the three PID controllers in Figure 5. The control program in the multi-DSP-based controller was first developed in C language on a host PC. The execution file was downloaded to the multi-DSP-based controller through Joint Test Action Group (JTAG) data links. Two multi-channel digital scopes were employed to record the transient responses of the DSTATCOM. During the DSTATCOM operation, some selected on-line calculation results in the controller were sent to the host PC for further evaluation. . Functional block diagram of the DSTATCOM hardware prototype test system. Figure 11. Functional block diagram of the DSTATCOM hardware prototype test system. Figures 12 and 13 reveal the hardware experimental results. Figure 12 shows the current responses with DSTATCOM compensation. In Figure 12a, the switching-in of the single-phase load created an unbalanced operation. The single-phase load operation requires active power with a lagging power factor. Figure 12b illustrates the source current response; the phase-a-to-ground voltage waveform was recorded at the same time for reference. With the real-time compensation of the DSTATCOM, the source current was corrected very quickly to be balanced with a unity power factor. Figure 12c shows the transient response of the synthesized DSTATCOM line current in the compensation. Table 1 records the steady-state DSTATCOM compensation result in Figure 12. The current unbalanced ratio I UR (%), expressed in Equation (20) indicates the effect of current balancing in the power source. The unbalanced ratio of the load current, I L UR (%), was 100%. With DSTATCOM compensation, the unbalanced ratio of the source current, I S UR (%), was substantially improved to a nearly perfect value of 3.26%.  Figure 12 shows the current responses with DSTATCOM compensation. In Figure 12a, the switching-in of the single-phase load created an unbalanced operation. The single-phase load operation requires active power with a lagging power factor. Figure 12b illustrates the source current response; the phase-a-to-ground voltage waveform was recorded at the same time for reference. With the real-time compensation of the DSTATCOM, the source current was corrected very quickly to be balanced with a unity power factor. Figure 12c shows the transient response of the synthesized DSTATCOM line current in the compensation. Table 1 records the steady-state DSTATCOM compensation result in Figure 12. The current unbalanced ratio   Figure 13 shows other responses in the DSTATCOM main circuit. The three DSTATCOM arms changed to phase-independent operation when the single-phase load was switched in. The physical test results agreed with the simulation results presented in Figure 9. The transient compensation response of the DSTATCOM was quite fast. The delta-connected DSTATCOM main circuit and the harmonics-minimizing method eliminated the specified harmonic components in the synthesized   Figures 13b,c. However, high-order harmonic currents were unavoidably generated in the three DSTATCOM arms. The hardware experimental results verified that the proposed SDBC-MMCC-based DSTATCOM is suitable for real-time phase balancing and power factor correction of single-phase loads in threephase, three-wire power distribution systems.   Figure 13 shows other responses in the DSTATCOM main circuit. The three DSTATCOM arms changed to phase-independent operation when the single-phase load was switched in. The physical test results agreed with the simulation results presented in Figure 9. The transient compensation response of the DSTATCOM was quite fast. The delta-connected DSTATCOM main circuit and the harmonics-minimizing method eliminated the specified harmonic components in the synthesized DSTATCOM line currents, as shown in Figure 13b,c. However, high-order harmonic currents were unavoidably generated in the three DSTATCOM arms.

Hardware Experimental Results
The hardware experimental results verified that the proposed SDBC-MMCC-based DSTATCOM is suitable for real-time phase balancing and power factor correction of single-phase loads in three-phase, three-wire power distribution systems.

Conclusion
In a three-phase, three-wire electric power distribution system, a newly designed SDBC-MMCC-based DSTATCOM employing staircase modulation and an indirect phasor-domain power angle regulation method for real-time single-phase load compensation was studied. An effective feedforward compensation algorithm was proposed for the DSTATCOM. The computer simulation results showed that the function of the proposed DSTATCOM was quite satisfactory. Finally, a hardware test system was built for functional verification. The proposed DSTATCOM showed a fast transient response and a satisfactory steady-state compensation effect. However, the simulation and experimental results also revealed that unbalanced operation of the DSTATCOM induced unbalanced harmonic currents in the three DSTATCOM arms. Thus, in practical applications, harmonic filters should be installed to enhance the electric power quality. Increasing the cascade numbers of the FHB cells in each DSTATCOM main circuit arm can also reduce undesired harmonic currents.
Author Contributions: W.-N.C. conceived this paper and composed the study system; C.-H.L. conducted the theoretical study, computer simulation, and hardware implementation; all authors wrote the paper.

Funding:
The financial support from the Ministry of Science and Technology (MOST), Taiwan, is acknowledged.
Acknowledgments: Valuable comments and discussions from the reviewers are appreciated.

Conflicts of Interest:
The authors declare no conflict of interest.