Control for Three-Phase LCL-Filter PWM Rectiﬁer with BESS-Oriented Application

: This paper deals with a battery energy storage system (BESS) in only one of its multiple operating modes, that is when the BESS is charging the battery bank and with the focus on the control scheme design for the BESS input stage, which is a three-phase LCL-ﬁlter PWM rectiﬁer. The rectiﬁer’s main requirements comprise output voltage regulation, power factor control, and low input current harmonic distortion, even in the presence of input voltage variations. Typically, these objectives are modeled by using a dq model with its corresponding two-loop controller architecture, including an outer voltage loop and a current internal loop. This paper outlines an alternative approach to tackle the problem by using not only an input–output map linearization controller, with the aim of a single-loop current control, but also by avoiding the dq modeling. In this case, the voltage is indirectly controlled by computing the current references based on the converter power balance. The mathematical model of the three-phase LCL-ﬁlter PWM rectiﬁer is deﬁned based on the delta connection of the ﬁlter, which accomplishes the requirements of a 100 kW BESS module. Extensive simulation results are included to conﬁrm the performance of the proposed closed-loop control in practical applications.


Introduction
The three-phase PWM voltage source rectifiers are broadly used in several industrial applications, such as battery energy storage systems (BESSs), which have been firmly increasing in installed power worldwide since 2015 [1][2][3][4]. Actually, as a starting background, a BESS must work in current and voltage control modes either for discharging energy to the grid or charging the battery bank [2]. Until now, this implies the use of several control-loops for complying with the battery-tied and the grid-tied requirements, which are typically carried out by two front-end converters (dc-dc and dc-ac) [2]. Concerning the PWM rectifier, the converter is widely used due to its well-known technical features: dc bus voltage regulation, near unity power factor, and sinusoidal currents with low total harmonic distortion (THD) as well [5][6][7][8].
To reduce high-frequency harmonic contents, according to the international standards such as IEEE519 and IEC 1000-3-2, the PWM rectifier is connected to the grid through an LCL filter for medium power applications. This type of filter leads not only to better mitigation of switching harmonics with lower inductances but also allows compliance with the voltage and current control modes when the converter delivers energy to the grid [9][10][11][12].
Regarding the rectifier mode operation, the most common control architecture found in the literature consists of two control loops (voltage and current) using PI or nonlinear controllers applying abc-dq-abc transformations [13][14][15][16][17]. In contrast, there are other control techniques for three-phase useful in placing the BESS as needed in the grid, the latter refers to connecting parallel modules (in a container) to typically reach a rated power from 1 MW to 2 MW depending on the battery technology [1, 2,26]. The modular topology presented in [26,31] (see Figure 1) is a suitable option for a medium power rating. The BESS comprises two main power stages: the dc-dc stage fulfills the battery bank requirements, while the dc-ac stage accomplishes the utility requirements through the LCL filter. The LCL filter is mainly designed to comply with the harmonic requirements when the BESS works as a load and as a power source, but it also allows the BESS to operate as a current source or as a voltage source. Nonetheless, there are some filter design constraints to consider, such as total impedance, current ripple through inductors, reactive power absorbed by filter capacitors, and resonance [10][11][12].
Furthermore, when the BESS delivers energy to the grid, the LCL filter is in delta connection because the battery bank voltage reference imposes how the dc bus voltage feeds the dc-ac stage [26]. This power stage works as a three-phase PWM rectifier to feed the dc-dc stage for charging the battery bank. For this purpose, the rectifier boosts the input voltages ( , , and ) to the dc bus voltage ; besides, the input currents ( , , and ) are indirectly controlled through the inductor currents ( , , and ) of each to fulfill the grid requirements. These grid-tied inductors are designed with a slight voltage drop so that the capacitor voltages ( , , and ) are similar to the input voltages [32]. Finally, the dc bus current is the result of each rectifier-tied inductor current ( , , and ). As a result, the mentioned characteristics define the converter topology to model.

Phase-Phase PWM Rectifier Model
Two considerations are established to analyze the three-phase PWM rectifier of Figure 1: • Assume that represents the combined battery bank and dc-dc converter dynamics. Hence, is computed with the sensed delivered current and the sensed output voltage, as specified in Equation (1). This consideration is valid due to the decoupling capacitor that allows the modeling of each power stage separately. • Full-bridge converter model, formed by the line-to-line , is obtained. This consideration is given for a considered three-phase balanced system where the converter and its voltage sensors are naturally delta-connected.
The corresponding switching states that generate the output voltage = − are shown in Table 1  The LCL filter is mainly designed to comply with the harmonic requirements when the BESS works as a load and as a power source, but it also allows the BESS to operate as a current source or as a voltage source. Nonetheless, there are some filter design constraints to consider, such as total impedance, current ripple through inductors, reactive power absorbed by filter capacitors, and resonance [10][11][12].
Furthermore, when the BESS delivers energy to the grid, the LCL filter is in delta connection because the battery bank voltage reference imposes how the dc bus voltage feeds the dc-ac stage [26]. This power stage works as a three-phase PWM rectifier to feed the dc-dc stage for charging the battery bank. For this purpose, the rectifier boosts the input voltages (v AB , v BC , and v CA ) to the dc bus voltage V DC ; besides, the input currents (i AB , i BC , and i CA ) are indirectly controlled through the inductor currents (i A , i B , and i A ) of each L f 2 to fulfill the grid requirements. These grid-tied inductors are designed with a slight voltage drop so that the capacitor voltages (v cAB , v cBC , and v cCA ) are similar to the input voltages [32]. Finally, the dc bus current I DC is the result of each rectifier-tied inductor current (i a , i b , and i c ). As a result, the mentioned characteristics define the converter topology to model.

Phase-Phase PWM Rectifier Model
Two considerations are established to analyze the three-phase PWM rectifier of Figure 1: • Assume that Z load represents the combined battery bank and dc-dc converter dynamics. Hence, Z load is computed with the sensed delivered current i load and the sensed output voltage, as specified in Equation (1). This consideration is valid due to the decoupling capacitor C DC that allows the modeling of each power stage separately.

•
Full-bridge converter model, formed by the line-to-line v AB , is obtained. This consideration is given for a considered three-phase balanced system where the converter and its voltage sensors are naturally delta-connected.
The corresponding switching states that generate the output voltage v ab = v a − v b are shown in Table 1. The switching states sw 1 and sw 2 , which are, respectively, associated with Q 1 and Q 3 , simplify the model analysis by stating: v AB = V DC (sw 1 − sw 2 ) and I DC(ab) = i ab (sw 1 − sw 2 ), where sw 1 , and sw 2 ∈ {1, 0} are the switching functions and the dc bus current I DC(ab) is formed with the corresponding current phases (i a and i b ).
Besides, the input current i AB in the delta connected source is computed with Equation (2), based on the sensed current at each inductor L f 2 .
The previous considerations lead to the equivalent phase-phase circuit model of Figure 2, where d 1 , d 2 ∈ (0,1) are the averaged functions of sw 1 and sw 2 , respectively, and d 12 = d 1 − d 2 ∈ (−1, 1). Current i AB = (i A − i B )/3, and the dc bus current is given by the function d 12 i ab where i ab = i a − i b .   I  0  1  0  1  1  1  0  0  II  0  1  1  0  0  1  −  −   III  1  0  0  1  1  0  IV  1  0  1  0  0  0  0  0 Besides, the input current in the delta connected source is computed with Equation (2), based on the sensed current at each inductor .
The previous considerations lead to the equivalent phase-phase circuit model of Figure 2, where , ∈ (0,1) are the averaged functions of and , respectively, and = − ∈ (−1, 1). Current = ( − )/3, and the dc bus current is given by the function By analyzing the bold circuit with Kirchhoff's voltage and current laws (KVL and KCL, respectively), the mathematical model is expressed in Equation (3). The first and the second expressions describe the KVL for loops one and two, where the source current and the current through inductors are obtained as state variables, respectively. Similarly, the third and the fourth expressions describe the KCL at nodes one and two, where the capacitor voltage and the dc bus voltage are obtained as state variables, respectively. cAB Defining = ( )' as the state variables of ( )', respectively and the lineto-line control as = ; then, the corresponding state-space system in matrix form is shown in Equation (4).
The state-space system can be expressed in its input-affine nonlinear form = ( ) + ( ) , which is described in Equation (5). By analyzing the bold circuit with Kirchhoff's voltage and current laws (KVL and KCL, respectively), the mathematical model is expressed in Equation (3). The first and the second expressions describe the KVL for loops one and two, where the source current i AB and the current through inductors L f 2 are obtained as state variables, respectively. Similarly, the third and the fourth expressions describe the KCL at nodes one and two, where the capacitor voltage v cAB and the dc bus voltage V DC are obtained as state variables, respectively.
Defining x = ( x 1 x 2 x 3 x 4 )' as the state variables of (i AB i ab v cAB V DC )', respectively and the line-to-line control as d 12 = u ab ; then, the corresponding state-space system in matrix form is shown in Equation (4).
The state-space system can be expressed in its input-affine nonlinear form In this research paper, all sensors are considered available to obtain the physical variables for the control loop, since these sensors are typically used in a power converter. Besides, the sinusoidal PWM (SPWM) technique is considered due to its simplicity to prove the proposed control.

Nonlinear Control Design Based on Input-Output Map Linearization
The control scheme is developed using the line-to-line model. Its merit lies in the opportunity to avoid abc-dq-abc transformations and double control loops. Hence, to pinpoint the control design, the control objectives should be considered:

•
To regulate the dc bus voltage for a given duty cycle, even with input voltage variations.

•
To produce a low-harmonic distortion of the input current signal. In this case, the THD should be lower than 5%.

•
To accomplish a near unity input power factor. For this task the current i AB must track the input voltage v AB .
The first objective, which is naturally the main function of the rectifier itself, is a sufficient task because the converter acts as a voltage source for the dc-dc stage that should be designed to withstand input voltage disturbances. In contrast, the other two control objectives are needed to comply with the power quality requirements described in IEEE-519. These control objectives are achieved with the proposed control scheme of Figure 3. It mainly consists of a single-loop nonlinear controller and a current reference generator.
( ) In this research paper, all sensors are considered available to obtain the physical variables for the control loop, since these sensors are typically used in a power converter. Besides, the sinusoidal PWM (SPWM) technique is considered due to its simplicity to prove the proposed control.

Nonlinear Control Design Based on Input-Output Map Linearization
The control scheme is developed using the line-to-line model. Its merit lies in the opportunity to avoid abc-dq-abc transformations and double control loops. Hence, to pinpoint the control design, the control objectives should be considered: • To regulate the dc bus voltage for a given duty cycle, even with input voltage variations.

•
To produce a low-harmonic distortion of the input current signal. In this case, the THD should be lower than 5%.

•
To accomplish a near unity input power factor. For this task the current must track the input voltage .
The first objective, which is naturally the main function of the rectifier itself, is a sufficient task because the converter acts as a voltage source for the dc-dc stage that should be designed to withstand input voltage disturbances. In contrast, the other two control objectives are needed to comply with the power quality requirements described in IEEE-519. These control objectives are achieved with the proposed control scheme of Figure 3. It mainly consists of a single-loop nonlinear controller and a current reference generator. To compute the current reference, the power balance between the ac side and the dc side is considered. Then, by matching the input power described by Equation (6) to the output power described by Equation (7), the peak current * can be obtained, as shown in Equation (8), where is the peak grid voltage, * is the desired dc bus voltage, and * is the load current computed with from Equation (1) as * = * / . To compute the current reference, the power balance between the ac side and the dc side is considered. Then, by matching the input power P AC described by Equation (6) to the output power P DC described by Equation (7), the peak current I * p can be obtained, as shown in Equation (8), where V p is the peak grid voltage, V * DC is the desired dc bus voltage, and i * load is the load current computed with Z load from Equation (1) as i * load = V * DC /Z load .
Given I * p , the instantaneous current reference i * AB is computed with Equation (9), where the reference must be in phase (φ) with the line-to-line voltage v AB to approach a unitary power factor.
The tracking problem is solved with the control law u ab by using the input-output map linearization of Equation (4) to simplify the analysis. The bilinear system has a relative degree of ρ = 3 with h( x) = x 1 , so that its diffeomorphism T AB ( x) is defined in Equation (10), where L i f h( x) is the i-th derivative of Lie and φ( x) satisfies L φ g( x) = 0 and g(0) = 0. The normal form is given in Equation (11), which is obtained with Equation (10), where η ∈ R and ξ ∈ R 3 .
The internal dynamics is restricted to As a result, the zero dynamics is described by Equation (12), which is asymptotically stable for Z load > 0 and C DC > 0. .
By defining e = h(x) − r AB and assuming that: • The current reference r AB and its derivatives up to ... r AB are bounded for all t ≥ 0 and ... r AB is a piecewise continuous function of t, and • The signals r AB , . . . , ... r AB are available online, the external dynamics can be linearized by using the control law (Equation (13)).

r AB
T ρ AB the last ρ components of the diffeomorphism.

Modeling and Control for Three-Phase PWM Rectifier
The strategy of using the line-to-line model to tune the nonlinear control gains leads to computing vector K 1X3 , for solving the tracking problem, instead of computing a matrix K 3X9 for the three-phase model. For analyzing the three-phase rectifier, the following model based on the extension of (4) is considered: where (x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 )' are defined as the state variables of (i AB i BC i CA i ab i bc i ca v cAB v cBC v cCA V DC )' respectively, and: For the three-phase rectifier control, and its relative grade vector as ρ = (3 3 3), let T ρ AB , T ρ BC , and T ρ CA be the last ρ components of the diffeomorphism for each line-to-line voltage sub-circuit described as: Then, the diffeomorphism of the three-phase PWM rectifier is described in Equation (15).
The internal dynamics is restricted to z As a result, the zero dynamics is described by Equation (16), which is asymptotically stable for Z load > 0 and C DC > 0. .
Therefore, the line-to-line control can be computed with Equations (17)- (19) for the three-phase rectifier by considering the corresponding voltages and current references.
u BC = L f 1 x 10 u CA = L f 1 x 10 where

r CA
An integral controller is included, in the nonlinear control block of Figure 3, to provide robustness to the system concerning constant parametric uncertainties that could be in the converter itself, such as parasitics and disturbances in the grid, such as voltage variations. Then, the control laws result in: x 10 u CA = L f 1 x 10 The control objective can be met by the design of the gain values (K k i ) = K for the extended system, such that the matrix A − BK is Hurwitz (or stable) where A and B are defined in Equation (23) with A c and B c as the canonical representation of the ρ integrators. The tracking control problem, now converted into a stabilization one, is reduced to a problem of designing the K values to assign every eigenvalue with a strictly negative real part and place them in the open left-half complex plane [33].
For the gain selection, the topology physical limitations should be considered given that, even with nonlinear controllers, the established objectives cannot be achieved if these limitations are exceeded. In summary, the procedure of the control design is described in Figures 4 and 5. robustness to the system concerning constant parametric uncertainties that could be in the converter itself, such as parasitics and disturbances in the grid, such as voltage variations. Then, the control laws result in: The control objective can be met by the design of the gain values ( ) = for the extended system, such that the matrix − is Hurwitz (or stable) where and are defined in Equation (23) with and as the canonical representation of the integrators. The tracking control problem, now converted into a stabilization one, is reduced to a problem of designing the values to assign every eigenvalue with a strictly negative real part and place them in the open lefthalf complex plane [33].
For the gain selection, the topology physical limitations should be considered given that, even with nonlinear controllers, the established objectives cannot be achieved if these limitations are exceeded. In summary, the procedure of the control design is described in Figures 4 and 5.

Simulation Results
In this section, the main simulation results are presented to point out the control effectiveness in complying with the rectifier requirements, which are shown in Table 2 [34]. Additionally, the passive devices are sized for a 100 kW module, which is a common power rating for BESS applications [1]. The simulated system is shown in Figure 6 where the required sensed signals, according to variables of Figure 1, are pointed out for computing the current references and the nonlinear control. According to Figure 4, a parameterization with respect to the highest value of is considered, as described in Equation (23), for , and a similar consideration is done for the other control laws.
 

Simulation Results
In this section, the main simulation results are presented to point out the control effectiveness in complying with the rectifier requirements, which are shown in Table 2 [34]. Additionally, the passive devices are sized for a 100 kW module, which is a common power rating for BESS applications [1]. The simulated system is shown in Figure 6 where the required sensed signals, according to variables of  Figure 4, a parameterization with respect to the highest value of K is considered, as described in Equation (24), for u AB , and a similar consideration is done for the other control laws.

Simulation Results
In this section, the main simulation results are presented to point out the control effectiveness in complying with the rectifier requirements, which are shown in Table 2 [34]. Additionally, the passive devices are sized for a 100 kW module, which is a common power rating for BESS applications [1]. The simulated system is shown in Figure 6 where the required sensed signals, according to variables of Figure 1, are pointed out for computing the current references and the nonlinear control. According to Figure 4, a parameterization with respect to the highest value of is considered, as described in Equation (23), for , and a similar consideration is done for the other control laws. For designing the control law, the three-phase LCL PWM rectifier model (Equation (14)) was validated with the specialized simulators: PSCAD ® and SimPowerSystems-Simulink ® . Figure 7 shows the validation with Simulink in open-loop mode showing currents , , , voltages , , , and the dc voltage . However, for the simulation, the defined libraries with semiconductors were used for the power converter stage. Concerning the battery model, the equivalent electrical circuit (EEC) of Figure 8, was used. The elements of the EEC model represent the internal battery dynamics where is the internal/ohmic resistance, and represent capacitor and resistor for the distribution of reactivity and the local property of electrodes, and For designing the control law, the three-phase LCL PWM rectifier model (Equation (14)) was validated with the specialized simulators: PSCAD ® and SimPowerSystems-Simulink ® . Figure 7 shows the validation with Simulink in open-loop mode showing currents i A , i B , i C , voltages v cAB , v cBC , v cCA , and the dc voltage V DC . However, for the simulation, the defined libraries with semiconductors were used for the power converter stage. Concerning the battery model, the equivalent electrical circuit (EEC) of Figure 8, was used. The elements of the EEC model represent the internal battery dynamics where R 0 is the internal/ohmic resistance, C 1 and R 1 represent capacitor and resistor for the distribution of reactivity and the local property of electrodes, C 2 and R 2 represent the interfacial impedance of the cell, v oc represents the battery open circuit voltage, and v bat is the battery voltage [35][36][37].       To assess the three-phase PWM rectifier performance with the proposed control scheme, a load current i load depicted in Figure 9 was used. It represents the current with load steps of the dc-dc stage for charging the battery bank in accordance with the duty class. To assess the three-phase PWM rectifier performance with the proposed control scheme, a load current depicted in Figure 9 was used. It represents the current with load steps of the dc-dc stage for charging the battery bank in accordance with the duty class.

Performance with the Duty Class
The tracking problem is achieved as it is depicted in Figure 10, with the corresponding duty class, where the input currents , , and track their corresponding references and are in phase with the voltages , , and with a power factor of 0.99. It can be observed in Figure  11 that the error is kept close to zero, even at the highest load condition.

Current (A)
Voltage (V) Figure 9. Load current i load demanded by Z load .

Performance with the Duty Class
The tracking problem is achieved as it is depicted in Figure 10, with the corresponding duty class, where the input currents i AB , i BC , and i CA track their corresponding references and are in phase with the voltages v AB , v BC , and v CA with a power factor of 0.99. It can be observed in Figure 11 that the error is kept close to zero, even at the highest load condition.
Concerning the THD of current, the requirement is achieved with the proposed control along with the inductor L f 1 and L f 2 values of the LCL filter. The criteria for selecting the filter values were considering the converter operation as an inverter. Nevertheless, this paper only addresses the process of working as a PWM rectifier; hence, the THD = 0.95% for 110 kW as shown in Figure 12.

Performance with the Duty Class
The tracking problem is achieved as it is depicted in Figure 10, with the corresponding duty class, where the input currents , , and track their corresponding references and are in phase with the voltages , , and with a power factor of 0.99. It can be observed in Figure  11 that the error is kept close to zero, even at the highest load condition.  Concerning the THD of current, the requirement is achieved with the proposed control along with the inductor and values of the LCL filter. The criteria for selecting the filter values were considering the converter operation as an inverter. Nevertheless, this paper only addresses the process of working as a PWM rectifier; hence, the THD = 0.95% for 110 kW as shown in Figure 12. The tracking problem is achieved as it is depicted in Figure 10, with the corresponding duty class, where the input currents , , and track their corresponding references and are in phase with the voltages , , and with a power factor of 0.99. It can be observed in Figure  11 that the error is kept close to zero, even at the highest load condition.  Concerning the THD of current, the requirement is achieved with the proposed control along with the inductor and values of the LCL filter. The criteria for selecting the filter values were considering the converter operation as an inverter. Nevertheless, this paper only addresses the process of working as a PWM rectifier; hence, the THD = 0.95% for 110 kW as shown in Figure 12. The dc bus voltage regulation, which is indirectly controlled by the input current, as shown in Figure 13. An error of 0.5% can be observed by using the integral action in contrast to the 2.9% of error without using it.

Performance with Input Voltage Variations and Uncertainties
Additionally, to reveal the effectiveness of the integral action, the control robustness is tested for input voltage variations; the indirectly regulated output voltage remains within the established 3% requirement despite the grid voltage varies ±10% based on rated power, as it can be seen in Figure  14. The dc bus voltage regulation, which is indirectly controlled by the input current, as shown in Figure 13. An error of 0.5% can be observed by using the integral action in contrast to the 2.9% of error without using it. The dc bus voltage regulation, which is indirectly controlled by the input current, as shown in Figure 13. An error of 0.5% can be observed by using the integral action in contrast to the 2.9% of error without using it.

Performance with Input Voltage Variations and Uncertainties
Additionally, to reveal the effectiveness of the integral action, the control robustness is tested for input voltage variations; the indirectly regulated output voltage remains within the established 3% requirement despite the grid voltage varies ±10% based on rated power, as it can be seen in Figure  14.

Performance with Input Voltage Variations and Uncertainties
Additionally, to reveal the effectiveness of the integral action, the control robustness is tested for input voltage variations; the indirectly regulated output voltage V DC remains within the established 3% requirement despite the grid voltage varies ±10% based on rated power, as it can be seen in Figure 14.

Performance with Input Voltage Variations and Uncertainties
Additionally, to reveal the effectiveness of the integral action, the control robustness is tested for input voltage variations; the indirectly regulated output voltage remains within the established 3% requirement despite the grid voltage varies ±10% based on rated power, as it can be seen in Figure  14. Concerning the parametric variation, the tolerance values of ±10% in each passive device, the increase of 100% in its parasitic series resistance, and a 100% increase in the on-resistance of power semiconductors are evaluated. For the 10% case, the currents , , and track the corresponding references (with an error near to zero) and are in phase with the voltages , , and , respectively (see Figure 15). As a consequence, the indirectly regulated voltage behaves as shown in Figure 16, where the highest voltage error is 1.4% when the converter delivers 150 kW. Concerning the parametric variation, the tolerance values of ±10% in each passive device, the increase of 100% in its parasitic series resistance, and a 100% increase in the on-resistance of power semiconductors are evaluated. For the 10% case, the currents i AB , i BC , and i CA track the corresponding references (with an error near to zero) and are in phase with the voltages v AB , v BC , and v CA , respectively (see Figure 15). As a consequence, the indirectly regulated voltage behaves as shown in Figure 16, where the highest voltage error is 1.4% when the converter delivers 150 kW.  Similarly, the control performance for the −10% tolerance in passive devices is shown next. The current tracking problem is solved as well, as can be seen in Figure 17, where the currents track the references with an error near to zero. In this case, the indirectly controlled voltage has an error of 1.2% for 150 kW (Figure 18), which is slightly less than the +10% tolerance. However, in both circumstances, the voltage is within the defined tolerance of 3%.  Similarly, the control performance for the −10% tolerance in passive devices is shown next. The current tracking problem is solved as well, as can be seen in Figure 17, where the currents track the references with an error near to zero. In this case, the indirectly controlled voltage has an error of 1.2% for 150 kW (Figure 18), which is slightly less than the +10% tolerance. However, in both circumstances, the voltage is within the defined tolerance of 3%. Similarly, the control performance for the −10% tolerance in passive devices is shown next. The current tracking problem is solved as well, as can be seen in Figure 17, where the currents track the references with an error near to zero. In this case, the indirectly controlled voltage has an error of 1.2% for 150 kW (Figure 18), which is slightly less than the +10% tolerance. However, in both circumstances, the voltage is within the defined tolerance of 3%. Similarly, the control performance for the −10% tolerance in passive devices is shown next. The current tracking problem is solved as well, as can be seen in Figure 17, where the currents track the references with an error near to zero. In this case, the indirectly controlled voltage has an error of 1.2% for 150 kW (Figure 18), which is slightly less than the +10% tolerance. However, in both circumstances, the voltage is within the defined tolerance of 3%. For the duty class shown in previous figures, the control signal is shown in Figure 19. It can be seen the saturated control is not presented in steady-state even in the 150 kW case, which shows the suitability of the proposed control scheme in achieving the requirements.

Discussion: Proposed Alternative Control Scheme vs. Traditional Control Scheme
To evaluate the effectiveness of the proposed alternative control scheme, load step changes, input voltage variations, and parametric uncertainties considering the specified duty class were addressed. Besides, the three main objectives dc bus voltage regulation, THD current requirement, and power factor were accomplished. Remarkably, the dc bus voltage regulation objective is within the ±3% requirement despite having only indirect current-loop control. The proposed control technique shows similar performance to the traditional control scheme.
Concerning the THD and the power factor requirements, the findings confirm the usefulness of the tracking control law. The results show the THD and power factor levels are always satisfactorily accomplished; however, it is fundamental to notice that these requirements are not only fulfilled with the control law but also with a correct LCL filter design (which is not the purpose of this paper).
In our view, the simulation results emphasize the validation of the proposed controller whose signal evolves in the −1 to 1 interval, which reveals the feasibility of considering the proposed control For the duty class shown in previous figures, the control signal u AB is shown in Figure 19. It can be seen the saturated control is not presented in steady-state even in the 150 kW case, which shows the suitability of the proposed control scheme in achieving the requirements. For the duty class shown in previous figures, the control signal is shown in Figure 19. It can be seen the saturated control is not presented in steady-state even in the 150 kW case, which shows the suitability of the proposed control scheme in achieving the requirements.

Discussion: Proposed Alternative Control Scheme vs. Traditional Control Scheme
To evaluate the effectiveness of the proposed alternative control scheme, load step changes, input voltage variations, and parametric uncertainties considering the specified duty class were addressed. Besides, the three main objectives dc bus voltage regulation, THD current requirement, and power factor were accomplished. Remarkably, the dc bus voltage regulation objective is within the ±3% requirement despite having only indirect current-loop control. The proposed control technique shows similar performance to the traditional control scheme.
Concerning the THD and the power factor requirements, the findings confirm the usefulness of the tracking control law. The results show the THD and power factor levels are always satisfactorily accomplished; however, it is fundamental to notice that these requirements are not only fulfilled with the control law but also with a correct LCL filter design (which is not the purpose of this paper).
In our view, the simulation results emphasize the validation of the proposed controller whose signal evolves in the −1 to 1 interval, which reveals the feasibility of considering the proposed control AB u Figure 19. Control signal u AB and a portion of the generated PWM.

Discussion: Proposed Alternative Control Scheme vs. Traditional Control Scheme
To evaluate the effectiveness of the proposed alternative control scheme, load step changes, input voltage variations, and parametric uncertainties considering the specified duty class were addressed. Besides, the three main objectives dc bus voltage regulation, THD current requirement, and power factor were accomplished. Remarkably, the dc bus voltage regulation objective is within the ±3% requirement despite having only indirect current-loop control. The proposed control technique shows similar performance to the traditional control scheme.
Concerning the THD and the power factor requirements, the findings confirm the usefulness of the tracking control law. The results show the THD and power factor levels are always satisfactorily accomplished; however, it is fundamental to notice that these requirements are not only fulfilled with the control law but also with a correct LCL filter design (which is not the purpose of this paper).
In our view, the simulation results emphasize the validation of the proposed controller whose signal evolves in the −1 to 1 interval, which reveals the feasibility of considering the proposed control scheme for a PWM rectifier used into a BESS application.
Additionally, in Table 3, a contrast of the main control characteristics for the proposed control scheme and the reviewed control techniques are summarized. The evaluated items reveal that the Park transformation is avoided in three control approaches including the proposed approach. Nonetheless, the direct power control requires a computing power stage instead. Besides, all the controllers required the internal current control loop, since the system is minimum phase when the current is the output. In contrast to the voltage loop that is included in the reported approaches, it is substituted by the online power balance in the proposed scheme. Also, the delays due to the Park transformations and its inverse are avoided. However, the nonlinear controller requires three derivatives, which adds complexity. Table 3. The contrast of the proposed control scheme and other reported approaches [6,16,20,23,[38][39][40][41][42][43].