An Innovative Dual-Boost Nine-Level Inverter with Low-Voltage Rating Switches

This article presents an innovative switched-capacitor based nine-level inverter employing single DC input for renewable and sustainable energy applications. The proposed configuration generates a step-up bipolar output voltage without end-side H-bridge, and the employed capacitors are charged in a self-balancing form. Applying low-voltage rated switches is another merit of the proposed inverter, which leads to extensive reduction in total standing voltage. Thereby, switching losses as well as inverter cost are reduced proportionally. Furthermore, the comparative analysis against other state-of-the-art inverters depicts that the number of required power electronic devices and implementation cost is reduced in the proposed structure. The working principle of the proposed circuit along with its efficiency calculations and thermal modeling are elaborated in detail. In the end, simulations and experimental tests are conducted to validate the flawless performance of the proposed nine-level topology in power systems.


Introduction
In recent years, extensive research has been carried out on multilevel inverters (MLIs) due to their potential in various industrial applications, particularly grid-connected renewable energy sources, machine drives, and high-voltage direct current transmission systems. Improved output waveforms quality, reduced device stress (dv/dt), and increased efficiency are some merits of the MLIs in comparison with the standard two-level inverter [1][2][3][4]. The most popular traditional/basic multilevel topologies are CHB, NPC, and FC, which have widely been put into commercial use in high/medium voltage systems (above 3 kV). Nonetheless, high control/modulation technique complexity and large power electronic device count (dc power supplies, semiconductors, and capacitors) are cited as demerits of the aforementioned topologies [5][6][7].
To overcome these drawbacks, researchers and industrialists all around the world are contributing to present innovative topologies with the ability to produce more voltage levels with reduced device  Figure 1, it comprises twelve power switches, two capacitors (C 1 , C 2 ), and only one input DC source with the advantage of regenerative capability. The output voltage can be boosted up to 2V IN by connecting the input source with pre-charged capacitors in series. It should be underscored that the blocking voltage of all switches employed in the proposed inverter is equal to the input DC source (i.e., V IN ), with the exception of S 7 , S 8, and S 12 which block only half the V IN . In other words, it generates a bipolar output voltage without using end-side H-bridge. This ability is considered a beneficial feature of the proposed circuit since the lower switch voltage rating, the cheaper switch.
The working principle of the proposed inverter is illustrated in Figure 2. As can be observed, C 1  The working principle of the proposed inverter is illustrated in Figure 2. As can be observed, C1 and C2 are charged up to VIN/2 by turning S3 and S4 on during 0 and ±1VIN levels. Then, the capacitors are connected in parallel at ±VIN/2 and ±3VIN/2 levels. Thereby, the voltage across them is balanced. Finally, they are discharged across the load during ±VIN/2 and ±2VIN levels. Relying on this simple switching plan, the proposed inverter does not require any external balancer circuit.  Table 1 compares the presented circuit with other recently-introduced topologies in terms of the number of required semiconductors/DC sources and switches voltage rating. As observed from the table, [14] the proposed circuit employs the least number of switches and capacitors compared to the other ones. These minimizations result in simpler control and a higher degree of compactness. Apart from this, the table depicts a fourfold increase in the number of required DC power supplies for [14] and conventional CHB, while the others and proposed inverter utilize only one DC source.

Comparative Assessment
Applying switches with lower PIV is also a distinct advantage of the proposed inverter. In other words, it enjoys the lowest level of TSV. To prove this, the number of employed IGBTs with the same The working principle of the proposed inverter is illustrated in Figure 2. As can be observed, C1 and C2 are charged up to VIN/2 by turning S3 and S4 on during 0 and ±1VIN levels. Then, the capacitors are connected in parallel at ±VIN/2 and ±3VIN/2 levels. Thereby, the voltage across them is balanced. Finally, they are discharged across the load during ±VIN/2 and ±2VIN levels. Relying on this simple switching plan, the proposed inverter does not require any external balancer circuit.  Table 1 compares the presented circuit with other recently-introduced topologies in terms of the number of required semiconductors/DC sources and switches voltage rating. As observed from the table, [14] the proposed circuit employs the least number of switches and capacitors compared to the other ones. These minimizations result in simpler control and a higher degree of compactness. Apart from this, the table depicts a fourfold increase in the number of required DC power supplies for [14] and conventional CHB, while the others and proposed inverter utilize only one DC source.

Comparative Assessment
Applying switches with lower PIV is also a distinct advantage of the proposed inverter. In other words, it enjoys the lowest level of TSV. To prove this, the number of employed IGBTs with the same  Table 1 compares the presented circuit with other recently-introduced topologies in terms of the number of required semiconductors/DC sources and switches voltage rating. As observed from the table, ref. [14] the proposed circuit employs the least number of switches and capacitors compared to the other ones. These minimizations result in simpler control and a higher degree of compactness. Apart from this, the table depicts a fourfold increase in the number of required DC power supplies for [14] and conventional CHB, while the others and proposed inverter utilize only one DC source.

Comparative Assessment
Applying switches with lower PIV is also a distinct advantage of the proposed inverter. In other words, it enjoys the lowest level of TSV. To prove this, the number of employed IGBTs with the same voltage rating for each structure is presented in the following table. For instance, the proposed 9 L inverter needs nine and three switches with the PIV of 1V IN and V IN /2 respectively, while [13] requires nineteen IGBTs with the voltage ratings of V IN . Thereby, the proposed inverter can be an acceptable alternative to the topologies listed in Table 1.
M *: Number of cascaded modules.
Furthermore, the single-source topologies are also compared in terms of total implementation cost (see Table 2). It should be noted that CHB and [14] are not considered in the cost-comparative analysis since they require four DC power supplies. For a fair comparison, power rating (i.e., volt/ampere rating) of all the MLIs are assumed to be equal to 5 kW/30.7 A. Moreover, a 50% voltage rating margin is considered for the selection of switches and capacitors. It is observed from Table 2 that the proposed inverter requires the least implementation cost compared to the other ones.

Multicarrier PWM Strategy
Therein, phase disposition PWM technique is applied to control each IGBT of the proposed topology. To do this, eight triangular carriers (V t1 to V t8 ) arranged with shifts in amplitudes are required (see Figure 3a). It should be noted that they are the same in amplitude (A t ), frequency (f t ) and phase [16,17]. The carriers are compared to a reference waveform (V ref ) which results in generating appropriate fire pulses for all switches. For instance, S 11 is turned on when In other words, S 11 must be turned on when S 1 : ON, S 4 : ON, S 3 : OFF (or S 2 : ON, S 3 : ON, S 4 : OFF), which can be observed in Figure 2. Similarly, S 12 is turned on when In other words, S 12 must be turned on when S 7 and S 8 are OFF (see Figure 2). Further clarification concerning switching strategy is brought up in Figure 3b and Table 3.

Power Loss Analysis
The power loss for a multilevel inverter is composed of three parts including P C , P S and P R which are elaborated as follows: 4.1.1. Conduction Loss (P C ) P C is caused by parasitic resistance (i.e., ON-state resistance of the switch (R S ) and its parallel diode (R D ), capacitor internal resistance (R C )) involved in the current paths [18]. Table 4 shows the equivalent value of the parasitic resistance (R eq ) existing in each voltage level. It should be noted that in the present work R S , R D, and R C are considered equal to 0.27 Ω, 0.05 Ω, and 0.03 Ω, respectively. Table 4. R eq in Each Step.

Output Level
R eq (Ω) the output voltage switches between 0 and +V IN /2 (see Figure 3a). Consequently, the output current passes through two switches and two diodes (three switches, two diodes, and one capacitor) during 0 (+V IN /2) level, as depicted in Table 4. In this case, the energy dissipated within 0 < t < t 1 (t 6 < t < t 7 or t 12 < t < 2π) is attained by Equation (1) in which A t , A ref, and f ref are considered equal to 0.25, 0.9, and 50 Hz, respectively [18]. Moreover, t 1 is calculated as follows: Similarly, the energy losses that occurred in other time intervals are calculated by Equations (3)-(8).
Due to quarter-wave symmetry of the output voltage, the total conduction loss for the proposed 9 L topology is: 4.1.2. Switching Loss (P S ) The overlap of switch voltage and current during rise and fall times (i.e., t on and t off ) leads to P S , which is highly proportional to the f S . The turn-on and turn-off power loss of the switch S are attained by [19]: In which I S on (I S off ) is the switch current after (before) turning on (off). Considering t on = t off = 58 ns and f t = 4 kHz, P S for all the switches is obtained as follows: × 58 × 10 −9 = 6.15 × 10 −6 × P out , j = 1, 2, 9, 10, 11 (12) × 58 × 10 −9 = 12.3 × 10 −6 × P out , j = 3, 4, 5, 6 (13) × 58 × 10 −9 = 3.07 × 10 −6 × P out , j = 7, 8 (14) P S12,on = P S12,o f f = 1 Consequently, the total switching loss for the presented 9 L inverter is calculated by: 4.1.3. Power Loss Generated by Capacitor Voltage Ripple (P R ) P R is due to the voltage difference between the capacitor and input DC source during the charging periods. Generally, the maximum discharging value of each capacitor in a switched-capacitor circuit is attained by [13,18]: where [t c , t d ] is the discharging interval of each capacitor. According to Figures 2a and 3a, the maximum discharging period of C 1 (or C 2 ) is equal to [t 3 , t 4 ]. Thus, considering maximum acceptable voltage drop across C 1 (or C 2 ) equal to ∆V ripple , the capacitance of each capacitor is calculated by [13,18]: For example, considering P out = 1.4 kW (I Load = 7 A, V IN =200 V) and ∆V ripple = 10%, the capacitances for the proposed inverter are obtained as follows: It also should be noted that nominal voltage of the capacitors is equal to V IN /2 (see Figure 2). Consequently, P R for the proposed topology is attained as follows: (20) Therefore, considering Equations (9), (16), and (20), the efficiency is calculated by Equation (21).
Theoretical efficiency of the proposed inverter has been calculated at different output power and presented in Figure 4. It is observed that there is a marked rise in the efficiency by increasing the output power.
where [tc, td] is the discharging interval of each capacitor. According to Figures 2a and 3a, the maximum discharging period of C1 (or C2) is equal to [t3, t4]. Thus, considering maximum acceptable voltage drop across C1 (or C2) equal to ΔVripple, the capacitance of each capacitor is calculated by [13,18]: For example, considering Pout = 1.4 kW (ILoad = 7 A, VIN=200 V) and ΔVripple = 10%, the capacitances for the proposed inverter are obtained as follows: It also should be noted that nominal voltage of the capacitors is equal to VIN/2 (see Figure 2). Consequently, PR for the proposed topology is attained as follows: Therefore, considering Equations (9), (16), and (20), the efficiency is calculated by Equation (21).
Theoretical efficiency of the proposed inverter has been calculated at different output power and presented in Figure 4. It is observed that there is a marked rise in the efficiency by increasing the output power.

Thermal Model
Heat distribution through semiconductor components is caused by power loss, which leads to an increasing of Tj [20]. This temperature, for safety reasons, should be monitored and kept within a specified range during the inverter operation. Figure 5a illustrates the thermal model implemented for a single semiconductor, in which the thermal impedance between junction and case (Zth) is considered a four-layer foster network (see Figure 5b) [21,22]. It should be noted that Zc and Zs are the thermal impedances from the case to the heat sink and from the heat sink to the ambient, respectively. These are found on the manufacturer datasheet.

Thermal Model
Heat distribution through semiconductor components is caused by power loss, which leads to an increasing of T j [20]. This temperature, for safety reasons, should be monitored and kept within a specified range during the inverter operation. Figure 5a illustrates the thermal model implemented for a single semiconductor, in which the thermal impedance between junction and case (Z th ) is considered a four-layer foster network (see Figure 5b) [21,22]. It should be noted that Z c and Z s are the thermal impedances from the case to the heat sink and from the heat sink to the ambient, respectively. These are found on the manufacturer datasheet.  Modelling loss dissipation of the proposed 9 L inverter in MATLAB/Simulink yields the junction temperature of the power electronic devices [23][24][25]. Herein, Ta is considered equal to 40 °C and the PM75CLA060 switch produced by Mitsubishi Electric is chosen in the thermal estimation.
The estimated Tj of some power switches employed in the proposed inverter at 20 kW output power is illustrated in Figure 6. It can be observed that S12 has the lowest Tj (approximately 43.9 °C), while this temperature approaches 46.7 °C for S11.  Modelling loss dissipation of the proposed 9 L inverter in MATLAB/Simulink yields the junction temperature of the power electronic devices [23][24][25]. Herein, T a is considered equal to 40 • C and the PM75CLA060 switch produced by Mitsubishi Electric is chosen in the thermal estimation.
The estimated T j of some power switches employed in the proposed inverter at 20 kW output power is illustrated in Figure 6. It can be observed that S 12 has the lowest T j (approximately 43.9 • C), while this temperature approaches 46.7 • C for S 11 .  Modelling loss dissipation of the proposed 9 L inverter in MATLAB/Simulink yields the junction temperature of the power electronic devices [23][24][25]. Herein, Ta is considered equal to 40 °C and the PM75CLA060 switch produced by Mitsubishi Electric is chosen in the thermal estimation.
The estimated Tj of some power switches employed in the proposed inverter at 20 kW output power is illustrated in Figure 6. It can be observed that S12 has the lowest Tj (approximately 43.9 °C), while this temperature approaches 46.7 °C for S11.

Simulation and Experimental Results
Simulations have been conducted in MATLAB for steady-state and transient modes, as presented below. Figure 7 shows the inverter output voltage/current and capacitors voltage at resistive-inductive load (f t = 4 kHz, C 1 = C 2 = 2300 µF, R = 100 Ω, L = 100 mH). These results confirm the flawless performance and self-balanced ability of the presented 9 L inverter. Moreover, the value of the input DC source is selected at 200 V. Thus, the capacitors and output voltages reach 100 V and 400 V, respectively. The proposed topology has also been simulated under step change in the load, and the results are presented in Figure 8. As can be observed, the voltage ripple across the capacitors rises promptly from 3.5% to 7.2% by decreasing the load impedance. Once again, these figures verify the inherent capacitor voltage balancing ability during inverter operation. Figure 9 shows the voltage waveforms across some power switches employed in the proposed topology. It is clear that S 3 , S 5, and S 11 (also S 1 , S 2 , S 4 , S 6 , S 9 and S 10 ) must withstand voltages equal to the input DC source (i.e., 200 V). Other switches (S 7 , S 8 and S 12 ), however, block voltages equal to half the input DC source (i.e., 100 V). To sum up, unlike topologies with end side H-bridge, none of the switches required for the proposed inverter tolerate maximum output voltage (i.e., 400 V).
Furthermore, the effect of different modulation indexes and switching frequencies on the operation of the proposed inverter is shown in Figure 10. It is observed that the inverter output voltage has lower THD at higher modulation index (and higher switching frequency). Moreover, the fundamental component of output voltage is decreased at lower modulation index.

Simulation and Experimental Results
Simulations have been conducted in MATLAB for steady-state and transient modes, as presented below. Figure 7 shows the inverter output voltage/current and capacitors voltage at resistive-inductive load (ft = 4 kHz, C1 = C2 = 2300 µF, R = 100 Ω, L = 100 mH). These results confirm the flawless performance and self-balanced ability of the presented 9 L inverter. Moreover, the value of the input DC source is selected at 200 V. Thus, the capacitors and output voltages reach 100 V and 400 V, respectively. The proposed topology has also been simulated under step change in the load, and the results are presented in Figure 8. As can be observed, the voltage ripple across the capacitors rises promptly from 3.5% to 7.2% by decreasing the load impedance. Once again, these figures verify the inherent capacitor voltage balancing ability during inverter operation.   Figure 9 shows the voltage waveforms across some power switches employed in the proposed topology. It is clear that S3, S5, and S11 (also S1, S2, S4, S6, S9 and S10) must withstand voltages equal to the input DC source (i.e., 200 V). Other switches (S7, S8 and S12), however, block voltages equal to half the input DC source (i.e., 100 V). To sum up, unlike topologies with end side H-bridge, none of the switches required for the proposed inverter tolerate maximum output voltage (i.e., 400 V).    Figure 9 shows the voltage waveforms across some power switches employed in the proposed topology. It is clear that S3, S5, and S11 (also S1, S2, S4, S6, S9 and S10) must withstand voltages equal to the input DC source (i.e., 200 V). Other switches (S7, S8 and S12), however, block voltages equal to half the input DC source (i.e., 100 V). To sum up, unlike topologies with end side H-bridge, none of the switches required for the proposed inverter tolerate maximum output voltage (i.e., 400 V).   Furthermore, the effect of different modulation indexes and switching frequencies on the operation of the proposed inverter is shown in Figure 10. It is observed that the inverter output voltage has lower THD at higher modulation index (and higher switching frequency). Moreover, the fundamental component of output voltage is decreased at lower modulation index. To validate the high performance of the proposed model, a low-power prototype of the proposed inverter has been implemented and tested. Accordingly, a Texas Instruments (TMS320F28335) fixed-point DSP control board generated gate pulses for employed switches (IRFP460 500 V/ 20 A). Moreover, the value of capacitances and input DC source are selected at 2300 µF and 140 V, respectively. Figure 11 illustrates the results obtained from the hardware implementation of the proposed inverter model under steady-state and transient operating conditions. These figures fully confirm the flawless performance of the proposed inverter. To validate the high performance of the proposed model, a low-power prototype of the proposed inverter has been implemented and tested. Accordingly, a Texas Instruments (TMS320F28335) fixed-point DSP control board generated gate pulses for employed switches (IRFP460 500 V/20 A). Moreover, the value of capacitances and input DC source are selected at 2300 µF and 140 V, respectively. Figure 11 illustrates the results obtained from the hardware implementation of the proposed inverter model under steady-state and transient operating conditions. These figures fully confirm the flawless performance of the proposed inverter.

Conclusions
Herein, the operating principle of a new 9 L inverter has been discussed and confirmed experimentally. The comparative analysis depicted that the presented topology not only reduces the number of semiconductors/DC links required for generating a 9 L voltage waveform, but also employs IGBTs with lower PIV. These merits lead to a high compactness and cost reduction of the conversion system. Due to the intrinsic self-voltage balancing ability, there is no need for complex modulation methods. Thereupon, it enjoys simple control and implementation. Furthermore, the theoretical efficiency demonstrated that the presented configuration has higher efficiency by increasing output power (up to 2000 W). Eventually, the feasibility and effectiveness of the proposed model was verified by the simulation and experimental results.
Author Contributions: All authors contributed equally to this work and all authors have read and approved the final manuscript.
Funding: This research received no external funding.

Conflicts of Interest:
The authors declare no conflicts of interest.

Conclusions
Herein, the operating principle of a new 9 L inverter has been discussed and confirmed experimentally. The comparative analysis depicted that the presented topology not only reduces the number of semiconductors/DC links required for generating a 9 L voltage waveform, but also employs IGBTs with lower PIV. These merits lead to a high compactness and cost reduction of the conversion system. Due to the intrinsic self-voltage balancing ability, there is no need for complex modulation methods. Thereupon, it enjoys simple control and implementation. Furthermore, the theoretical efficiency demonstrated that the presented configuration has higher efficiency by increasing output power (up to 2000 W). Eventually, the feasibility and effectiveness of the proposed model was verified by the simulation and experimental results.
Author Contributions: All authors contributed equally to this work and all authors have read and approved the final manuscript.
Funding: This research received no external funding.

Conflicts of Interest:
The authors declare no conflicts of interest. Turn-on and turn-off power loss of the switch S (W) P out Inverter output power (W) R S and R D ON-state resistance of the switch S and its parallel diode (Ω) R C Capacitor internal resistance (Ω) R eq Equivalent value of the parasitic resistance in each voltage level (Ω) R and L Resistance (Ω) and inductance (H) of the load t on and t off Rise and fall times of the switch S (s) f S Switching frequency (Hz) T j Semiconductor junction temperature ( • C) T c Semiconductor case temperature ( • C) T s Heat sink temperature ( • C) T a Ambient temperature ( • C) Z th Thermal impedance between junction and case of the semiconductor Z c Thermal impedance between semiconductor case and its heat sink Z s Thermal impedance between heat sink and ambient