A Study on Neutral-Point Potential in Three-Level NPC Converters

: This paper proposes an accurate mathematical model of three-level neutral-point-clamped (NPC) converters that can accurately represent the midpoint potential drift of the DC link with parameter perturbation. The mathematical relationships between the ﬂuctuation in neutral-point voltage, the parametric perturbation, and the capacitance error are obtained as mathematical expressions in this model. The expressions can be used to quantitatively analyze the reason for the neutral-point voltage imbalance and balancing e ﬀ ect based on a zero-sequence voltage injection. The injected zero-sequence voltage, which can be used to balance the DC-side voltages with the combined action of active current, can be easily obtained from the proposed model. A balancing control under four-quadrant operation modes is proposed by considering the active current to verify the e ﬀ ectiveness of this model. Both the simulation and experiment results validate the excellent performance of the proposed model compared to the conventional model.


Introduction
Three-level neutral-point-clamped (NPC) converters are popularly used in renewable energy generation and energy storage, which have been widely recognized as promising solutions to the problems associated with increasing environmental challenges [1][2][3]. Compared to the two-level topology, three-level NPC converters are much more attractive because of their lower voltage stress on power electronic devices, lower total harmonic distortion, higher efficiency, and even better economic performance [4][5][6].
However, the neutral-point potential drift, which results in an imbalance of voltages of the two DC-side capacitors, is an inherent problem for the three-level NPC topology. Without considering the sampling error, capacitance error, inconsistent characteristics of devices, and operation under unbalanced conditions are usually considered the reasons for potential drift. How to keep the upper and lower voltages equal is very important for the devices to run safely and reliably [7][8][9].

Main Circuit Topology
The circuit topology of three-level NPC grid-connected converters used in renewable, energy-based applications is presented in Figure 1. The converter transfers active power from wind energy, photovoltaic energy, chemical energy, or the energy storage system to the distribution network. In some cases, it also can transfer active power from the distribution network to the energy storage system as well as compensate reactive power to the network. modulation (SVPWM) strategies were proposed to adjust the dwell time between small vector switching states by judging the direction of the neutral point current and the deviation of the neutral point potential. However, the calculation methods are complex and difficult to implement. In [24], a pulse width modulation (PWM) strategy was proposed where the both DC-side voltages can be adjusted independently through zero-sequence voltage injections and compensation for the unbalance in neutral point voltages, but the process of calculating the injected zero-sequence voltages is complicated.
However, these control strategies, above all, ignore the quantitative analysis of the potential drift and balancing effect based on zero-sequence voltage injection. Meanwhile, if the converter is used in renewable energy generation and energy storage with four-quadrant operation modes, the DC voltage balancing control is very difficult to realize in existing literature because the active current of the converter is not taken into consideration.
This paper proposes an accurate mathematical model of the neutral-point potential in three-level NPC converters based on the SPWM strategy with parametric perturbation and zero-sequence voltage injection. The model is simple and direct, but very interesting and valuable. To the best of our knowledge, it is novel and has not been previously reported in the literature. From this model, the relationship between the drift potential value and all the AC-side and DC-side variables can be deduced by quantitative analyses. The calculated drift potential value shows that the basic reason for the neutral-point potential drift is the uneven shunt loss caused by the parametric perturbation, and the capacitance error has no influence on it. The balancing control can be directly obtained based on the combined action of the injected zero-sequence voltage and active current. The required zerosequence voltage for balancing control can be easily calculated by this model.
The rest of this paper is organized as follows. Section 2 describes the main circuit topology, modulation strategy and AC-side current control. Section 3 develops the accurate mathematical model of the neutral-point potential drift, which shows the reason for the neutral-point potential drift. DC voltage control is realized in Section 4. In Section 5, the effectiveness and performance of this model and control strategy are verified by simulation and experiment.

Main Circuit Topology
The circuit topology of three-level NPC grid-connected converters used in renewable, energybased applications is presented in Figure 1. The converter transfers active power from wind energy, photovoltaic energy, chemical energy, or the energy storage system to the distribution network. In some cases, it also can transfer active power from the distribution network to the energy storage system as well as compensate reactive power to the network.    As shown in Figure 1, U dc denotes the DC-side voltage source, and Y d is the internal resistor. u x (x = a, b, c) is the system voltage, v x is the output voltage of the converter. C 1 and C 2 are the two DC-side capacitors. Y 1 and Y 2 represent the shunt loss, including losses in the two parallel resistors and the power electronic switches. U 1 and U 2 are the two DC-side capacitor voltages. L s is the linked reactor. The series losses are represented by the equivalent resistance R s .
The purpose of DC-side voltage control is to maintain U 1 and U 2 at an equal and prespecified level.

Modulation Strategy
Power electronic switches in Figure 1 can be turned on and off based on the alternative phase opposition disposition (APOD) sine pulse width modulation (SPWM) strategy, as shown in Figure 2. Take phase a of Figure 1 as an example, s a is the modulation signal with zero-sequence DC component s 0 . CA 1 and CA 2 are the two triangular carrier waveforms with the same frequency, same amplitude, and contrary phases. Switches Q 1 and Q 3 are turned on and off based on the comparison of s a and CA 1 . Switches Q 2 and Q 4 are turned on and off based on the comparison of s a and CA 2 . Diodes D 1 and D 2 provide the bidirectional current path for the AC-side terminal to the common point of the DC capacitors O, when both Q 2 and Q 3 are on or off. Therefore, v a swings between the neutral-point potential (here referred to as zero) when both Q 2 and Q 3 are on or off, U 1 when both Q 1 and Q 2 are on, and −U 2 when both Q 3 and Q 4 are on [28]. As shown in Figure 1, denotes the DC-side voltage source, and Yd is the internal resistor. (x = a, b, c) is the system voltage, is the output voltage of the converter. C1 and C2 are the two DC-side capacitors. Y1 and Y2 represent the shunt loss, including losses in the two parallel resistors and the power electronic switches. U1 and U2 are the two DC-side capacitor voltages. is the linked reactor. The series losses are represented by the equivalent resistance .
The purpose of DC-side voltage control is to maintain U1 and U2 at an equal and prespecified level.

Modulation Strategy
Power electronic switches in Figure 1 can be turned on and off based on the alternative phase opposition disposition (APOD) sine pulse width modulation (SPWM) strategy, as shown in Figure 2. Take phase a of Figure 1 as an example, is the modulation signal with zero-sequence DC component s0. CA1 and CA2 are the two triangular carrier waveforms with the same frequency, same amplitude, and contrary phases. Switches Q1 and Q3 are turned on and off based on the comparison of and CA1. Switches Q2 and Q4 are turned on and off based on the comparison of and CA2. Diodes D1 and D2 provide the bidirectional current path for the AC-side terminal to the common point of the DC capacitors O, when both Q2 and Q3 are on or off. Therefore, swings between the neutral-point potential (here referred to as zero) when both Q2 and Q3 are on or off, U1 when both Q1 and Q2 are on, and −U2 when both Q3 and Q4 are on [28].

AC-Side Current Control
The system voltages can be written as Based on Kirchhoff's voltage law, the AC-side current control model can be derived as where = , = , and = . Transforming Equation (2) into the dq rotating frame results in Alternative phase opposition disposition sine pulse width modulation (APOD-SPWM) strategy.

AC-Side Current Control
The system voltages can be written as Based on Kirchhoff's voltage law, the AC-side current control model can be derived as where Transforming Equation (2) into the dq rotating frame results in The capacitance of the capacitors will decrease slowly as time goes on, and the shunt power loss is not the same during different running states. Let where C is the nominal value of the total dc capacitance value, Y is the estimated value of total shunt loss, ∆c reflects the deviation capacity of the two capacitors, and ∆y reflects the uneven shunt loss between the two DC-side capacitors [30].
Substituting Equation (22) into Equations (20) and (21) yields Equations (23) and (24) show the basic mathematical model of DC-side voltages with parametric perturbation. From this model, it can be seen that u 1 and u 2 can be regulated by i p + i n and i p − i n .

Instantaneous Value of i p + i n and i p − i n
In general, the switch function s x with zero-sequence dc component s 0 can be written as where m is the modulation index and 0 < m < 1. δ is the phase angle between the output voltage of the converter and the system voltage, −π/2 < δ < π/2. It is assumed that the output currents are sinusoidal, as in the following equations: where |I vd | and |I vq | are the amplitudes of active current and reactive current, respectively, that are related to the converter. Base on the polarity of s a , s b , and s c , a complete primitive period can be divided into six parts, as shown in Figure 3, where ωt 1 . . . ωt 7 are the zero-crossing points of s x respectively, and From Equations (12)- (15) and Figure 3, the instantaneous values of and can be obtained and are shown in Table 1.   (17) and (18), and Table 1, the instantaneous values of + and − can be derived and are shown in Table 2. Table 2. Instantaneous values of + and − .

The Neutral-Point Potential Model
From Equations (25) and (26), the following can be directly obtained: Then + can be deduced from Equation (27) and Table 2, where From Equations (12)- (15) and Figure 3, the instantaneous values of i px and i nx can be obtained and are shown in Table 1.  From Equations (17) and (18), and Table 1, the instantaneous values of i p + i n and i p − i n can be derived and are shown in Table 2. Table 2. Instantaneous values of i p + i n and i p − i n .

The Neutral-Point Potential Model
From Equations (25) and (26), the following can be directly obtained: Then i p + i n can be deduced from Equation (27) and Table 2, where The instantaneous value of i p − i n shown in Table 2 is not always the same. In order to analyze and control the DC-side voltages, the generalized state-space averaging method can be used, which is a mature tool for large signal, dynamic modeling of power converters [31]. Here, where ω = 2π/T, and x k (t) is the kth coefficients of Fourier series expansion of x(t).
Only the DC component within one fundamental period can be taken into consideration for the DC-side voltage control. Thus Because of s 0 , the interval lengths of Part I, III and V in Figure 3 are not equal to the interval lengths of parts II, IV and VI, which results in a DC component of i p − i n . From Equations (25) and (26), and Table 2, it can be deduced that Because s 0 ≈ 0, it can be assumed that From Equation (34), Equation (33) can be rewritten as Taking the zeroth averages of both sides of Equations (23) and (24), considering Equations (29)-(31) and (35), the following is obtained where u 1 0 and u 2 0 are the DC components of u 1 and u 2 .
Suppose that under DC voltage stable control (which may not be necessary under some operation conditions, such as in renewable energy based applications), u 1 0 = 0, and d u 1 0 dt = 0, then from Equation (36) the following can be obtained Equation (39) is the accurate mathematical model of the neutral-point potential drift in three-level NPC converters based on the SPWM strategy with parametric perturbations and zero-sequence voltage injections. This model is simple and direct but very interesting and valuable.
From Equation (39), the stable drift potential value with parametric perturbation and zero-sequence voltage injection can be easily obtained as Equation (40) shows the relationship between the drift potential value and all AC-and DC-side variables by quantitative analysis. The relationships are very clear.
When s 0 = 0, a stable value can be derived as In order to adjust u 2 0 = 0, the required zero-sequence component can be easily obtained as . Actually, the parametric perturbation ∆y is associated with the inconsistent characteristics of power electronic switches and unequal shunt resistances. If ∆y = 0, the potential drift may still exist because of the unexpected zero-sequence component from digital implementation in the modulation signal.

Balancing Control
The DC link of three-level NPC converters is connected by two series capacitors, and the purpose of DC-side voltage control is to maintain the two voltages at an equal and prespecified level. Thus, control can be divided into two parts: (1) Maintain U 1 + U 2 at a prespecified level, which can be called stable control of the DC-side voltage, and (2) Maintain U 1 and U 2 as equal, which can be called DC-side voltage balancing control.
Stable control of the DC-side voltage can be easily obtained from the analytical techniques developed for the two-level converters. If the converter has a DC voltage source, such as that used in renewable energy-based applications, stable control is not necessary.
It is well known that by injecting a zero-sequence voltage, the DC-side voltage balancing control can be realized. However, existing strategies do not take the influence of the active current I vd of the converter into consideration.
Equation (39) shows that I vd is very important for the DC-side voltage balancing control. The injected zero-sequence voltage can be used to adjust the potential drift with the combined action of I vd directly. Thus, it is very difficult to realize the DC link voltage balancing control if the converter is used in four-quadrant operation mode.
Taking the polarity and amplitude of I vd into consideration, the DC-side voltage balancing control can be realized, as shown in Figure 4, where I vd can be calculated from Equation (46). Actually, the parametric perturbation ∆y is associated with the inconsistent characteristics of power electronic switches and unequal shunt resistances. If ∆y = 0, the potential drift may still exist because of the unexpected zero-sequence component from digital implementation in the modulation signal.

Balancing Control
The DC link of three-level NPC converters is connected by two series capacitors, and the purpose of DC-side voltage control is to maintain the two voltages at an equal and prespecified level. Thus, control can be divided into two parts: (1) Maintain + at a prespecified level, which can be called stable control of the DC-side voltage, and (2) Maintain U1 and U2 as equal, which can be called DCside voltage balancing control.
Stable control of the DC-side voltage can be easily obtained from the analytical techniques developed for the two-level converters. If the converter has a DC voltage source, such as that used in renewable energy-based applications, stable control is not necessary.
It is well known that by injecting a zero-sequence voltage, the DC-side voltage balancing control can be realized. However, existing strategies do not take the influence of the active current of the converter into consideration.
Equation (39) shows that is very important for the DC-side voltage balancing control. The injected zero-sequence voltage can be used to adjust the potential drift with the combined action of directly. Thus, it is very difficult to realize the DC link voltage balancing control if the converter is used in four-quadrant operation mode.
Taking the polarity and amplitude of into consideration, the DC-side voltage balancing control can be realized, as shown in Figure 4, where can be calculated from Equation (46).

Calculating the Value of I vd
The value of I vd is very important for the voltage balancing control, but it cannot be directly obtained from sampling or coordinate transformation.
Suppose that u 2 = 0, from Equation (16), then the output voltage v abc can be written as By transforming v abc into the dq rotating frame, based on Equations (4) and (7), it can be deduced that Transforming I abc shown in Equation (26) into the dq rotating frame, based on Equations (4) and (5), I vd and I vq can be obtained as Substituting Equations (42) and (43) into Equations (44) and (45), replacing I d and I q with I * d and I * q , the values of I vd and I vq can be deduced as

Simulation Analysis
A simulation model based on the topology shown in Figure 1 is set up by using MATLAB/Simulink. The control block is shown in Figure 5, and simulation parameters are shown in Table 3. In this case, the DC link has a DC voltage source, and voltage stable control is not needed here. The reference currents I * d and I * q will be set by the control system under different working conditions, including but not limited to, renewable energy applications. . .   (22), it can be deduced that The existence of 〈 〉 may be caused by ∆y and ∆c, which reflect the difference between the upper and lower sides. The amplitude may be influenced by Y and C. In order to get the relationship, set = 0 at first, and the current references can be fixed such as * = * = 50 A so as to get a certain value of . Figure 6 shows the waveforms of u2 under different Yp1, Yp2, C1, and C2 when = 0. The values of ∆y, ∆c, Y, and C can be obtained from Equation (48), shown in Table 4.  From Equation (22), it can be deduced that The existence of u 2 0 may be caused by ∆y and ∆c, which reflect the difference between the upper and lower sides. The amplitude may be influenced by Y and C. In order to get the relationship, set s 0 = 0 at first, and the current references can be fixed such as I * d = I * q = 50 A so as to get a certain value of Y p . Figure 6 shows the waveforms of u 2 under different Y p1 , Y p2 , C 1 , and C 2 when s 0 = 0. The values of ∆y, ∆c, Y, and C can be obtained from Equation (48), shown in Table 4.
The existence of 〈 〉 may be caused by ∆y and ∆c, which reflect the difference between the upper and lower sides. The amplitude may be influenced by Y and C. In order to get the relationship, set = 0 at first, and the current references can be fixed such as * = * = 50 A so as to get a certain value of . Figure 6 shows the waveforms of u2 under different Yp1, Yp2, C1, and C2 when = 0. The values of ∆y, ∆c, Y, and C can be obtained from Equation (48), shown in Table 4.        Under the conditions shown in Figure 6, the output currents always track the reference currents very well without steady error. The system voltage u a , reference current i * a , and output current i a of phase A in abc frame under the conditions of Figure 6f are shown in Figure 7. Under the conditions shown in Figure 6, the output currents always track the reference currents very well without steady error. The system voltage , reference current * , and output current of phase A in abc frame under the conditions of Figure  From Figure 6a,c-f, it can be obtained that ∆y is proportional to 〈 〉 with opposite polarity. From Figure 6a,b, it can be seen that ∆c has no influence on 〈 〉 . From Figure 6c,g, it can be obtained that Y is inversely proportional to 〈 〉 . From Figure 6c,h, it can be seen that C has no influence on the stable value 〈 〉 . Thus, the relationships between 〈 〉 and ∆y, ∆c, Y, and C all correspond to Equation (39) from Figure 6.
Because the reference currents in Figure 6 are the same, the estimated value of Yp from Figure  6c can be used in Figure 6d-h. From this value, the calculated values of 〈 〉 in Figure 6d-h can be derived, as shown in Table 4. It can be seen that the simulation values and calculated values are very close, which verified Equation (39) by a quantitative relationship when = 0.
From Figure 6, it also can be observed that u2 mainly has the DC component and third component, and C influences the amplitude of the third component, which can be easily derived.
By introducing , the waveforms of u2 with different * and * are shown in Figure 8. The values of and can be obtained from Equations (46) and (47), shown in Table 5. From Figure 6a,c-f, it can be obtained that ∆y is proportional to u 2 0 with opposite polarity. From Figure 6a,b, it can be seen that ∆c has no influence on u 2 0 . From Figure 6c,g, it can be obtained that Y is inversely proportional to u 2 0 . From Figure 6c,h, it can be seen that C has no influence on the stable value u 2 0 . Thus, the relationships between u 2 0 and ∆y, ∆c, Y, and C all correspond to Equation (39) from Figure 6.
Because the reference currents in Figure 6 are the same, the estimated value of Y p from Figure 6c can be used in Figure 6d-h. From this value, the calculated values of u 2 0 in Figure 6d-h can be derived, as shown in Table 4. It can be seen that the simulation values and calculated values are very close, which verified Equation (39) by a quantitative relationship when s 0 = 0. From Figure 6, it also can be observed that u 2 mainly has the DC component and third component, and C influences the amplitude of the third component, which can be easily derived.
By introducing s 0 , the waveforms of u 2 with different I * d and I * q are shown in Figure 8. The values of I vd and I vq can be obtained from Equations (46) and (47), shown in Table 5. Under the conditions shown in Figure 6, the output currents always track the reference currents very well without steady error. The system voltage , reference current * , and output current of phase A in abc frame under the conditions of Figure 6f are shown in Figure 7. From Figure 6a,c-f, it can be obtained that ∆y is proportional to 〈 〉 with opposite polarity. From Figure 6a,b, it can be seen that ∆c has no influence on 〈 〉 . From Figure 6c,g, it can be obtained that Y is inversely proportional to 〈 〉 . From Figure 6c,h, it can be seen that C has no influence on the stable value 〈 〉 . Thus, the relationships between 〈 〉 and ∆y, ∆c, Y, and C all correspond to Equation (39) from Figure 6.
Because the reference currents in Figure 6 are the same, the estimated value of Yp from Figure  6c can be used in Figure 6d-h. From this value, the calculated values of 〈 〉 in Figure 6d-h can be derived, as shown in Table 4. It can be seen that the simulation values and calculated values are very close, which verified Equation (39) by a quantitative relationship when = 0.
From Figure 6, it also can be observed that u2 mainly has the DC component and third component, and C influences the amplitude of the third component, which can be easily derived.     From Figures 6a and 8a-d, it can be obtained that s 0 is proportional to u 2 0 with an opposite polarity. From Figure 8d,e, it can be obtained that I vd influences u 2 0 with an opposite polarity. From Figure 8g,h, it can be obtained that I vq has no influence on u 2 0 . Thus, the relationships between u 2 0 and I vd , I vq , and s 0 all correspond to Equation (39) from Figure 8.
Substituting U* = 380 V, ∆y = 0, s 0 = 0.002, I vd = 40.8 A, and u 2 0 = −12.6 V from Figure 8a into Equation (39), the estimated value of Y p can be derived as From this value, the calculated values of u 2 0 in Figure 8b-d can be derived, as shown in Table 5.
From this value, the calculated values of u 2 0 in Figure 8f can be derived, as shown in Table 5. From Figure 8e,f, it can be observed that the balancing control can be realized based on the combined action of the injected zero-sequence voltage and active current.
Thus, the accuracy of Equation (39) is sufficiently verified.

DC Voltage Balancing Control
This case study demonstrates the effectiveness of DC voltage balancing control by considering I vd and s 0max = 0.05.
Initially the converter is under a steady-state condition with reference currents I * d1 and I * q1 without DC voltage balancing control. At t = 10.0 s the balancing control has been used. At t = 20.0 s the reference currents have been changed into I * d2 and I * q2 . Figure 9 shows the waveforms under the traditional balancing control, which do not take the polarity of I vd into consideration. It can be seen that the potential drift is worsened when the active current is reversed. Figure 10 shows the waveforms under this proposed balancing control. It can be observed that the potential drift is regulated within a narrow range even in response to the current reversal. From this value, the calculated values of 〈 〉 in Figure 8f can be derived, as shown in Table 5. From Figure 8e,f, it can be observed that the balancing control can be realized based on the combined action of the injected zero-sequence voltage and active current.
Thus, the accuracy of Equation (39) is sufficiently verified.

DC Voltage Balancing Control
This case study demonstrates the effectiveness of DC voltage balancing control by considering and = 0.05. Initially the converter is under a steady-state condition with reference currents * and * without DC voltage balancing control. At t = 10.0 s the balancing control has been used. At t = 20.0 s the reference currents have been changed into * and * . Figure 9 shows the waveforms under the traditional balancing control, which do not take the polarity of into consideration. It can be seen that the potential drift is worsened when the active current is reversed. Figure 10 shows the waveforms under this proposed balancing control. It can be observed that the potential drift is regulated within a narrow range even in response to the current reversal.   Figure 11 shows the waveforms without considering the amplitude of . It can be seen that the potential drift has been controlled within a certain range. However, the first parameters are much larger when the reference currents have been changed. The instruction value swings between −0.05 to 0.05. Figure 12 shows the waveform under this proposed balancing control with dynamic adjusting parameters by taking the amplitude of into consideration. The instruction value can converge rapidly in Figure 12.   Figure 11 shows the waveforms without considering the amplitude of . It can be seen that the potential drift has been controlled within a certain range. However, the first parameters are much larger when the reference currents have been changed. The instruction value swings between −0.05 to 0.05. Figure 12 shows the waveform under this proposed balancing control with dynamic adjusting parameters by taking the amplitude of into consideration. The instruction value can converge rapidly in Figure 12.  Figure 11 shows the waveforms without considering the amplitude of I vd . It can be seen that the potential drift has been controlled within a certain range. However, the first parameters are much larger when the reference currents have been changed. The instruction value s 0 swings between −0.05 to 0.05. Figure 12 shows the waveform under this proposed balancing control with dynamic adjusting parameters by taking the amplitude of I vd into consideration. The instruction value s 0 can converge rapidly in Figure 12.  Figure 11. Waveforms without considering the amplitude of (a) DC voltages. (b) The instruction value s0.   Figure 11. Waveforms without considering the amplitude of (a) DC voltages. (b) The instruction value s0. Thus, compared with the traditional balancing control, the effectiveness of DC voltage balancing control with considering I vd has been verified.

Experimental Verification
As depicted in Figure 13, the experimental platform was set up. Converter I and II have a common DC link, where converter I is used to supply the DC voltage source, and converter II is used to validate the effectiveness of the model and voltage balancing control. Two signals are used to transfer the converters' running state directly. If one converter is working, the other should work immediately, and vice versa.  Thus, compared with the traditional balancing control, the effectiveness of DC voltage balancing control with considering has been verified.

Experimental Verification
As depicted in Figure 13, the experimental platform was set up. Converter I and II have a common DC link, where converter I is used to supply the DC voltage source, and converter II is used to validate the effectiveness of the model and voltage balancing control. Two signals are used to transfer the converters' running state directly. If one converter is working, the other should work immediately, and vice versa.
Running State The control blocks of converter I and II are the same and are shown in Figure 5. The reference current * of converter I comes from the DC voltage stable control, which is used to maintain DC link stability. The reference currents of converter II are set from the human machine interface (HMI). The two converters use the same module with the same parameters of U* = 380 V, Ls = 0.3 mH, R1 = R2 = 24 kΩ, C1 = C2 = 10,000 uF, and carrier frequency fc = 9.6 kHz.
The control board shown in Figure 14 is composed of an advanced risc machine (ARM) processor and field programmable gate array (FPGA). The arm processor is used to realize the calculation of root mean square (rms) values, system-level protection, running processes, and communicating with HMI. The sample module, digital phase-locked loop (DPLL), current control, and DC voltage control are realized in the FPGA. The realization diagram of the control system is shown in Figure 15. The control blocks of converter I and II are the same and are shown in Figure 5. The reference current I * d of converter I comes from the DC voltage stable control, which is used to maintain DC link stability. The reference currents of converter II are set from the human machine interface (HMI). The two converters use the same module with the same parameters of U* = 380 V, L s = 0.3 mH, R 1 = R 2 = 24 kΩ, C 1 = C 2 = 10,000 uF, and carrier frequency fc = 9.6 kHz.
The control board shown in Figure 14 is composed of an advanced risc machine (ARM) processor and field programmable gate array (FPGA). The arm processor is used to realize the calculation of root mean square (rms) values, system-level protection, running processes, and communicating with HMI. The sample module, digital phase-locked loop (DPLL), current control, and DC voltage control are realized in the FPGA. The realization diagram of the control system is shown in Figure 15.     Figure 15. Realization diagram of the control system. Figure 16 shows the waveforms of the system voltage , output current of converter II, DCside up and lower voltages UII1 and UII2 without the DC voltage balancing control. The reference currents are * = * = 50 A. From Figure 16b, it can be seen that there is deviation, and 〈 2 〉 0 = 5 V, which means that the upper loss is smaller than lower loss, ∆y < 0.   Figure 16 shows the waveforms of the system voltage u a , output current i a of converter II, DC-side up and lower voltages U II1 and U II2 without the DC voltage balancing control. The reference currents are I * d = I * q = 50 A. From Figure 16b, it can be seen that there is deviation, and u 2 0 = 5 V, which means that the upper loss is smaller than lower loss, ∆y < 0.    Figure 15. Realization diagram of the control system. Figure 16 shows the waveforms of the system voltage , output current of converter II, DCside up and lower voltages UII1 and UII2 without the DC voltage balancing control. The reference currents are * = * = 50 A. From Figure 16b, it can be seen that there is deviation, and 〈 〉 = 5 V, which means that the upper loss is smaller than lower loss, ∆y < 0.  In order to verify the relationship between u 2 0 and ∆y, an external resistor Re = 8 kΩ is used. Figure 17 shows the waveforms of U II1 and U II2 when Re is connected. From Figure 17a, it can be seen that the deviation becomes smaller when the resistor connected from point P 2 to O 2 increases the upper-side loss. From Figure 17b, it can be seen that the deviation becomes bigger when the resistor connected from point N 2 to O 2 increases the lower-side loss. This relationship corresponds to Equation (39).
In order to verify the relationship between 〈 〉 and ∆y, an external resistor Re = 8 kΩ is used. Figure 17 shows the waveforms of UII1 and UII2 when Re is connected. From Figure 17a, it can be seen that the deviation becomes smaller when the resistor connected from point P2 to O2 increases the upper-side loss. From Figure 17b, it can be seen that the deviation becomes bigger when the resistor connected from point N2 to O2 increases the lower-side loss. This relationship corresponds to Equation (39). In order to verify the relationship between 〈 〉 and ∆c, an external capacitor = 10,000 uF was used. Figure 18 shows the waveforms of UII1 and UII2 when is connected. From this figure, it can be seen that the deviation is nearly stable when the capacitor is connected, which corresponds to Equation (39). It also can be found that affects the amplitude of the third component. In order to validate the effectiveness of voltage balancing control, the current reference values were changed, and the waveforms of U1 and U2 are shown in Figure 19. From this figure, it can be seen that the balancing control considering works very well. In order to verify the relationship between u 2 0 and ∆c, an external capacitor C add = 10,000 uF was used. Figure 18 shows the waveforms of U II1 and U II2 when C add is connected. From this figure, it can be seen that the deviation is nearly stable when the capacitor is connected, which corresponds to Equation (39). It also can be found that C add affects the amplitude of the third component. Figure 17 shows the waveforms of UII1 and UII2 when Re is connected. From Figure 17a, it can be seen that the deviation becomes smaller when the resistor connected from point P2 to O2 increases the upper-side loss. From Figure 17b, it can be seen that the deviation becomes bigger when the resistor connected from point N2 to O2 increases the lower-side loss. This relationship corresponds to Equation (39). In order to verify the relationship between 〈 〉 and ∆c, an external capacitor = 10,000 uF was used. Figure 18 shows the waveforms of UII1 and UII2 when is connected. From this figure, it can be seen that the deviation is nearly stable when the capacitor is connected, which corresponds to Equation (39). It also can be found that affects the amplitude of the third component. In order to validate the effectiveness of voltage balancing control, the current reference values were changed, and the waveforms of U1 and U2 are shown in Figure 19. From this figure, it can be seen that the balancing control considering works very well. In order to validate the effectiveness of voltage balancing control, the current reference values were changed, and the waveforms of U 1 and U 2 are shown in Figure 19. From this figure, it can be seen that the balancing control considering I vd works very well. In order to verify the relationship between 〈 〉 and ∆y, an external resistor Re = 8 kΩ is used. Figure 17 shows the waveforms of UII1 and UII2 when Re is connected. From Figure 17a, it can be seen that the deviation becomes smaller when the resistor connected from point P2 to O2 increases the upper-side loss. From Figure 17b, it can be seen that the deviation becomes bigger when the resistor connected from point N2 to O2 increases the lower-side loss. This relationship corresponds to Equation (39). In order to verify the relationship between 〈 〉 and ∆c, an external capacitor = 10,000 uF was used. Figure 18 shows the waveforms of UII1 and UII2 when is connected. From this figure, it can be seen that the deviation is nearly stable when the capacitor is connected, which corresponds to Equation (39). It also can be found that affects the amplitude of the third component.  Under traditional balancing control, the control effect is nearly the same if the reference currents are the same over the entire time. If the polarity of is changed, equipment will stop working because DC overvoltage is protected.

Conclusions
A simple and direct, but very interesting and valuable, model of neutral-point potential in threelevel NPC converters is proposed. From this model, simulation and experiment, some conclusions can be drawn from this model, as follows: (1) The basic reason for the neutral-point potential drift is the uneven shunt loss caused by parametric perturbation, and the capacitance error has no influence on it. (2) Zero-sequence voltage can be used to control the potential drift with the combination of the active current of the converter. (3) The total shunt loss, which is related to the output voltages and currents of the converter, is inversely proportional to the stable drift potential value. (4) The total DC capacitance has no influence on the stable drift potential value, but it affects the dynamic performance and amplitude of the third component.
Future work will focus on NPC converters with a higher number of levels based on the proposed analysis method. Under traditional balancing control, the control effect is nearly the same if the reference currents are the same over the entire time. If the polarity of I vd is changed, equipment will stop working because DC overvoltage is protected.

Conclusions
A simple and direct, but very interesting and valuable, model of neutral-point potential in three-level NPC converters is proposed. From this model, simulation and experiment, some conclusions can be drawn from this model, as follows: (1) The basic reason for the neutral-point potential drift is the uneven shunt loss caused by parametric perturbation, and the capacitance error has no influence on it. (2) Zero-sequence voltage can be used to control the potential drift with the combination of the active current of the converter. (3) The total shunt loss, which is related to the output voltages and currents of the converter, is inversely proportional to the stable drift potential value. (4) The total DC capacitance has no influence on the stable drift potential value, but it affects the dynamic performance and amplitude of the third component.
Future work will focus on NPC converters with a higher number of levels based on the proposed analysis method.