Flux-Balance Control for LLC Resonant Converters with Center-Tapped Transformers

: LLC resonant converters with center-tapped transformers are widely used. However, these converters su ﬀ er from a ﬂux walking issue, which causes a larger output ripple and possible transformer saturation. In this paper, a ﬂux-balance control strategy is proposed for resolving the ﬂux walking issue. First, the DC magnetizing current generated due to the mismatched secondary-side leakage inductances, and its e ﬀ ects on the voltage gain are analyzed. From the analysis, the ﬂux-balance control strategy, which is based on the original output-voltage control loop, is proposed. Since the DC magnetizing current is not easily measured, a current sensing strategy with a current estimator is proposed, which only requires one current sensor and is easy to estimate the DC magnetizing current. Finally, a simulation scheme and a hardware prototype with rated output power 200 W, input voltage 380 V, and output voltage 20 V is constructed for veriﬁcation. The simulation and experimental results show that the proposed control strategy e ﬀ ectively reduces the DC magnetizing current and output voltage ripple at mismatched condition.


Introduction
The LLC resonant converter is widely used in many different applications such as onboard chargers, server power systems, laptops, desktops, photovoltaic regeneration systems. Owing to the characteristics of zero-voltage-switching (ZVS) at the primary side and zero-current-switching (ZCS) at the secondary side, high efficiency and high power density of the LLC converter are achieved [1][2][3][4][5][6][7]. The half-bridge (HB) and full-bridge (FB) with the center-tapped transformer rectifier topologies shown in Figure 1 are the most commonly used topologies of the LLC resonant converter. Thanks to the center-tapped transformer, only two rectifying diodes are necessary at the secondary side [8][9][10][11]. Without the center-tap, it would be required to implement a full-wave rectifier. side currents imbalance will reflect upon the magnetizing inductance on the primary side. Therefore, the magnetizing current will have a DC component, which will lead to the flux walking and possible transformer core saturation.
(a) (b)  Figure 2b shows the key waveforms of the LLC resonant converter operating below the resonant conditions with the mismatched leakage inductances in the secondary side windings. In Figure 2b, the current waveforms of the diode 1 and diode 2 are not symmetrical. The magnetizing current (iLm) will, therefore, contain a DC component. Since the resonant capacitance is in series with the primary side, the resonant current (iLr) will not have a DC component from charge balance concept. Besides,  Figure 2a shows the key waveforms of the LLC resonant converter operating below the resonant frequency with the matching leakage inductances in both secondary side windings, where v gs1 and v gs2 are the driving signals of the MOSFET Q 1 and Q 2 , respectively. Figure 2a reveals that the current waveforms of the diode 1 (i D1 ) and diode 2 (i D2 ) are symmetrical, and energy flows through the diode 1 and diode 2 in the positive and negative cycles, respectively. In Figure 2a, the magnetizing current will have no DC component.  Figure 2b shows the key waveforms of the LLC resonant converter operating below the resonant conditions with the mismatched leakage inductances in the secondary side windings. In Figure 2b, the current waveforms of the diode 1 and diode 2 are not symmetrical. The magnetizing current (iLm) will, therefore, contain a DC component. Since the resonant capacitance is in series with the primary side, the resonant current (iLr) will not have a DC component from charge balance concept. Besides, the mismatched condition considers not only the leakage inductances of the secondary side windings of the transformer but also the parasitic inductances of the printed-circuit-board (PCB) traces on the secondary side. To improve the flux walking issue in the LLC resonant converter, improved winding structures for the secondary side were proposed [12][13][14]. The coupling coefficients between the primary side and two secondary sides were increased to mitigate the flux walking issue [12]. The further improved method is used in the Bifilar winding structure to overcome this problem [13]. The flux distribution of the non-symmetrical structure of the secondary side windings were analyzed in [14]. However, they cannot consider the mismatch problems caused by the PCB circuit traces.
According to abovementioned issue, a flux-balance control strategy, which is based on the original output-voltage control loop, is proposed in this paper. The flux-balance control is added to improve the magnetizing current imbalance problem caused by the secondary side mismatches.
Besides, the DC magnetizing current of the LLC resonant converter is difficult to sense directly. An indirect method to sense the magnetizing current was used [15], which involved sensing the currents at the primary and secondary side, simultaneously and subtracting them to obtain the magnetizing current. Then, the DC component was obtained using a low-pass filter. This solution, However, practical LLC resonant converters with center-tapped transformers contain a flux walking issue, which causes a larger output ripple and possible transformer saturation [12][13][14]. This is because the secondary side windings are usually not symmetrical in practical manufacture. The mismatched leakage inductances are generated in the secondary side windings, which causes an imbalance in the secondary side currents, resulting in a larger output voltage ripple. The secondary side currents imbalance will reflect upon the magnetizing inductance on the primary side. Therefore, the magnetizing current will have a DC component, which will lead to the flux walking and possible transformer core saturation. Figure 2b shows the key waveforms of the LLC resonant converter operating below the resonant conditions with the mismatched leakage inductances in the secondary side windings. In Figure 2b, the current waveforms of the diode 1 and diode 2 are not symmetrical. The magnetizing current (i Lm ) will, therefore, contain a DC component. Since the resonant capacitance is in series with the primary side, the resonant current (i Lr ) will not have a DC component from charge balance concept. Besides, the mismatched condition considers not only the leakage inductances of the secondary side windings of the transformer but also the parasitic inductances of the printed-circuit-board (PCB) traces on the secondary side.
To improve the flux walking issue in the LLC resonant converter, improved winding structures for the secondary side were proposed [12][13][14]. The coupling coefficients between the primary side and two secondary sides were increased to mitigate the flux walking issue [12]. The further improved method is used in the Bifilar winding structure to overcome this problem [13]. The flux distribution of the non-symmetrical structure of the secondary side windings were analyzed in [14]. However, they cannot consider the mismatch problems caused by the PCB circuit traces.
According to abovementioned issue, a flux-balance control strategy, which is based on the original output-voltage control loop, is proposed in this paper. The flux-balance control is added to improve the magnetizing current imbalance problem caused by the secondary side mismatches. Besides, the DC magnetizing current of the LLC resonant converter is difficult to sense directly. An indirect method to sense the magnetizing current was used [15], which involved sensing the currents at the primary and secondary side, simultaneously and subtracting them to obtain the magnetizing current. Then, the DC component was obtained using a low-pass filter. This solution, however, required several current sensing devices, which increased the circuit cost; moreover, the low-pass filter produced a slow dynamic response. Therefore, this paper proposes a simple magnetizing current sensing strategy with a DC current estimation scheme to overcome the abovementioned issue.
Moreover, for small-signal model, the mathematical methods for deriving the small-signal dynamic model of the LLC resonant converter were developed [16][17][18][19]. However, these works focused only on the switching frequency to output voltage transfer function. Besides, matching with circuit ac sweep simulation occurs only under specific operating conditions. Nevertheless, system identification [20,21] is a useful method to obtain the small-signal model of the system without using any complex mathematical model. Therefore, the system identification [21] is used to obtain the small-signal models of the LLC resonant converter for controllers design in this paper.
The remainder of this paper is organized as follows. Section 2 analyzes the mismatched leakage inductances effects of the secondary side on the DC magnetizing current and voltage gain. Section 3 describes the proposed control strategy with the magnetizing current sensing and the DC magnetizing current estimation. Section 4 describes the controller designs for the flux-balance loop and output-voltage loop, which are based on the transfer functions obtained by using the system identification tool of MATLAB (R2018b, MathWorks, Natick, MA, USA). Section 5 presents the simulated and experimental results, to verify the effectiveness of the proposed control strategy. Finally, Section 6 provides the conclusions. Figure 3 shows the DC current path in the LLC resonant tank when the leakage inductances at the secondary side are mismatched. It is assumed that the leakage inductance of the positive-cycle loop at the secondary side (L lk2,pos ) is smaller than the leakage inductance of the negative-cycle loop at the secondary side (L lk2,neg ). According to Kirchhoff's current law (KCL), the relationship among i Lr , i Lm , and i Dx can be expressed as follows

Analysis of the Magnetizing Current DC Value
where n is the turns ratio of the transformer. Since the resonant capacitance is in series with the input of the transformer, the DC current of the resonant inductor is zero. That is, the average resonant inductor current in a switching period is zero in steady-state, and can be expressed as follows Based on (3), the relationship between the magnetizing DC current and difference in the DC currents of both diodes can be expressed as follows where I D1,DC and I D2,DC are the DC currents of the diodes at secondary side. Equation (4) shows that the magnetizing DC current is proportional to the difference between I D1,DC and I D2,DC with the turns ratio n. Therefore, the largest I Lm,DC would be induced for the largest current mismatch in the secondary side condition. ratio n. Therefore, the largest ILm,DC would be induced for the largest current mismatch in the secondary side condition.

Analysis of the Voltage Gain under Mismatched Condition
A non-ideal transformer equivalent circuit can be expressed by the model shown in Figure 4a, which is called the "T model" [22,23]. In Figure 4a, the leakage inductances are distributed at the primary and secondary sides, separately. This circuit is not suitable for the analysis of the LLC resonant converter. On the other hand, Figure 4b shows the "L model" [22,23]. In this model, the leakage inductance at the secondary side is removed. Therefore, it is suitably used in the LLC resonant tank for analysis.
For center-tapped applications, the L model of the transformer can be separated into the positive and negative cycle models. For a matched condition, the parameters of the L model for the positive and negative cycle will be the same. This will not be the case for the mismatched condition because the leakage inductances at the secondary side would affect the resonant parameters during the positive and negative cycles. Figure 5 shows the equivalent circuit models of the LLC resonant tank for the positive (lower left) and negative (lower right) cycles. The relative parameters of the L model during the positive and negative cycles can be derived from Figure 4 and is presented as follows

Analysis of the Voltage Gain under Mismatched Condition
A non-ideal transformer equivalent circuit can be expressed by the model shown in Figure 4a, which is called the "T model" [22,23]. In Figure 4a, the leakage inductances are distributed at the primary and secondary sides, separately. This circuit is not suitable for the analysis of the LLC resonant converter. On the other hand, Figure 4b shows the "L model" [22,23]. In this model, the leakage inductance at the secondary side is removed. Therefore, it is suitably used in the LLC resonant tank for analysis.   For center-tapped applications, the L model of the transformer can be separated into the positive and negative cycle models. For a matched condition, the parameters of the L model for the positive and negative cycle will be the same. This will not be the case for the mismatched condition because the leakage inductances at the secondary side would affect the resonant parameters during the positive and negative cycles. Figure 5 shows the equivalent circuit models of the LLC resonant tank for the positive (lower left) and negative (lower right) cycles. The relative parameters of the L model during the positive and negative cycles can be derived from Figure 4 and is presented as follows L r,h = L ext + L lk1 + L m n 2 L lk2,h Energies 2019, 12, 3211 5 of 18 h = pos : duringthepositivecycle neg : duringthenegativecycle (8) where L m indicates the magnetizing inductance of the transformer, L lk1 and L lk2,h express the leakage inductances at the primary and secondary sides of the transformer, respectively, m h indicates the equivalent turns ratio of the L model, L ext represents the external resonant inductance, L p,h expresses the equivalent paralleled inductance of the L model, and L r,h is the total equivalent resonant inductance of the L model. Therefore, the parameters of the L model during the positive and negative cycles can be obtained using (5)- (8).   The voltage gain during the positive and negative cycles can be expressed as follows  The voltage gain during the positive and negative cycles can be expressed as follows Energies 2019, 12, 3211 6 of 18 where f r indicates the resonant frequency, C r is the resonant capacitance, Q h is the qualify factor, R ac is the equivalent ac load resistance, R o is the load resistance, f s is the switching frequency, f n,h is the normalized frequency, and L n,h is the ratio between L p,h and L r,h . Based on (9)- (14), the voltage gain curves during the positive and negative cycles can be drawn as shown in Figure 6. The solid lines represent the nominal Q-value condition and dashed lines express the high Q-value condition. Assuming the normal leakage inductance L lk,2n = L lk,2,pos = L lk,2,neg at the secondary side, i.e., at matched condition, f n,pos and f n,neg would be one as indicated by the curve a (i.e., maroon solid line) with the normal operating point indicated by the sky blue circle in Figure 6. When operating under the mismatched condition and assuming the leakage inductances at the secondary side are satisfying L lk,2n = L lk,2,pos < L lk,2,neg , the voltage gain during the positive cycle follows the original curve a (i.e., maroon solid line); during the negative cycle, the voltage gain curve moves toward the left as shown by the curve b (i.e., light blue solid line). Under the mismatched condition, the voltage gain also operates at M = 1.05, because of the voltage loop regulation, and the operating point shifts to the point indicated by the pink circle.
where fr indicates the resonant frequency, Cr is the resonant capacitance, Qh is the qualify factor, Rac is the equivalent ac load resistance, Ro is the load resistance, fs is the switching frequency, fn,h is the normalized frequency, and Ln,h is the ratio between Lp,h and Lr,h. Based on (9)- (14), the voltage gain curves during the positive and negative cycles can be drawn as shown in Figure 6. The solid lines represent the nominal Q-value condition and dashed lines express the high Q-value condition. Assuming the normal leakage inductance Llk,2n = Llk,2,pos = Llk,2,neg at the secondary side, i.e., at matched condition, fn,pos and fn,neg would be one as indicated by the curve a (i.e. maroon solid line) with the normal operating point indicated by the sky blue circle in Figure     controller, and a variable-frequency-variable-duty-pulse-width-modulator (VFVDPWM). The output of the voltage loop controller controls the switching period of the MOSFETs Q 1 and Q 2 . The output of the flux-balance loop controller offsets the duty ratio of the MOSFETs Q 1 and Q 2 from 0.5. The input of the flux-balance loop controller is the error between i Lm,DC and i Lm,DC,ref , which is zero in steady-state. Thus, the flux-balance loop forces the DC magnetizing current to zero and solves the flux walking issue. The DC estimator estimates the DC magnetizing current, and the i Lm sampling scheme samples relative information of the magnetizing current from the resonant current i Lr . The relationship between the DC magnetizing current and the duty ratio are not direct, because the resonant capacitance is in series between the half-bridge switches and the input of the transformer. According to the proposed flux-balance control, when the duty is regulated, the resonant capacitance to hold the charge balance in steady-state, the DC current of the resonant inductance, therefore, keeps zero, and the rectifier diodes turned off time, therefore, be changed when the duty ratio be regulated. Finally, the magnetizing DC current would be regulated. Detailed descriptions of the functional blocks of the magnetizing current sampling scheme, the DC current estimator, and the VFVDPWM are provided below. loop includes the sampling setup for the magnetizing current, a DC current estimator, a flux-balance loop controller, and a variable-frequency-variable-duty-pulse-width-modulator (VFVDPWM). The output of the voltage loop controller controls the switching period of the MOSFETs Q1 and Q2. The output of the flux-balance loop controller offsets the duty ratio of the MOSFETs Q1 and Q2 from 0.5. The input of the flux-balance loop controller is the error between iLm,DC and iLm,DC,ref, which is zero in steady-state. Thus, the flux-balance loop forces the DC magnetizing current to zero and solves the flux walking issue. The DC estimator estimates the DC magnetizing current, and the iLm sampling scheme samples relative information of the magnetizing current from the resonant current iLr. The relationship between the DC magnetizing current and the duty ratio are not direct, because the resonant capacitance is in series between the half-bridge switches and the input of the transformer. According to the proposed flux-balance control, when the duty is regulated, the resonant capacitance to hold the charge balance in steady-state, the DC current of the resonant inductance, therefore, keeps zero, and the rectifier diodes turned off time, therefore, be changed when the duty ratio be regulated. Finally, the magnetizing DC current would be regulated. Detailed descriptions of the functional blocks of the magnetizing current sampling scheme, the DC current estimator, and the VFVDPWM are provided below.  Figure 8 shows the magnetizing current sampling scheme, where iLr is the resonant current, iLm is the magnetizing current, iLm,p, and iLm,n are the peak values of the magnetizing current during the positive and negative cycles, respectively. The magnetizing current of the LLC resonant converter cannot be measured directly because the magnetizing inductance is an equivalent element in the transformer. However, owing to the LLC resonant converter usually operates with the switching frequency below the resonant frequency, the resonant current is equal to the magnetizing current when the diodes on the secondary side are turned off. As shown in Figure 8, during these intervals, the peak values of the magnetizing current during the positive and negative cycles occur when the respective MOSFET Q1 and Q2, are turned off. According to the previous statement, the sampling pluses of SOCi,p and SOCi,n can be applied from the VFVDPWM, which are generated when the driving signals of MOSFET Q1 and Q2 are turned off, respectively. After that, iLm,p and iLm,n can be sampled during each switching period.  Figure 8 shows the magnetizing current sampling scheme, where i Lr is the resonant current, i Lm is the magnetizing current, i Lm,p , and i Lm,n are the peak values of the magnetizing current during the positive and negative cycles, respectively. The magnetizing current of the LLC resonant converter cannot be measured directly because the magnetizing inductance is an equivalent element in the transformer. However, owing to the LLC resonant converter usually operates with the switching frequency below the resonant frequency, the resonant current is equal to the magnetizing current when the diodes on the secondary side are turned off. As shown in Figure 8, during these intervals, the peak values of the magnetizing current during the positive and negative cycles occur when the respective MOSFET Q 1 and Q 2 , are turned off. According to the previous statement, the sampling pluses of SOC i,p and SOC i,n can be applied from the VFVDPWM, which are generated when the driving signals of MOSFET Q 1 and Q 2 are turned off, respectively. After that, i Lm,p and i Lm,n can be sampled during each switching period.

DC Value Estimation of the Magnetizing Current
This paper proposes the DC value estimation scheme to obtain the DC magnetizing current, which will be used as one of the inputs of the flux-balance controller. Figure 9 shows the magnetizing current waveform (red line), which is similar to a triangular wave (shown by the blue dashed line). The magnetizing DC current can be estimated after the iLm,p and iLm,n are sampled, and is expressed as follows where iLm,DC,est[n] represents the estimated magnetizing DC current. Equation (15) reveals that the estimated magnetizing DC current can be approximated as the sum of iLm,p[n] and iLm,n[n], divided by 2, which is a very simple method to obtain the magnetizing DC current. The block diagram of the DC magnetizing current estimator is shown in Figure 10.

DC Value Estimation of the Magnetizing Current
This paper proposes the DC value estimation scheme to obtain the DC magnetizing current, which will be used as one of the inputs of the flux-balance controller. Figure 9 shows the magnetizing current waveform (red line), which is similar to a triangular wave (shown by the blue dashed line). The magnetizing DC current can be estimated after the i Lm,p and i Lm,n are sampled, and is expressed as follows where i Lm,DC,est [n] represents the estimated magnetizing DC current. Equation (15) reveals that the estimated magnetizing DC current can be approximated as the sum of i Lm,p [n] and i Lm,n [n], divided by 2, which is a very simple method to obtain the magnetizing DC current. The block diagram of the DC magnetizing current estimator is shown in Figure 10.

DC Value Estimation of the Magnetizing Current
This paper proposes the DC value estimation scheme to obtain the DC magnetizing current, which will be used as one of the inputs of the flux-balance controller. Figure 9 shows the magnetizing current waveform (red line), which is similar to a triangular wave (shown by the blue dashed line where iLm,DC,est[n] represents the estimated magnetizing DC current. Equation (15) reveals that the estimated magnetizing DC current can be approximated as the sum of iLm,p[n] and iLm,n[n], divided by 2, which is a very simple method to obtain the magnetizing DC current. The block diagram of the DC magnetizing current estimator is shown in Figure 10.

Variable-Frequency-Variable-Duty-Pulse-Width-Modulator
In conventional LLC resonant converters, the output voltage regulation is achieved by controlling the switching frequency and maintaining the duty ratios of MOSFET Q1 and Q2 at 50%.

Variable-Frequency-Variable-Duty-Pulse-Width-Modulator
In conventional LLC resonant converters, the output voltage regulation is achieved by controlling the switching frequency and maintaining the duty ratios of MOSFET Q 1 and Q 2 at 50%. The proposed flux-balance control scheme utilizes the controlled duty ratio for MOSFET Q 1 for the magnetizing DC current regulation. Figure 11 shows the operating timing of the VFVDPWM, where v carr is the carrier waveform, d Q1 is the duty ratio control signal of MOSFET Q 1 , t s is the switching period control signal. In Figure 11, the slope of v carr is fixed. t s can therefore control the magnitude of v carr to control the switching period. d Q1 , which is equal to 0.5t s in the matched condition, controls the duty ratio of MOSFET Q 1 for the flux-balance loop regulation. SOC i,p is generated when d Q1 equals v carr and SOC i,n is generated when t s equals v carr . Thus, the control signal and magnetizing current sampling pulses of the proposed flux-balance loop can be obtained from Figure 11.

Variable-Frequency-Variable-Duty-Pulse-Width-Modulator
In conventional LLC resonant converters, the output voltage regulation is achieved by controlling the switching frequency and maintaining the duty ratios of MOSFET Q1 and Q2 at 50%. The proposed flux-balance control scheme utilizes the controlled duty ratio for MOSFET Q1 for the magnetizing DC current regulation. Figure 11 shows the operating timing of the VFVDPWM, where vcarr is the carrier waveform, dQ1 is the duty ratio control signal of MOSFET Q1, ts is the switching period control signal. In Figure 11, the slope of vcarr is fixed. ts can therefore control the magnitude of vcarr to control the switching period. dQ1, which is equal to 0.5ts in the matched condition, controls the duty ratio of MOSFET Q1 for the flux-balance loop regulation. SOCi,p is generated when dQ1 equals vcarr and SOCi,n is generated when ts equals vcarr. Thus, the control signal and magnetizing current sampling pulses of the proposed flux-balance loop can be obtained from Figure 11.

Small-Signal Models Built Using System Identification
Unlike the pulse-width-modulation (PWM) converter, the LLC resonant converter is a complex nonlinear system. Therefore, it is difficult to obtain its small-signal model through mathematical derivation. Previously, researchers had developed the mathematical methods for deriving the smallsignal dynamic model of the LLC resonant converter [16][17][18][19]. However, these works focused only on the matching with circuit ac sweep simulation occurs only under specific operating conditions. At the same time, the flux-balance loop proposed in this paper, there is no more literature to discuss. The system identification tool of MATLAB [21] is a useful tool to obtain the small-signal model transfer function without using any complex mathematical model derivation. Figure 12 shows the processing flow windows of the system identification of MATLAB. The transfer function of the system can be obtained from the simulated or measured system data such as time response or

Small-Signal Models Built Using System Identification
Unlike the pulse-width-modulation (PWM) converter, the LLC resonant converter is a complex nonlinear system. Therefore, it is difficult to obtain its small-signal model through mathematical derivation. Previously, researchers had developed the mathematical methods for deriving the small-signal dynamic model of the LLC resonant converter [16][17][18][19]. However, these works focused only on the matching with circuit ac sweep simulation occurs only under specific operating conditions. At the same time, the flux-balance loop proposed in this paper, there is no more literature to discuss. The system identification tool of MATLAB [21] is a useful tool to obtain the small-signal model transfer function without using any complex mathematical model derivation. Figure 12 shows the processing flow windows of the system identification of MATLAB. The transfer function of the system can be obtained from the simulated or measured system data such as time response or frequency response. Therefore, the system identification tool of MATLAB [21] is used to obtain the small-signal model for controller design, in this paper. frequency response. Therefore, the system identification tool of MATLAB [21] is used to obtain the small-signal model for controller design, in this paper.  Figure 13 shows the control block diagram of the flux-balance loop, for which the loop gain can be expressed as

Flux-Balance Loop Controller Design
where Gbc(s) represents the transfer function of the controlled plant, which is the duty ratio of MOSFET Q1 (d1-tilde) to the magnetizing DC current (iLm,DC-tilde), GPWM,d(s) represents the transfer function of the duty ratio control signal (vcon,d-tilde) to the duty ratio of MOSFET Q1, and Gcomp,b(s) indicates the controller of the flux-balance loop.
Using the system identification tool of MATLAB, the uncompensated loop gain from the duty ratio control signal to the magnetizing DC current under full load operation condition can be expressed as follows. The parameters of the LLC resonant converter are shown in Table 1, which will be shown in Section 5.   Figure 13 shows the control block diagram of the flux-balance loop, for which the loop gain can be expressed as

Flux-Balance Loop Controller Design
where G bc (s) represents the transfer function of the controlled plant, which is the duty ratio of MOSFET where Kpb is the DC gain, which is determined according to the crossover frequency sets as fc,b = 10 kHz, and zb is the zero, which is set at 17.5 kHz for pole/zero cancellation. The phase margin (PM) is set as 72° to ensure stability. The bode plot of the compensated flux-balance loop gain, after the addition of the controller, is shown in Figure 14b. (a) Figure 13. Control block diagram of the flux-balance loop.
Using the system identification tool of MATLAB, the uncompensated loop gain from the duty ratio control signal to the magnetizing DC current under full load operation condition can be expressed as follows. The parameters of the LLC resonant converter are shown in Table 1, which will be shown in Section 5.
The characteristic equation in (17) has two real poles at 110 krad/s (17.5 kHz) and 377 krad/s (60 kHz), respectively. Figure 14a shows the bode plots of the uncompensated flux-balance loop gains obtained from the mathematical model in (17) (blue dashed line) and Simplis circuit simulation (red solid line). Figure 14a reveals that the dominate pole is at 17.5 kHz. The controller of the flux-balance loop G comp,b (s) can, therefore, be chosen as a PI-type controller and can be expressed as follows where K pb is the DC gain, which is determined according to the crossover frequency sets as f c,b = 10 kHz, and z b is the zero, which is set at 17.5 kHz for pole/zero cancellation. The phase margin (PM) is set as 72 • to ensure stability. The bode plot of the compensated flux-balance loop gain, after the addition of the controller, is shown in Figure 14b. where Kpb is the DC gain, which is determined according to the crossover frequency sets as fc,b = 10 kHz, and zb is the zero, which is set at 17.5 kHz for pole/zero cancellation. The phase margin (PM) is set as 72° to ensure stability. The bode plot of the compensated flux-balance loop gain, after the addition of the controller, is shown in Figure 14b.  Figure 15 shows the control block diagram of the output-voltage loop, the loop gain of which can be expressed as follows   Figure 15 shows the control block diagram of the output-voltage loop, the loop gain of which can be expressed as follows (19) where G fv (s) represents the transfer function of the controlled plant, which is the switching frequency of MOSFET Q 1 (f -tilde) to the output voltage (v o -tilde), G PWM,d (s) represents the transfer function of the switching frequency control signal (v con,f -tilde) to the switching frequency of MOSFET Q 1 , and G comp,v (s) is the controller of the output-voltage loop. switching frequency control signal (vcon,f-tilde) to the switching frequency of MOSFET Q1, and Gcomp,v(s) is the controller of the output-voltage loop.

Output-Voltage Loop Controller Design
Using the system identification tool of MATLAB, the uncompensated loop gain from the switching frequency control signal to the output voltage under full load operation condition can be expressed as follows. The parameters of the LLC resonant converter are shown in Table 1. . The characteristic equation in (20) has a complex pole pair at 21.42 ± j18.346 krad/s (3.41 ± j2.9 kHz) and a zero at 30.97 krad/s (4.93 kHz). Figure 16a shows the bode plots of the uncompensated output-voltage loop gains obtained from the mathematical model in (20) (blue dashed line) and Simplis circuit simulation (red solid line). Figure 16a reveals that the phase down to −90°, due to the zero, is very close to complex pole pair. Thus, (20) can be simplified as a first-order system. The controller of the output voltage Gcomp,v(s) can also be chosen as a PI-type controller and can be expressed as follows  (21) where Kpv is the DC gain, which is determined according to the crossover frequency sets as fc,v = 6 kHz, zv is the zero, which is set at 18.85 kHz for pole/zero cancellation, and the phase margin at fc,v is 78.33° to ensure stability. The bode plot of the compensated output-voltage loop gain, after the addition of the controller, is shown in Figure 16b.  Table 1.
The characteristic equation in (20) has a complex pole pair at 21.42 ± j18.346 krad/s (3.41 ± j2.9 kHz) and a zero at 30.97 krad/s (4.93 kHz). Figure 16a shows the bode plots of the uncompensated output-voltage loop gains obtained from the mathematical model in (20) (blue dashed line) and Simplis circuit simulation (red solid line). Figure 16a reveals that the phase down to −90 • , due to the zero, is very close to complex pole pair. Thus, (20) can be simplified as a first-order system. The controller of the output voltage G comp,v (s) can also be chosen as a PI-type controller and can be expressed as follows where K pv is the DC gain, which is determined according to the crossover frequency sets as f c,v = 6 kHz, z v is the zero, which is set at 18.85 kHz for pole/zero cancellation, and the phase margin at f c,v is 78.33 • to ensure stability. The bode plot of the compensated output-voltage loop gain, after the addition of the controller, is shown in Figure 16b.  .
The characteristic equation in (20) has a complex pole pair at 21.42 ± j18.346 krad/s (3.41 ± j2.9 kHz) and a zero at 30.97 krad/s (4.93 kHz). Figure 16a shows the bode plots of the uncompensated output-voltage loop gains obtained from the mathematical model in (20) (blue dashed line) and Simplis circuit simulation (red solid line). Figure 16a reveals that the phase down to −90°, due to the zero, is very close to complex pole pair. Thus, (20) can be simplified as a first-order system. The controller of the output voltage Gcomp,v(s) can also be chosen as a PI-type controller and can be expressed as follows s =K s s s 3 + 18.85 10 = 70 (21) where Kpv is the DC gain, which is determined according to the crossover frequency sets as fc,v = 6 kHz, zv is the zero, which is set at 18.85 kHz for pole/zero cancellation, and the phase margin at fc,v is 78.33° to ensure stability. The bode plot of the compensated output-voltage loop gain, after the addition of the controller, is shown in Figure 16b.

Simulation and Experimental Verification
To verify the proposed approach, Simplis software was used to construct the simulation, and an experimental platform was built as shown in Figure 17. In this paper, the center-tapped model constructed in Simplis is similar to Figure 5. Two ideal transformers, where the primary side is connecting in parallel, and the secondary side connecting in series, are used. The magnetizing inductance and leakage inductances are added in the primary side and secondary sides, respectively. The advantage of this method is that all of branches current and nodes voltages can easily be measured for observation and analysis.
The proposed flux-balance control strategy was implemented by using Texas Instrument C2000 Piccolo 28035 digital signal processor. For experimental equipment, Agilent Technologies InfiniiVision DSO-X 3054A oscilloscope (BW = 500 MHz) was used; Keysight Technologies 1147B current probe (BW = 50 MHz) was used for iLr measurement, and Sapphire Instrument LDP-6002 (BW = 25 MHz) differential voltage probes were used for differential voltage measurement (vgs1). Table 1 lists the related parameters of the LLC resonant converter. The leakage inductance at the secondary side, during the negative cycle, covers the matched condition (Llk2,neg = 53 nH) and mismatched condition (Llk2,neg = 167.77 nH). The set switching frequency is less than the resonant frequency, i.e. fs < fr, for an input voltage Vi = 380 V.

Simulation and Experimental Verification
To verify the proposed approach, Simplis software was used to construct the simulation, and an experimental platform was built as shown in Figure 17. In this paper, the center-tapped model constructed in Simplis is similar to Figure 5. Two ideal transformers, where the primary side is connecting in parallel, and the secondary side connecting in series, are used. The magnetizing inductance and leakage inductances are added in the primary side and secondary sides, respectively. The advantage of this method is that all of branches current and nodes voltages can easily be measured for observation and analysis.   Figure 18 shows the simulated and experimental results of the LLC resonant converter at full load in steady-state operation with the matched secondary-side leakage inductances, i.e., Llk2,pos = Llk2,neg = 53 nH. In Figure 18a, the peak-to-peak ripple of the output voltage is approximately 734 mV. The conduction times of the secondary side diodes are 2.96 μs. The resonant frequency is fr = 168.9 kHz, and switching frequency is fs = 134.78 kHz. In Figure 18b, the peak-to-peak ripple of the output voltage is 700 mV and conduction times of the secondary-side diodes are approximately 3.14 μs during the positive and negative cycles. Therefore, the resonant frequency is fr = 159.23 kHz and switching frequency is fs = 130.11 kHz. The simulated and experimental results show that the magnetizing current is almost balanced between horizontal axis, i.e., ILm,DC = 0 A, but some parasitic effects in the secondary side of the hardware cause a mismatch between the simulated and experimental results. The proposed flux-balance control strategy was implemented by using Texas Instrument C2000 Piccolo 28035 digital signal processor. For experimental equipment, Agilent Technologies InfiniiVision DSO-X 3054A oscilloscope (BW = 500 MHz) was used; Keysight Technologies 1147B current probe (BW = 50 MHz) was used for i Lr measurement, and Sapphire Instrument LDP-6002 (BW = 25 MHz) differential voltage probes were used for differential voltage measurement (v gs1 ). Table 1 lists the related parameters of the LLC resonant converter. The leakage inductance at the secondary side, during the negative cycle, covers the matched condition (L lk2,neg = 53 nH) and mismatched condition (L lk2,neg = 167.77 nH). The set switching frequency is less than the resonant frequency, i.e., f s < f r , for an input voltage V i = 380 V. = 53 nH. In Figure 18a, the peak-to-peak ripple of the output voltage is approximately 734 mV. The conduction times of the secondary side diodes are 2.96 µs. The resonant frequency is f r = 168.9 kHz, and switching frequency is f s = 134.78 kHz. In Figure 18b, the peak-to-peak ripple of the output voltage is 700 mV and conduction times of the secondary-side diodes are approximately 3.14 µs during the positive and negative cycles. Therefore, the resonant frequency is f r = 159.23 kHz and switching frequency is f s = 130.11 kHz. The simulated and experimental results show that the magnetizing current is almost balanced between horizontal axis, i.e., I Lm,DC = 0 A, but some parasitic effects in the secondary side of the hardware cause a mismatch between the simulated and experimental results.  Figure 18 shows the simulated and experimental results of the LLC resonant converter at full load in steady-state operation with the matched secondary-side leakage inductances, i.e., Llk2,pos = Llk2,neg = 53 nH. In Figure 18a, the peak-to-peak ripple of the output voltage is approximately 734 mV. The conduction times of the secondary side diodes are 2.96 μs. The resonant frequency is fr = 168.9 kHz, and switching frequency is fs = 134.78 kHz. In Figure 18b, the peak-to-peak ripple of the output voltage is 700 mV and conduction times of the secondary-side diodes are approximately 3.14 μs during the positive and negative cycles. Therefore, the resonant frequency is fr = 159.23 kHz and switching frequency is fs = 130.11 kHz. The simulated and experimental results show that the magnetizing current is almost balanced between horizontal axis, i.e., ILm,DC = 0 A, but some parasitic effects in the secondary side of the hardware cause a mismatch between the simulated and experimental results.   Figure 19 shows the simulated and experimental results of the LLC resonant converter at steady-state, when operating at full load with the mismatched secondary side leakage inductances, i.e., L lk2,pos = 53 nH and L lk2,neg = 167.77 nH. In Figure 19a, the peak-to-peak ripples of the output voltage during the positive and negative cycles are 744 mV and 881 mV, respectively. The conduction time of the secondary side diode during the positive cycle is 2.83 µs. Therefore, the resonant frequency during the positive cycle is f r,pos = 176.67 kHz. The conduction time of the secondary side diode during the negative cycle is 3.15 µs. Hence, the resonant frequency during the negative cycle is f r,neg = 158.73 kHz. The switching frequency is f s = 127.98 kHz and magnetizing DC current is I Lm,DC = 436 mA. In Figure 19b, the peak-to-peak ripples of the output voltage during the positive and negative cycles are 750 mV and 1 V, respectively. The conduction time of the secondary side diode during the positive cycle is 3 µs. Hence, the resonant frequency during positive cycle is f r,pos = 166.67 kHz. The conduction time of the secondary side diode during the negative cycle is 3.2 µs; therefore, the resonant frequency during the negative cycle is f r,neg = 156.25 kHz. The switching frequency is f s = 127.01 kHz. The magnetizing DC current can be estimated as I Lm,DC,est = 400 mA using (15), which is approximately the same as the simulated result, although the experimental result does not measure the magnetizing DC current directly. Figure 20 shows the simulated and experimental results of the LLC resonant converter at full load in steady-state with the flux-balance loop control, for the same mismatched condition as that in Figure 19. In Figure 20a, the peak-to-peak ripples of the output voltage during the positive and negative cycles are 780 mV and 774 mV, respectively. The conduction time of the secondary side diode during the positive cycle is 2.97 µs; therefore, the resonant frequency during positive cycle is f r,pos = 168.35 kHz. The conduction time of the secondary side diode during the negative cycle is 3.04 µs; hence, the resonant frequency during the negative cycle is f r,neg = 164.47 kHz. The switching frequency is f s = 125.37 kHz and magnetizing DC current is I Lm,DC = 19 mA. In Figure 20b, the peak-to-peak ripples of the output voltage during the positive and negative cycles are 750 mV and 740 mV, respectively. The conduction time of the secondary side diode during the positive cycle is 3.15 µs; hence, the resonant frequency during positive cycle is f r,pos = 158.73 kHz. The conduction time of the secondary side diode during the negative cycle is 3.2 µs; therefore, the resonant frequency during negative cycle is f r,neg = 156.25 kHz.

Steady-State Operation
The switching frequency is f s = 126.21 kHz. The magnetizing DC current can be estimated to be I Lm,DC,est = 20 mA, using (15). The magnetizing DC current estimated from the experimental result is close to the value obtained from the simulations, which confirms the effectiveness of the approach proposed in this paper. the positive and negative cycles are 744 mV and 881 mV, respectively. The conduction time of the secondary side diode during the positive cycle is 2.83 μs. Therefore, the resonant frequency during the positive cycle is fr,pos = 176.67 kHz. The conduction time of the secondary side diode during the negative cycle is 3.15 μs. Hence, the resonant frequency during the negative cycle is fr,neg = 158.73 kHz. The switching frequency is fs = 127.98 kHz and magnetizing DC current is ILm,DC = 436 mA. In Figure  19b, the peak-to-peak ripples of the output voltage during the positive and negative cycles are 750 mV and 1 V, respectively. The conduction time of the secondary side diode during the positive cycle is 3 μs. Hence, the resonant frequency during positive cycle is fr,pos = 166.67 kHz. The conduction time of the secondary side diode during the negative cycle is 3.2 μs; therefore, the resonant frequency during the negative cycle is fr,neg = 156.25 kHz. The switching frequency is fs = 127.01 kHz. The magnetizing DC current can be estimated as ILm,DC,est = 400 mA using (15), which is approximately the same as the simulated result, although the experimental result does not measure the magnetizing DC current directly.  Figure 20 shows the simulated and experimental results of the LLC resonant converter at full load in steady-state with the flux-balance loop control, for the same mismatched condition as that in Figure 19. In Figure 20a, the peak-to-peak ripples of the output voltage during the positive and negative cycles are 780 mV and 774 mV, respectively. The conduction time of the secondary side diode during the positive cycle is 2.97 μs; therefore, the resonant frequency during positive cycle is fr,pos = 168.35 kHz. The conduction time of the secondary side diode during the negative cycle is 3.04 μs; hence, the resonant frequency during the negative cycle is fr,neg = 164.47 kHz. The switching frequency is fs = 125.37 kHz and magnetizing DC current is ILm,DC = 19 mA. In Figure 20b, the peak-topeak ripples of the output voltage during the positive and negative cycles are 750 mV and 740 mV, respectively. The conduction time of the secondary side diode during the positive cycle is 3.15 μs; hence, the resonant frequency during positive cycle is fr,pos = 158.73 kHz. The conduction time of the secondary side diode during the negative cycle is 3.2 μs; therefore, the resonant frequency during negative cycle is fr,neg = 156.25 kHz. The switching frequency is fs = 126.21 kHz. The magnetizing DC current can be estimated to be ILm,DC,est = 20 mA, using (15). The magnetizing DC current estimated from the experimental result is close to the value obtained from the simulations, which confirms the effectiveness of the approach proposed in this paper.  Figure 21 shows the simulated and experimental results of the transient response of the LLC resonant converter, which compensates for the mismatched secondary side leakage inductances using the flux-balance loop, for load changes from 50% to 70%. The transient time is approximately 200 μs, as shown in the simulated and experimental results. Figure 21 reveals that the voltage loop and the flux-balance loop operate simultaneously, without affecting each other in the transient state. Figure 22 shows the simulated and experimental results of the transient response of the LLC resonant converter, which compensates for the mismatched secondary side leakage inductances with the fluxbalance loop, for load changes from 70% to 50%. The simulated and experimental results show that the transient time is 200 μs. Figure 22 shows that the voltage loop and flux-balance loop do not affect each other, even during the load step down. Figure 23 shows the experimental results of the disabled and enabled flux-balance loop at 70% load, considering the mismatched secondary side leakage inductances. When the flux-balance loop is disabled, the maximum peak-to-peak ripple of the output voltage is 818.75 mV. Once the flux-balance loop is enabled, the maximum peak-to-peak ripple of the output voltage reduces to 731.25 mV.   Figure 22 shows the simulated and experimental results of the transient response of the LLC resonant converter, which compensates for the mismatched secondary side leakage inductances with the flux-balance loop, for load changes from 70% to 50%. The simulated and experimental results show that the transient time is 200 µs. Figure 22 shows that the voltage loop and flux-balance loop do not affect each other, even during the load step down. Figure 23 shows the experimental results of the disabled and enabled flux-balance loop at 70% load, considering the mismatched secondary side leakage inductances. When the flux-balance loop is disabled, the maximum peak-to-peak ripple of the output voltage is 818.75 mV. Once the flux-balance loop is enabled, the maximum peak-to-peak ripple of the output voltage reduces to 731.25 mV. Figure 22 shows the simulated and experimental results of the transient response of the LLC resonant converter, which compensates for the mismatched secondary side leakage inductances with the fluxbalance loop, for load changes from 70% to 50%. The simulated and experimental results show that the transient time is 200 μs. Figure 22 shows that the voltage loop and flux-balance loop do not affect each other, even during the load step down. Figure 23 shows the experimental results of the disabled and enabled flux-balance loop at 70% load, considering the mismatched secondary side leakage inductances. When the flux-balance loop is disabled, the maximum peak-to-peak ripple of the output voltage is 818.75 mV. Once the flux-balance loop is enabled, the maximum peak-to-peak ripple of the output voltage reduces to 731.25 mV.

Conclusions
In this paper, a flux-balance loop control strategy was proposed to solve the flux walking issues of the center-tapped transformer in the LLC resonant converter, which were caused by mismatched leakage inductances at the secondary side. The magnetizing DC current effect and voltage gain parameter variation caused by the mismatched conditions at the secondary side were analyzed. Based on these analyses, the flux-balance control loop combining with the original output-voltage control loop, was proposed to resolve the issues. Besides, a magnetizing DC current sampling strategy and estimation scheme was also proposed to overcome the difficulties in measuring the magnetizing DC current. The simulation and experimental results confirmed the effectiveness of the proposed control strategy.
Author Contributions: Yuan-Chih Lin substantially contributed to literature search, control strategy design, examination and interpretation of the results, development of the overall system, and review and proofreading of the manuscript. Ding-Tang Chen substantially contributed to implement the control strategy, production and analysis of the results, and preparation and revision of the manuscript. Ching-Jan Chen substantially contributed to the review and proofreading of the manuscript.

Conclusions
In this paper, a flux-balance loop control strategy was proposed to solve the flux walking issues of the center-tapped transformer in the LLC resonant converter, which were caused by mismatched leakage inductances at the secondary side. The magnetizing DC current effect and voltage gain parameter variation caused by the mismatched conditions at the secondary side were analyzed. Based on these analyses, the flux-balance control loop combining with the original output-voltage control loop, was proposed to resolve the issues. Besides, a magnetizing DC current sampling strategy and estimation scheme was also proposed to overcome the difficulties in measuring the magnetizing DC current. The simulation and experimental results confirmed the effectiveness of the proposed control strategy.