A Control Scheme without Sensors at the PV Source for Cost and Size Reduction in Two-Stage Grid Connected Inverters

: In order to reduce the cost of PV facilities, the market requires low cost and highly reliable PV inverters, which must comply with several regulations. Some research has focused on decreasing the distortion of the current injected into the grid, reducing the size of the DC-link capacitors and removing sensors, while keeping a good performance of the maximum power point tracking (MPPT) algorithms. Although those objectives are di ﬀ erent, all of them are linked to the inverter DC-link voltage control loop. Both the reduction of the DC-link capacitance and the use of sensorless MPPT algorithms require a voltage control loop faster than that of conventional implementations in order to perform properly, but the distortion of the current injected into the grid might rise as a result. This research studies a complete solution for two-stage grid-connected PV inverters, based on the features of second-order generalized integrators. The experimental tests show that the proposed implementation has a performance similar to that of the conventional control of two-stage PV inverters but at a much lower cost.


Introduction
In order to reduce the installation and maintenance costs, the photovoltaic (PV) market requires low cost and reliable systems. Moreover, grid-connected PV inverters must comply with several electromagnetic compatibility (EMC) regulations, some of which limit the distortion of the current injected into the grid (THDi), like IEC EN61000 and IEEE519 [1][2][3][4]. Maximum power point tracking (MPPT) algorithms are implemented to optimize the performance of PV systems [5][6][7][8][9]. Conventional MPPT algorithms use current and voltage sensors to calculate the power extracted from the PV source. Several investigations have focused on reducing the number of sensors in PV inverters when implementing MPPT algorithms [10][11][12][13], which has a positive impact on cost reduction.
One possible solution to achieve both a good maximum point tracking (MPPT) performance and a reduced THDi is the use of two-stage grid-connected PV inverters, based on a DC-DC converter connected to the PV source, followed by a grid-connected inverter [14][15][16]. This paper focused on this kind of topologies.
There is a trend to reduce the required capacitance at the DC-link between the DC-DC converter and the inverter stage, which allows replacing electrolytic capacitors by film capacitors, which are more durable [17][18][19][20][21][22]. Two major effects of the DC-link capacitance reduction are the increase of the voltage ripple at the capacitors and higher transient variations of that voltage under dynamic operation point changes of the inverter. These variations must be bound for the proper operation of the inverter.
In this research, the implementation of control structures based on second-order generalized integrators (SOGI) [23][24][25][26][27] is proposed to support the DC-link capacitance reduction of two-stage The inverter has a reduced size DC-link. Voltage and current sensors for the measurement of the PV panel voltage, VPV, and current, IPV, are available, in order to compare conventional MPPT algorithms, which make use of those sensors, with sensorless MPPT algorithms under the same conditions.
Costs saving associated with a smaller bulk capacitor and to the absence of MPPT sensors depends on several characteristics, but the estimation done for the implemented prototype is detailed in Table A1 of Appendix A.

Grid-tied VSI
The voltage source inverter (VSI) is formed by the DC-link capacitance (CDC), a full bridge of IGBTs and an LCL grid filter. The full-bridge is commutated by means of unipolar sinusoidal pulse width modulation (SPWM). The grid filter was designed following the guidelines of Reference [28]. The values of the inverter are shown in Table 1.
The current ICDC has high-frequency current components (IDC_SW) due to the switching of the transistors and a low-frequency current component (IDC_AC). The frequency of IDC_AC is twice the grid frequency and causes a voltage ripple at the DC-link (VDC_R). In Reference [18] it was shown that the minimum value of CDC is determined by the maximum and minimum permissible voltage at the DClink caused by VDC_R. However, this criterion does not consider the dynamics of the DC-link [19] and transient voltage variations, that are due to changes in the operation point. The proposed value of the capacitance, CDC, to study the effects of a reduced DC-link is designed to limit the peak to peak value The inverter has a reduced size DC-link. Voltage and current sensors for the measurement of the PV panel voltage, V PV , and current, I PV , are available, in order to compare conventional MPPT algorithms, which make use of those sensors, with sensorless MPPT algorithms under the same conditions.
Costs saving associated with a smaller bulk capacitor and to the absence of MPPT sensors depends on several characteristics, but the estimation done for the implemented prototype is detailed in Table A1 of Appendix A.

Grid-tied VSI
The voltage source inverter (VSI) is formed by the DC-link capacitance (C DC ), a full bridge of IGBTs and an LCL grid filter. The full-bridge is commutated by means of unipolar sinusoidal pulse width modulation (SPWM). The grid filter was designed following the guidelines of Reference [28]. The values of the inverter are shown in Table 1.
The current I CDC has high-frequency current components (I DC_SW ) due to the switching of the transistors and a low-frequency current component (I DC_AC ). The frequency of I DC_AC is twice the grid frequency and causes a voltage ripple at the DC-link (V DC_R ). In Reference [18] it was shown that the minimum value of C DC is determined by the maximum and minimum permissible voltage at the DC-link caused by V DC_R . However, this criterion does not consider the dynamics of the DC-link [19] and transient voltage variations, that are due to changes in the operation point. The proposed value of the capacitance, C DC , to study the effects of a reduced DC-link is designed to limit the peak to peak value of V DC_R to 10% of V DC at nominal power (P G = 230 W), thus the value of the capacitance C DC is calculated following Equation (1).

Step Up DC-DC Converter
The DC-DC stage, shown in Figure 1, is a Flyback converter designed for boosting the voltage from the PV panel (V PV ) up to the voltage of the DC-link (V DC ) and providing high-frequency galvanic isolation between the PV panel and the grid. The converter is designed to work in discontinuous conduction mode (DCM) because the value of the transformer magnetizing inductance (L M ) and the physical size of the transformer become smaller [15]. The MPPT algorithm establishes the operation point of this stage since the PV panel voltage is at the input of the DC-DC converter. It is worth pointing out that in the two-stage PV inverter structure the output voltage of the DC-DC converter is regulated by the inverter stage, whereas the panel voltage is controlled by the DC-DC converter following the reference value provided by the MPPT algorithm.
The current I SW , through the switch of the DC-DC converter, is composed by Equation (2) an average value equal to the PV panel current, I PV , and a high-frequency component, I CIN , provided by a low voltage input capacitance, C IN , following Equation (2). (2) The size of C IN depends on the high-frequency current components at the input of the DC-DC converter. Besides, the value of the output capacitance, C DC , has an influence on the MPPT performance, since V PV is susceptible to the low-frequency voltage ripple at the DC-link voltage, V DC_R . It is worth pointing out that the implementation of a peak current control (PCC) is highly desirable for protecting the power switches from transient overcurrents. The values of the DC-DC converter are detailed in Table 2.

Control
The control of the two-stage inverter has been implemented digitally in a Texas Instruments TMS320F28335 [29] microcontroller with digital signal processor (DSP) extensions at a sampling frequency (F S ) of 40 kHz. The controllers have been calculated in the continuous domain, having taken into account the digital delays, and then discretized using the bilinear "Tustin" transform. The delay between the sampling and the update of the reference inside the DSP has been done by using a second-order Padé approximation.
It is worth pointing out that the dynamic models used in this control study result from perturbing the averaged variables of the DC-DC converter or of the inverter stage around an operation point, as expressed by Equation (3). In Equation (3), X andx denote the operation point value and the small-signal term of the averaged variable, x, respectively. The averaging is done in every cycle of the switching frequency.

Control Scheme of the VSI Stage
The complete control structure of the VSI is shown in Figure 2.

Control
The control of the two-stage inverter has been implemented digitally in a Texas Instruments TMS320F28335 [29] microcontroller with digital signal processor (DSP) extensions at a sampling frequency (FS) of 40 kHz. The controllers have been calculated in the continuous domain, having taken into account the digital delays, and then discretized using the bilinear "Tustin" transform. The delay between the sampling and the update of the reference inside the DSP has been done by using a second-order Padé approximation.
It is worth pointing out that the dynamic models used in this control study result from perturbing the averaged variables of the DC-DC converter or of the inverter stage around an operation point, as expressed by Equation (3). In Equation (3), X and x denote the operation point value and the small-signal term of the averaged variable, x, respectively. The averaging is done in every cycle of the switching frequency.

Control Scheme of the VSI Stage
The complete control structure of the VSI is shown in Figure 2.

Synchronization with the Grid
The synchronization with the grid voltage (VG) has been implemented by means of an SOGI based Frequency Locked Loop (FLL-SOGI) [27], which provides the calculation of the grid frequency in rad/s, ωG_FLL, a sinusoidal signal in phase with the grid, v', and a sinusoidal signal in quadrature, qv'. The amplitude of the fundamental harmonic of VG, v'pk, is calculated following Equation (4), and a normalized sinusoidal signal in phase with the grid, v'n, is obtained in Equation (5).

Synchronization with the Grid
The synchronization with the grid voltage (V G ) has been implemented by means of an SOGI based Frequency Locked Loop (FLL-SOGI) [27], which provides the calculation of the grid frequency in rad/s, ω G_FLL , a sinusoidal signal in phase with the grid, v', and a sinusoidal signal in quadrature, qv'. The amplitude of the fundamental harmonic of V G , v' pk , is calculated following Equation (4), and a normalized sinusoidal signal in phase with the grid, v' n , is obtained in Equation (5).
3.1.2. Control of the Current Injected into the Grid The control of the current injected into the grid, I G , is indirectly performed by controlling the current through the inductance Lf of the filter, I Lf , because the control of I Lf is less sensitive to grid impedance variations [30].
A proportional + resonant controller + a harmonics compensator (P + R + HC) current regulator, G ILf (s), expressed by Equation (6), has been designed following Reference [26] and References [31][32][33][34] for tracking the sinusoidal reference of I Lf , I Lf Ref . Both the resonant and the harmonics compensator have been implemented by means of second-order generalized integrators (SOGI).
Taking into account that the value of ω G_FLL used in Equation (6), provided by the FLL-SOGI, it can be concluded that G ILf is adaptive in frequency, allowing high performance even under large variations of the grid frequency. The index 'i' in Equation (6) represents the corresponding harmonic. The gains of G ILf are shown in Table 3. A reduced DC-link capacitance leads to the fast dynamics of the V DC control loop at the expense of an increase of the THDi of I G [16,17]. In Reference [16] a notch filter in the DC-link voltage control loop was implemented to reduce the low-frequency harmonics of I G . In the current study, the notch filter is implemented by means of SOGIs, achieving adaptation to grid frequency variations. This implementation allows an increase of the crossover frequency of the V DC control loop without increasing the distortion of I G , even with a high low voltage ripple at the DC-link and under large grid frequency variations. The control scheme of V DC is shown in Figure 3.  In Figure 3, two small-signal transfer functions play an important role. The first one is the transfer function ı̂ ı̂ ⁄ (s) in Figure 3a, which is obtained by closing the control loop of ILf. This transfer function can be approximated by (7) in Figure 3b, where ωCi is the crossover frequency of the VSI current loop.
In the case of a three-phase grid connected inverter, the derivation of the transfer function from the AC side active current to the DC-link voltage and the adjustment of the voltage loop PI regulator can be found in Reference [35], pages 210-219. In the case of the single-phase inverter under study, an analogous Equation (8) can be derived, based on the power balance and the power perturbation at the DC and AC sides. The transfer function from the peak value of the inverter output current at the AC side to the DC-link voltage can be expressed by Equation (8) after some derivation. Note that Equation (8) consists of a first-order transfer function with an (unstable) right half plane (RHP) pole, ωP_RHP, whose value depends on the operation point values VDC and IDC.
The loop gain TVDC(s) of Figure 3 is tuned by means of the PI regulator GVDC(s). Equation (9) provides the crossover frequency, Fc_VDC, one decade higher than ωP_RHP/(2 π). Note that an open loop unstable system can be stabilized by feedback only if the loop gain has a gain crossover frequency much higher than the maximum possible value of the unstable open loop pole, Fc_VDC >> ωP_RHP/(2 π) in this case. Besides, the value of Fc_VDC must be much lower than twice the grid frequency (FG), to reduce the effect of the low-frequency voltage ripple at the DC-link (fripple = 2 Fc_VDC) in the current reference signal iLf_ref, which could produce an unacceptable distortion of the grid injected current. In Figure 3, two small-signal transfer functions play an important role. The first one is the transfer functionî Lf /î LfRef (s) in Figure 3a, which is obtained by closing the control loop of I Lf . This transfer function can be approximated by (7) in Figure 3b, where ω Ci is the crossover frequency of the VSI current loop.î In the case of a three-phase grid connected inverter, the derivation of the transfer function from the AC side active current to the DC-link voltage and the adjustment of the voltage loop PI regulator can be found in Reference [35], pages 210-219. In the case of the single-phase inverter under study, an analogous Equation (8) can be derived, based on the power balance and the power perturbation at the DC and AC sides. The transfer function from the peak value of the inverter output current at the AC side to the DC-link voltage can be expressed by Equation (8) after some derivation. Note that Equation (8) consists of a first-order transfer function with an (unstable) right half plane (RHP) pole, ω P_RHP , whose value depends on the operation point values V DC and I DC .
The loop gain T VDC (s) of Figure 3 is tuned by means of the PI regulator G VDC (s). Equation (9) provides the crossover frequency, Fc_ VDC , one decade higher than ω P_RHP /(2 π). Note that an open loop unstable system can be stabilized by feedback only if the loop gain has a gain crossover frequency much higher than the maximum possible value of the unstable open loop pole, Fc_ VDC >> ω P_RHP /(2 π) in this case. Besides, the value of Fc_ VDC must be much lower than twice the grid frequency (F G ), to reduce the effect of the low-frequency voltage ripple at the DC-link (f ripple = 2 Fc_ VDC ) in the current reference signal i Lf_ref , which could produce an unacceptable distortion of the grid injected current.
It can be observed from Figure 3 that a notch filter, F NS (s), is placed in series with the PI controller Gv DC (s). The expression of the notch filter transfer function is given by Equation (10). The center frequency of F NS (s) is twice the grid frequency (ω NS = 2 ω G_FLL ) in order to filter the ripple at f ripple coming from the sensed DC-link voltage. The tuning of the notch filter is provided by the FLL-SOGI previously described. The constant K NS is used to adjust the bandwidth of the filter, BW NS , as shown in Equation (11). The notch filter allows getting a high enough crossover frequency of the voltage loop with no distortion of the grid injected current. Note that a fast enough DC-link voltage loop is crucial to keep the DC-link voltage within safe values in reduced size DC-links with low capacitance.
The Bode plots of T VDC (s) depicted in Figure 4a are those obtained when the notch filter, F NS (s), placed in series with Gv DC (s) isn´t used. The PI regulator G VDC (s) (9) has been tuned in order to achieve a crossover frequency F C_VDC = 53 Hz, with a phase margin higher than 82 • (PM > 82 • ) and a gain margin higher than 70 dB (GM > 70 dB). The system is stable but the attenuation at 100 Hz is just 5.5 dB. Therefore, the output of the voltage regulator has a remarkable low-frequency voltage ripple due to V DC_R , thus producing a high distortion of the grid current. Gv (s) = −0.03902 · s + 0.6283 s (9) It can be observed from Figure 3 that a notch filter, FNS(s), is placed in series with the PI controller GvDC(s). The expression of the notch filter transfer function is given by Equation (10). The center frequency of FNS(s) is twice the grid frequency (ωNS = 2 ωG_FLL) in order to filter the ripple at fripple coming from the sensed DC-link voltage. The tuning of the notch filter is provided by the FLL-SOGI previously described. The constant KNS is used to adjust the bandwidth of the filter, BWNS, as shown in Equation (11). The notch filter allows getting a high enough crossover frequency of the voltage loop with no distortion of the grid injected current. Note that a fast enough DC-link voltage loop is crucial to keep the DC-link voltage within safe values in reduced size DC-links with low capacitance.
The Bode plots of TVDC(s) depicted in Figure 4a are those obtained when the notch filter, FNS(s), placed in series with GvDC(s) isn´t used. The PI regulator GVDC(s) (9) has been tuned in order to achieve a crossover frequency FC_VDC = 53 Hz, with a phase margin higher than 82° (PM > 82°) and a gain margin higher than 70 dB (GM > 70 dB). The system is stable but the attenuation at 100 Hz is just 5.5 dB. Therefore, the output of the voltage regulator has a remarkable low-frequency voltage ripple due to VDC_R, thus producing a high distortion of the grid current. Figure 4b shows the Bode plots of TVDC(s) when the notch filter is used in series with GVDC(s). In that case the value of FC_VDC has slightly decreased (FC_VDC = 46 Hz), getting high stability margins: PM > 52° and GM > 70 dB. The system is also stable, but the attenuation at 100 Hz is higher than 100 dB.

Control Scheme of the DC-DC Stage
The control structure of the DC-DC stage is depicted in Figure 5. It is composed by an outer digital voltage loop, regulating VPV, in cascade with an analog peak current control (PCC) circuit, which sets the peak value of the current, ISW, through the Flyback converter power transistor.  Figure 4b shows the Bode plots of T VDC (s) when the notch filter is used in series with G VDC (s). In that case the value of F C_VDC has slightly decreased (F C_VDC = 46 Hz), getting high stability margins: PM > 52 • and GM > 70 dB. The system is also stable, but the attenuation at 100 Hz is higher than 100 dB.

Control Scheme of the DC-DC Stage
The control structure of the DC-DC stage is depicted in Figure 5. It is composed by an outer digital voltage loop, regulating V PV , in cascade with an analog peak current control (PCC) circuit, which sets the peak value of the current, I SW , through the Flyback converter power transistor.

Peak Current Control of DC-DC Stage
The PCC control scheme shown in Figure 5 and has been designed following Reference [15]. This control structure is based on the cycle-by-cycle measurement of the current through the transistor, ISW, of the DC-DC converter. The peak value of ISW is limited by the control signal VC. An external stabilization ramp signal, VSe, is added to the sensed current signal, VSn. This method also provides protection for both the HF transformer and the power transistors against an eventual overcurrent.
The modulation index of the PCC, mc = 1 + Se/Sn (Equation (13)), is tuned by means of the slope Se of the external ramp VSe. The value Se = 110 V/ms accomplishes a dynamic behaviour of v v ⁄ (s) close to that of a first-order system, as it can be observed from Figure 6a. The high VDC_R ripple value produced by the low size of CDC can change the operation point along the I-V curve of the PV source, degrading the MPPT performance. Therefore, a low susceptibility of VPV to the ripple VDC_R is required. The open loop susceptibility of VPV to variations of VDC (Equation (14)) at 100 Hz is lower than −41.5dB as shown in Figure 6b, therefore VDC_R, that is 10% of VDC (40 Vpp), causes a VPV voltage ripple of 340 mVpp. It can be concluded that the 100 Hz ripple at VDC has a low influence on the PV voltage. Therefore, the sensing of VPV could be avoided and still a good MPPT would be obtained.

Peak Current Control of DC-DC Stage
The PCC control scheme shown in Figure 5 and has been designed following Reference [15]. This control structure is based on the cycle-by-cycle measurement of the current through the transistor, I SW , of the DC-DC converter. The peak value of I SW is limited by the control signal V C . An external stabilization ramp signal, V Se , is added to the sensed current signal, V Sn . This method also provides protection for both the HF transformer and the power transistors against an eventual overcurrent.
The modulation index of the PCC, mc = 1 + Se/Sn (Equation (13)), is tuned by means of the slope Se of the external ramp V Se . The value Se = 110 V/ms accomplishes a dynamic behaviour ofv V PV /v C (s) close to that of a first-order system, as it can be observed from Figure 6a. The high V DC_R ripple value produced by the low size of C DC can change the operation point along the I-V curve of the PV source, degrading the MPPT performance. Therefore, a low susceptibility of V PV to the ripple V DC_R is required. The open loop susceptibility of V PV to variations of V DC (Equation (14)) at 100 Hz is lower than −41.5dB as shown in Figure 6b, therefore V DC_R , that is 10% of V DC (40 Vpp), causes a V PV voltage ripple of 340 mVpp. It can be concluded that the 100 Hz ripple at V DC has a low influence on the PV voltage. Therefore, the sensing of V PV could be avoided and still a good MPPT would be obtained.

PV Panel Voltage (V PV ) Control Loop in the Conventional MPPT
The reference of V PV (V PVRef ) is updated at the sampling frequency of the MPPT, F MPPT . The PV panel voltage control loop is implemented digitally and its control scheme is depicted in Figure 7. The sampling frequency of the control loop (Fs) is 40 kHz. This control loop is adjusted by means the PI regulator G VPV (s), whose values are shown by Equation (15). The crossover frequency, Fc VPV , of the loop gain T VPV (s) must be much higher than F MPPT so that V PV can track V PVref . The transfer function v V PV /v C (s) is the closed loop of the PCC andv V PV /v C (s) is the open loop susceptibility of V PV to the variations of V DC .
As it can be observed from the Bode plots of the loop T VPV (s) in Figure 8a, the crossover frequency Fc VPV achieved by G VPV (s) is higher than 100 Hz. Therefore, an MPPT algorithm running at F MPPT = 10 Hz is suitable Figure 8b shows that the presence of this control loop reduces the susceptibilitŷ v V PV /v DC (s) (16) at 100 Hz down to −55 dB, therefore the voltage ripple in V PV caused by V DC_R is 71 mVpp. Note that the use of a control loop of V PV reduces the sensitivity of V PV to the 100 Hz ripple 8 lower than −41.5dB as shown in Figure 6b, therefore VDC_R, that is 10% of VDC (40 Vpp), causes a VPV voltage ripple of 340 mVpp. It can be concluded that the 100 Hz ripple at VDC has a low influence on the PV voltage. Therefore, the sensing of VPV could be avoided and still a good MPPT would be obtained.

PV Panel Voltage (VPV) Control Loop in the Conventional MPPT
The reference of VPV (VPVRef) is updated at the sampling frequency of the MPPT, FMPPT. The PV panel voltage control loop is implemented digitally and its control scheme is depicted in Figure 7. The sampling frequency of the control loop (Fs) is 40 kHz. This control loop is adjusted by means the PI regulator GVPV(s), whose values are shown by Equation (15). The crossover frequency, FcVPV, of the loop gain TVPV(s) must be much higher than FMPPT so that VPV can track VPVref.

MPPT Implementation without V PV and I PV Sensors
The conventional implementations of MMPT algorithms use current and voltage sensors to measure the voltage (V PV ) and the current (I PV ) of the PV source as it is shown in Figure 9. The use of voltage and current sensors increases the cost of the power converter. Sensorless MPPT algorithms have been developed [10][11][12][13] in order to reduce the number of sensors, yielding a cost reduction. In [11] a sensorless MPPT implementation based on the power balance at the DC-link was presented, which relies on the fact that the power injected into the grid (P G ) can be considered almost equal to the power extracted from the PV panels, P G ≈ P PV . In that implementation, the reference of the current injected into the grid (I G ) is used as an estimation of P G . This reference current depends on the control loop of V DC so that the sampling frequency of the MPPT algorithm (F MPPT ) is limited by the dynamics of that loop. Besides, the reference of I G is sensitive to the variations of the grid voltage and has a low-frequency ripple due to V DC_R . Moreover, the method explained in Reference [11] is based on the assumption that the amplitude of the grid voltage is stable.  A sensorless MPPT implementation shown in Figure 10 is proposed in this work. In this implementation, there is neither V PV nor I PV sensors and it is assumed that the power injected into the grid is almost equal to the power extracted from the PV panels, P G ≈ P PV , as in Reference [11]. A novelty of this research is that it takes de advantages of the PCC of the DC-DC stage and some SOGI based enhancements applied to the control of the VSI stage to improve the performance of the MPPT implementation. A perturb and observe (P and O) algorithm [36] has been programmed in both the conventional ( Figure 10) and the proposed sensorless ( Figure 11) MPPT algorithms to compare the performance of both implementations. Both implementations use the grid frequency as a time-base to execute the MPPT algorithm. This technique increases the rejection of the disturbances caused by V DC_R . In previous applications of a similar technique [12], the MPPT algorithm was executed at twice the grid frequency, but that sampling frequency is too fast for the control loops implemented in the proposed sensorless algorithm. In the present study, the MPPT algorithm was executed once every five cycles of the grid, yielding F MPPT = 10 Hz.  Figure 12a were obtained with a crossover frequency Fc_VDC = 10 Hz, yielding an overvoltage in VDC of 53V from its steady-state value. The response in Figure 12b is obtained with a crossover frequency Fc_VDC = 45 Hz. The response in Figure 12b was close to five times faster and the overvoltage is only 15 V, which In the conventional implementation, the MPPT algorithm provides the reference of V PV (V PV_Ref ) to the V PV control loop. In the proposed sensorless MPPT, both the V PV sensor and the V PV control loop have been removed, so that the MPPT provides the reference Vc to the analog PCC.

Estimation of the Power Injected into the Grid in the Sensorless MPPT
The reference I Lf_Ref_PK is the peak value of the current injected into the grid, being proportional to P G when the amplitude of the grid voltage is a static value. The signal I Lf_Ref_PK may have a remarkable low-frequency voltage ripple due to V DC_R , thus producing a high distortion of the grid injected current along with a disturbance in the estimation of P G . The SOGI based notch filter F NS (s) in series with the regulator G VDC (s) shown in Figure 3 is used to filter out that ripple. The use of the notch filter also enables a high crossover frequency of T VDC (s) without increasing the ripple in I Lf_Ref_PK , which is useful to implement a fast MPPT algorithm. The crossover frequency of T VDC (s) is F C_VDC = 45 Hz so that an MPPT of F MPPT = 10 Hz can be implemented.
The estimation of P G , P G_est , depends on I G and on the grid voltage RMS value (V G ) so that variations of V G perturb the calculations of P G_est . To overcome this issue, the value of the signal v' pk is used to calculate the estimation of P G as it is shown in Equation (17). The signal v' pk is the amplitude of the fundamental of V G and is provided by the FLL-SOGI, not requiring additional computational resources. The signal v' pk has very low sensitivity to the distortion of the grid voltage because it is naturally filtered by the FLL-SOGI.

Implementation of the Perturb and Observe (P&O) Algorithm
The conventional MPPT algorithm uses the measurements of V PV and I PV to set the operation point of the PV source. The algorithm increases or decreases V PV_Ref in perturbation steps of a value ∆V PV_Ref to move the operation point along the I-V curve. In the sensorless implementation shown in Figure 10, instead of the measurements of V PV and I PV , the value of P G_est expressed by Equation (17) was used. In Reference [11] it was proposed to manage the duty cycle of the switches (D F ) of the DC-DC to move the operation point along the I-V curve. In inverters with a reduced DC-link, the high susceptibility of V PV to the ripple V DC_R disturbs the operation point in the PV panel.
In the proposed sensorless MPPT, the value of I PV is indirectly set by means of the reference signal of the PCC loop, Vc. The use of PCC has two functions: reducing the susceptibility of V PV to the ripple V DC_R and protecting the DC-DC converter from overcurrents.
The variable Vc is increased or decreased in small steps of a value ∆Vc. It is worth pointing out that an increase of Vc causes an increase of I PV , moving the PV operation point to the left of the I-V curve, whereas a decrease of Vc moves the PV operation point to the right of the I-V curve. Figure 11 depicts the experimental setup. The laboratory tests have been performed using the two-stage inverter presented in Figure 1. The inverter under test was designed for connecting a single PV panel of 230 W to the single phase grid (230 V RMS @ 50 Hz) and has a DC-link with the capacitance calculated in (1), C DC = 50 µF. The challenge of using such a small value of C DC is to keep a low distortion of the grid current and small transient overvoltages at the DC-link. The control of the two-stage inverter has been implemented digitally in a Texas Instruments TMS320F28335 DSP [30] at a sampling frequency (F S ) of 40 kHz.

Results
The grid was emulated by means of a Cinergia GE&EL 50 grid emulator and electronic load. The voltage waveform was programmed according to the test waveform described in the international standard IEC-61000-4-7 [37], which has a value: THD V = 1.2%. The PV panel has been emulated by means of an AMETEK TerraSAS ETS1000X10D PV simulator.  Figure 12a were obtained with a crossover frequency Fc_ VDC = 10 Hz, yielding an overvoltage in V DC of 53V from its steady-state value. The response in Figure 12b is obtained with a crossover frequency Fc_ VDC = 45 Hz. The response in Figure 12b was close to five times faster and the overvoltage is only 15 V, which represents a reduction of 72%.
13 Figure 11. Experimental setup. Figure 12 shows the transient response of the DC-link voltage (VDC) and the current injected into the grid (IG) when the PV power steps from 150 W up to 200 W. The results shown in Figure 12a were obtained with a crossover frequency Fc_VDC = 10 Hz, yielding an overvoltage in VDC of 53V from its steady-state value. The response in Figure 12b is obtained with a crossover frequency Fc_VDC = 45 Hz. The response in Figure 12b was close to five times faster and the overvoltage is only 15 V, which represents a reduction of 72%.

Influence of the SOGI Notch in the Distortion of the Current Injected to the Grid
The increment of the crossover frequency Fc_VDC involves a higher susceptibility to VDC_R, which increases the harmonic distortion of the current injected into the grid (THDi). Figure 13 depicts the current injected into the grid (IG) using two different regulators for controlling VDC. In Figure 13b, the regulator GVDC(s) of the VDC control loop is the PI shown in Equation (9) with a crossover frequency Fc_VDC = 53 Hz. The waveform of IG in Figure 13b was obtained using the same PI regulator, but in series with the SOGI notch filter FNS(s) shown in Equation (10), centered at 100 Hz. The crossover frequency has been slightly reduced, Fc_VDC = 45 Hz, taking into account the addition of FNS(s).
Both tests have been performed injecting 200 W to the grid. The controller of the current injected into the grid (IG) is formed by the P+R regulator in series with the HC expressed by Equation (6). The

Influence of the SOGI Notch in the Distortion of the Current Injected to the Grid
The increment of the crossover frequency Fc_ VDC involves a higher susceptibility to V DC_R , which increases the harmonic distortion of the current injected into the grid (THDi). Figure 13 depicts the current injected into the grid (I G ) using two different regulators for controlling V DC . In Figure 13b, the regulator G VDC (s) of the V DC control loop is the PI shown in Equation (9) with a crossover frequency Fc_ VDC = 53 Hz. The waveform of I G in Figure 13b was obtained using the same PI regulator, but in series with the SOGI notch filter F NS (s) shown in Equation (10), centered at 100 Hz. The crossover frequency has been slightly reduced, Fc_ VDC = 45 Hz, taking into account the addition of F NS (s).  Both tests have been performed injecting 200 W to the grid. The controller of the current injected into the grid (I G ) is formed by the P+R regulator in series with the HC expressed by Equation (6). The resulting values of the THDi are 21.51% and 0.96%, respectively. This result indicates the effectiveness of the notch filter for reducing the THDi in spite of the small DC-link.
The following tests of the THDi have been performed for values of P G in the range P G = [40, 180] W. The results are shown in Figure 14. The purple trace represents the values of THDi obtained without the SOGI notch F NS (s) and the green trace represents the values obtained with F NS (s). The THDi without notch varies from 21.51% to 22.43%, clearly exceeding the limits of the IEEE519 standard [4] (5%), shown by the red line. The values of the THDi obtained with F NS (s) vary from 0.96% to 3.14%, widely complying with IEEE519 in the whole range of P G values. In all the measurements the distortion of the grid voltage is THDv = 1.2%.

Loop Gain Measurement
The loop gain TVDC(s) has been validated by means of loop gain measurement procedures [38][39][40]. The setup of the test is shown in Figure 15. An NF FRA5097 frequency response analyzer (FRA) is configured to perform an AC sweep from 2 Hz to 20 kHz. The signal generated by the oscillator of the FRA (vOSC_A) is acquired by the DSP, which carries out the control of the inverter through an internal 12-bit ADC. The acquired signal (vOSC) was digitally injected into the control loop as a perturbation. Both, vDC and vDC+vOSC signals were adapted digitally to be loaded into the pulse width modulation (PWM) unit of the DSP. The offset of the signals was removed through digital high pass filters, and then the amplitudes are digitally adjusted to maximize the resolution of the PWM. The

Loop Gain Measurement
The loop gain T VDC (s) has been validated by means of loop gain measurement procedures [38][39][40]. The setup of the test is shown in Figure 15. An NF FRA5097 frequency response analyzer (FRA) is configured to perform an AC sweep from 2 Hz to 20 kHz. The signal generated by the oscillator of the FRA (v OSC_A ) is acquired by the DSP, which carries out the control of the inverter through an internal 12-bit ADC. The acquired signal (v OSC ) was digitally injected into the control loop as a perturbation. Both, v DC and v DC +v OSC signals were adapted digitally to be loaded into the pulse width modulation (PWM) unit of the DSP. The offset of the signals was removed through digital high pass filters, and then the amplitudes are digitally adjusted to maximize the resolution of the PWM. The PWM signals (v DC ) PWM and (v DC + v OSC ) PWM were measured by the FRA. The PWM signals were filtered by the FRA through its internal tracking filter. The loop gain measurement of T VDC (s), shown in Figure 16,was performed at P G = 230 W. The results show the similarity between the experimental and theoretical Bode plots of T VDC (s).

MPPT
The performance of the sensorless "perturb and observe" (P and O) MPPT algorithm presented in this study has been compared to a conventional implementation, which uses sensors to measure V PV and I PV . The experimental tests have carried out to measure the start-up time until the maximum power point (MPP) was reached, and the performance at the MPPT under irradiation transients. All the tests were performed with an MPPT sampling frequency, F MPPT = 10 Hz. The perturbation step value programmed in the conventional implementation was ∆V PV_Ref = 300 mV. In the sensorless MPPT the perturbation step was ∆Vc = 12.5 mV, which corresponds to a 250 mA step in I PV in the operation region close to the MPP. It is worth pointing out that different values are perturbed in both MPPTs (either V PV_Ref or ∆Vc) and that the DC-DC converter operates in discontinuous conduction mode. Both facts prevent finding an equivalent value of the perturbation step in both MPPTs. by the FRA through its internal tracking filter. The loop gain measurement of TVDC(s), shown in Figure  16,was performed at PG = 230 W. The results show the similarity between the experimental and theoretical Bode plots of TVDC(s).

MPPT
The performance of the sensorless "perturb and observe" (P and O) MPPT algorithm presented in this study has been compared to a conventional implementation, which uses sensors to measure

MPPT
The performance of the sensorless "perturb and observe" (P and O) MPPT algorithm presented in this study has been compared to a conventional implementation, which uses sensors to measure  Figure 17 shows the evolution of the operation point at the PV source (V PV , I PV and P PV ) from the start-up until the MPP was reached. The conventional implementation was faster (2.75 s) than the sensorless (12.6 s) due to the differences in the perturbation step, but once the MPP is achieved, both implementations continue at the MPP.  Figure 17 shows the evolution of the operation point at the PV source (VPV, IPV and PPV) from the start-up until the MPP was reached. The conventional implementation was faster (2.75 s) than the sensorless (12.6 s) due to the differences in the perturbation step, but once the MPP is achieved, both implementations continue at the MPP.

MPPT Performance Close to the MPP
A key factor in the MPPT performance is the accuracy of the PV estimation and the dispersion of the operation point from the MPP along the I-V curve. The results shown in Figure 18 were obtained tracking the MPP of the 230 W PV panel at constant irradiation of 1000 W/m 2 during 50 s. The results in Figure 18a correspond to the conventional MPPT algorithm and the results in Figure  18b correspond to the sensorless algorithm. In both implementations, the operation points are very close to the MPP. The power extracted from the PV panel during the tests is shown in Table 4. In order to calculate the MPP tracking performance, the quotient between the average power and the peak power measured in each experiment has been used as a reference, as it is expressed by Equation (18). Although the sensorless algorithm presents a very slight disadvantage (0.06%) in terms of the tracking efficiency, the performance of both methods is almost the same.

MPPT Performance Close to the MPP
A key factor in the MPPT performance is the accuracy of the PV estimation and the dispersion of the operation point from the MPP along the I-V curve. The results shown in Figure 18 were obtained tracking the MPP of the 230 W PV panel at constant irradiation of 1000 W/m 2 during 50 s. The results in Figure 18a correspond to the conventional MPPT algorithm and the results in Figure 18b correspond to the sensorless algorithm. In both implementations, the operation points are very close to the MPP. The power extracted from the PV panel during the tests is shown in Table 4. In order to calculate the MPP tracking performance, the quotient between the average power and the peak power measured in each experiment has been used as a reference, as it is expressed by Equation (18). Although the sensorless algorithm presents a very slight disadvantage (0.06%) in terms of the tracking efficiency, the performance of both methods is almost the same.    The tracking of the MPP under heavy irradiation transients is shown in Figure 19. The tests have been performed for 50 s following the stages shown in Table 5. The black traces are the IV curve of the PV panel at 1000 W/m 2 and 600 W/m 2 . The blue traces represent the evolution in stage 2, during the reduction of the irradiation, and the red trace represents the evolution in stage 4, during the increase of irradiation.

Sensorless MPPT Irradiation Transients
Panel @1000W/m2 Panel @600W/m2 from 600W/m2 to 1000W/m2 from 1000W/m2 to 600W/m2  The power extracted from the PV panel during the tests is shown in Table 6. During stages 1, 3 and 5, both MPPTs tracked the MPP as was expected from the results shown in Table 4. During stage 2, the sensorless MPPT was not as accurate as the conventional one, but during stage 4 the sensorless MPPT exhibited a smaller dispersion of the operation point and, thus, a higher accuracy than the conventional one. It can be stated that the MPPT performance of both MPPTs was highly similar. Although the conventional MPPT had a faster start-up and was slightly more accurate in some tests, the performance of the proposed sensorless MPPT near the MPP was almost equal to the conventional implementation, but at a lower cost.

Conclusions
This paper focused on control techniques which help to reduce the cost of two-stage grid-connected PV inverters. In previous works, sensorless algorithms and techniques to reduce the capacitance of the DC-link have been proposed separately. The present study attempts to integrate both trends in a single implementation. The reduction of the DC-link capacitance requires a faster control loop to keep the DC-link voltage within safe values. However, this practice usually increases the THD of the current injected into the grid. The DC-link can be reduced in a factor of ten compared to standard values of the DC-link capacitance, yet with good values of the THDi, by increasing the speed of the voltage control loop and using a frequency adaptive notch filter tuned at twice the grid frequency.
SOGI structures are an effective way to implement tuned filters both in the inverter voltage loop and in its current loop. It is shown that the crossover frequency of the DC-link voltage control loop can be increased from typical values of 10 Hz to a value around 50 Hz, yet getting a THDi value lower than 1%. The combination of a fast voltage loop with a SOGI notch filter allows the reduction of the DC-link capacitance. An FLL-SOGI is used to get the value of the grid frequency to tune the SOGI controllers in the inverter control loops.
Summing up, this study proposes the implementation of the MPPT with no sensors at the PV source side, which takes advantages of the SOGI based enhancements implemented in the control of the converter. The high dynamics achieved by the inverter controllers yield a performance of the sensorless MPPT very similar to that of conventional MPPT implementations, but at a lower cost. Funding: This work has been co-financed by the Spanish Ministry of Economy and Competitiveness (MINECO) and by the European Regional Development Fund (ERDF) under Grant ENE2015-64087-C2-2-R and by the Spanish Ministry of Science, Innovation and University (MICINN) and the European Regional Development Fund (ERDF) under Grant RTI2018-100732-B-C21. The European Regional Development Fund (ERDF) and the Generalitat Valenciana (GVA) financed the purchase of the Cinergia GE&EL 50 grid emulator and electronic load used during the experimental part of this work under Grant IDIFEDER/2018/036.

Conflicts of Interest:
The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results. Table A1 shows the approximated costs of the prototype built for this study at the present time. It is important to note that a 6% cost saving is estimated.