Gallium-Nitride Semiconductor Technology and Its Practical Design Challenges in Power Electronics Applications: An Overview

: This paper will revise, experimentally investigate, and discuss the main application challenges related to gallium nitride power semiconductors in switch-mode power converters. Gallium Nitride (GaN) devices are inherently gaining space in the market. Due to its high switching speed and operational switching frequency, challenges related to the circuit design procedure, passive component selection, thermal management, and experimental testing are currently faced by power electronics engineers. Therefore, the focus of this paper is on low-voltage ( < 650 V) devices that are used to assemble DC-DC and/or DC-AC converters to, for instance, interconnect PV generation systems in the DC and/or AC grids. The current subjects will be discussed herein: GaN device structure, the advantages and disadvantages of each lateral gallium nitride technology available, design challenges related to electrical layout and thermal management, overvoltages and its implications in the driver signal, and ﬁnally, a comprehensive comparison between GaN and Si technology considering the main parameters to increase the converters efﬁciency.


Introduction
The power electronics field is known for its extensive range of applications, e.g., from power converters, semiconductors, electric machines, and generation/storage systems to analog and digital circuits, ICs, and RF [1].Most of these applications are currently in vogue, e.g., distributed generation with renewable energy sources and its control [2][3][4][5] and storage systems [6,7], since decreasing the CO 2 emissions generated by some of the centralized power plants is now required.Building Applied Photovoltaics (BAPV) and Building Integrated Photovoltaics (BIPV) and their connection to the system are the focus of much research currently.Researchers aim at improving the efficiency of the PV panels in the range of 1% pt; however, an important feature is often forgotten: the interconnection of these PV systems in the grid.Figure 1 illustrate this interconnection in the AC system.As can be seen in Figure 1, power electronics converters are also a key factor to achieve a higher system efficiency, since these devices are responsible for the interface between solar generation (in DC) and DC or AC systems.
Power converters, for most researchers, are a black-box.These devices, among other components, are made by passive components, e.g., capacitors, inductors, and transformers, and power semiconductors (diodes and FETs).High efficiency and power density are the main goal in these applications since the maximum amount of PV generation should be injected into the grid with a minimal size space occupied by these devices [8][9][10] because of the costs of the m 2 in highly-populated areas.For instance, a regular BAPV installation in a building environment is interconnected with the AC system via IGBT-based high-power inverters.This building needs a dedicated room of around 50 m 2 to place the inverters to interconnect a medium-sized (100 kWp) BAPV system.If, instead of high power inverters, the system is interconnected via DC-DC Module Level Converters (DC-DC MLC) or micro-inverters applying low-voltage/low-power semiconductors (GaN or even Si) connected directly at the back of the modules, the 50-m 2 room space is saved and can further be used for other purposes.Notice that, for these type of applications, both technologies (GaN and Si) can still be used.Furthermore, the size of the magnetics, passive components, and heat sinks will directly influence the size of these MLC or micro-inverters.The size of the magnetics and passives, the bulkiest components, together with heat sinks, in a power converter, are directly related to the operational switching frequency of the converter [8].Reported in the literature, for DC-DC MLC, GaN-based converters perform a size reduction of three times compared with the same structure in Si [11].Finally, this approach can also mitigate the partial shading problem when a few PV panels are connected in strings.Wide-Band Gap (WBG) [12,13] semiconductors are known to have faster transitions compared to Silicon (Si) switches, which determines the first project question: Do Wide Band Gap (WBG) devices present better overall performance than Silicon (Si) switches in terms of efficiency and power density in power electronics applications?To answer this question, a comprehensive analysis comparing these devices' characteristics should be done in order to evaluate each technology available on the market.As mentioned above, the power semiconductor operational switching frequency essentially determines the volume of the passive components in a power electronics converter.Currently, most of the applications and converters on the market are made based on Si power semiconductors.Silicon MOSFETs started to be used in power electronics applications in the early 1960s after its invention in 1960 at Bell Labs [14].This component started to gain more attention since it presented a high switching speed (at that time), which enabled its usage in application where BJTs suffer because of its internal characteristics and, eventually, even replacing BJTs in regular applications.From that point on, the field dramatically evolved, since with the dissemination of the power Si-MOSFET, operational frequencies of tens or hundreds of Hertz (Hz) migrated to tens or few hundreds of kiloHertz (kHz), enabling the shrinkage of the passive components and still achieving considerably high efficiencies.
Additionally, the MOSFET implementation opens the door for new DC-DC, DC-AC, AC-DC, and AC-AC topology proposals, since the converters can switch faster with lower overall losses.This breakthrough also pushes other components, e.g., capacitors, wires, cores, and isolation material, to become more reliable and to have better characteristics, whereas an optimization to achieve better performance and power density can be realized for higher switching frequencies [15][16][17][18].
Since then, silicon technology has evolved, and now, the Si material is close to its technological limits.Figure 2, with Baliga's Figure-Of-Merit (BFOM) [19,20], highlights the common materials' theoretical limits.BFOM calculates and compares, based on the materials' mobility (µ r ), permissivity ( r ), voltage breakdown (V B ), and band gap (E G ) (check Equation ( 1)), the on-resistance of each material per surface area.As can be seen in Figure 2, Gallium Nitride (GaN) and Silicon Carbide (SiC) present much better BFOM than the current state-of-the-art silicon material, since higher breakdown voltages can be achieved with lower on-resistances per cm 2 .These materials bring both higher speed (decreasing switching losses) and lower on-resistance for the same surface area (decreasing conduction losses) if compared with Si technology, which enable its usage in the new generation of power converters.Is silicon, after many years of dominating the power electronics semiconductors market, in danger of being massively replaced?The answer to this question is yet unknown, but one statement can be made: silicon technology has a promising competitor, as happened with BJTs in the early stage, so-called WBG semiconductors.Research companies and groups worldwide are investigating this new technology currently.
As previously mentioned, the most common WBG materials used currently to assemble power devices are Gallium Nitride (GaN) and Silicon Carbide (SiC) in commercial applications, although variations and other materials are also being explored in research, e.g., Ge, GeSn, AlGaN, GaAs, 4H-SiC, 2H-GaN, Ga 2 O 3 , diamond, and 2H-AlN, materials listed in [21,22].It was proven that, for high-voltage applications (>1200 V), SiC is a better option compared to GaN [23].Lateral GaN devices present limitations in terms of voltage and current capability because of the lateral structure, which limits the technology application to a lower voltage level.Comparatively, GaN material presents better characteristics than SiC, but due to the aforementioned limitation, GaN components are on the market for a voltage range up to 650 V.
GaN is a promising WBG technology for the applications in, e.g., BAPV/BIPV and in low-voltage DC networks, since the limited DC or AC voltage range is within the boundaries of this device.Therefore, the aims of this paper are the following: (1) present a brief review of the current state-of-the-art WBG GaN technology available on the market for low-voltage applications (<650 V); (2) give to power electronics engineers insights about the design and application challenges/recommendations that this new technology offers; and (3) discuss, based on different figures-of-merit, which technology, between GaN and Si, is the possible candidate for the next generation of power electronics converters.In the end, it is expected that the reader will have a clear vision about the different GaN technologies and which option suits better its specific applications.
The GaN devices on the market typically present different packages and characteristics, which lead to distinct circuit designs and thermal management challenges.In order to have a better understanding about the aforementioned criteria, the document will discuss, in Section 2, the GaN's internal structure (enhancement-mode (e-mode), cascode, depletion-mode (d-mode)) and the advantages and disadvantages of each technology available on the market.This discussion is relevant to situate specific applications of each technology, and based on this selection, different approaches, for instance, in terms of driver stage and heat sink selection, can be taken into consideration for final integration.Practical design challenges in terms of layout and cooling strategies will be further discussed in Section 3. Finally, a qualitative comparison between similar 650/600-V and 100-V GaN and Si power semiconductors is provided in Section 4 in order to discuss the important figures-of-merit that should be considered by designers when projecting its converters for such applications.

Device Configuration
According to [24], semiconductors with high band gap properties allow for higher operating temperatures, since a lower leakage current will be generated once these components present stronger chemical bonds at the lattice band.Internally, each GaN has its own layer structure [25][26][27][28].More specifically, GaN components can be made by GaN-on-GaN [29,30] or GaN-on-Si [31][32][33] substrates, for instance.
From the power electronics engineer perspective, special attention to understand the physical limits of the devices that will be applied in the circuit is necessary in order to select and project driver and power stages correctly.For instance, parasitic components and switch characteristics, e.g., threshold voltage, maximum/minimum gate voltages, and gate storage energy, constitute the essential information in order to project the driver stage accordingly for the selected switch.R ds−on is the parasitic element that defines the equivalent circuit of the device when conducting; hence, conduction losses can be calculated using this parameter.Tests under controlled conditions are also important to measure the transition times between on/off states.This information is important to calculate the switching losses under hard-switching applications.
GaN semiconductors, from the power electronics point of view, are divided into three main categories: depletion-mode, cascode-mode, and enhancement-mode.The category in which the device will be included is dependent on the internal structure and layout during its production, as mentioned above.These devices will be briefly discussed in this section.

Depletion-Mode
Depletion-mode devices are inherently "normally-on".Normally-on semiconductors present better R ds−on * Area if compared with normally-off GaN (cascode-mode and e-mode) and Si semiconductors, although it becomes more challenging for implementation, since its default state is "ON".This characteristic leads to the adoption of additional protection [34] and/or a soft-start synchronization at the driver stage in order to guarantee the switch operability before system connection, otherwise short-circuits may occur depending on the topology implemented.
This device turns-on with 0 V between gate-source terminals.Positive voltages can also be applied to turn-on the device, although extra circuitry or an extra voltage source needs to be used to achieve this requirement.To commute the semiconductor to the "OFF" state, a negative voltage of −15 V-−20 V has been reported in the literature [35,36] for d-mode devices.Figure 3a shows the representation of a d-mode device with its gate-source voltage levels.Additionally, application of d-mode devices also brings challenges for the gate-driver circuitry of these devices.Since its creation, many gate driver circuits have been proposed to overcome the issue with the voltage level.Some of these driver circuits are adjustable [37], depending on the threshold and full turn-on/-off voltages of the devices.Resonant drivers [38] are also reported in the literature.Ishibashi et al. [39,40] proposed a new driver solution based on the connection of a capacitor in series with the output gate-driver resistor.This capacitor is previously charged before it starts the device operation and is responsible for applying the required voltage between gate-source terminals of the semiconductor.

Cascode-Mode
The cascode structure was created to overcome the normally-on behavior of the d-mode GaN devices, since normally-on devices are not desirable in most power electronics applications that require a fail-safe operation.To do so, a Low-Voltage (LV) Si-based MOSFET (typically 30 V) is implemented in series with the High-Voltage (HV) GaN device [41][42][43][44].The device structure is shown in Figure 3b.The drain and source of the LV Si device are connected, respectively, to the source and gate of the HV GaN.
The switching behavior of this device will be briefly described.When the devices are in the off-state, the drain-source parasitic capacitance of the LV Si MOSFET is charged.Considering no internal parasitic inductances between the above-mentioned terminals and the HV GaN gate-source terminals (no delay included in the analysis), the voltage applied in the HV GaN gate-source is the negative value of the drain-source voltage of the LV Si device, characterizing the normally-on behavior of the HV GaN (off-state with negative voltage).When it is applied a gate-signal to turn the LV Si switch "ON", the channel of the Si switch is closed, and both Si drain-source and GaN gate-source capacitances discharge through the Si channel, decreasing and increasing the terminals voltage, respectively.When the drain-source voltage of the Si device is 0 V, the gate-source voltage of the HV GaN device is at the same voltage level, and the GaN device is fully-on (normally-on characteristics).
The LV Si MOSFET now drives the GaN semiconductor, adapting the control signals of the device, which previously needed a negative power supply to drive the normally-on GaN, and now, with the cascode structure, a positive voltage is used to turn-on the device.Conventional Si drivers can be implemented in this circumstance.An adaptation on the cascode control was proposed by Texas Instruments in [45], when the LV Si MOSFET was used only to start the device and remained in the on-state during the entire operation, instead of switching together with the HV GaN, for normal cascode operation.
In its internal structure, d-mode GaN devices do not have an anti-parallel body-diode, which brings the benefit of mitigating the reverse recovery losses during the switching transient.When an LV Si MOSFET is connected in series, adapting the device to become normally-off, the Si anti-parallel diode is internally inevitable and is added to the switch structure (check Figure 3b), which leads to an increase of reverse recovery losses at the device level.Moreover, the implementation of an LV Si MOSFET in series with an HV GaN device also increases the switch on-resistance, increasing the overall losses under the device's conduction stage.Hence, this technique was adopted only for GaN devices in the range of 600-650 V, when the on-resistance of the cascode device was not strongly affected by the introduction of the LV Si MOSFET.
An advantage of cascode-mode is related to the threshold voltage of the devices, since the LV Si MOSFET the responsible for driving the HV GaN.This configuration allows the application of a regular gate-driver circuit, once the LV Si switch is the component that drives the HV GaN.The gate driver and normally-on characteristics of the d-mode devices are bypassed by the cascode-mode, although the reverse recovery of the device increases by the application of a Si MOSFET, which also negatively affects the overall speed of the device.

Enhancement-Mode
The enhancement-mode device is structurally similar to the depletion-mode, since no LV Si MOSFET is implemented.The main difference between d-mode and e-mode devices is that the e-mode GaN is internally adapted to be able to turn-on with a positive voltage and turn-off with 0 V or negative voltages.This adaptation is made by introducing, for instance, an additional layer of p-doped GaN or AlGaN in between the gate and the AlGaN surface of the device.This addition shifts the threshold voltage, making it into a normally-off device, in which a positive voltage turns-on the device and a 0 V or negative voltages turns-off, as shown in Figure 3c.
Enhancement-mode devices add the advantages of the depletion-mode (no LV Si MOSFET in series) and the cascode-mode (normally-off structure) devices, which leads to a better switching behavior with less losses and a simpler driver implementation.The main drawback of the structure is related to the low threshold voltage of the device (check Table 1), in which it makes the component susceptible to ringing, since its voltage margin between 0 V and V th is extremely low.Additionally, to fully turn-on the device, the voltage level should be between 5-6 V (depending on the manufacturer), and the maximum allowed voltage between gate-source terminals is in the order of 7 V, which leads to an extremely low margin between fully turned-on and maximum gate voltages.Therefore, the gate channel can collapse if the voltage is not controlled to stay under the device limits.

Comparison between GaN Structures
To be able to compare the different structures, some Key Performance Indicators (KPIs) are defined for the 600-650-V GaN devices (components available on the market or tested as samples).For an application point of view, the important parameters that should be verified before component selection are shown in Table 1.Comparing the three structures, it can be noticed that the normally-off devices present lower values in terms of drain-source on-resistance compared with the cascode structure, for similar current levels.This KPI is directly related to the conduction losses performed during normal operation.Additionally, normally-off devices present zero reverse recovery and lower gate charge compared with cascode devices, decreasing the commutation losses.On the other hand, cascode and normally-on devices are less susceptible to inappropriate turn-on/-off since the threshold voltages are higher than the normally-off GaN devices on the market.This KPI brings an additional challenge for PCB designers, and this will be discussed in Section 3.

Advantages and Disadvantages of Each GaN Technology
Based on the discussion presented in Section 2, partial conclusions regarding the GaN technologies are depicted:

•
The normally-on device brings a cost benefit for manufacturers in terms of production, although presenting a limited amount of applications and gate-driver challenges (synchronization and/or extra safety) in order to have a safe operation.Possible applications include current-fed converters and converters with short-circuit protection schemes integrated.

•
Cascode GaNs bring the benefit of normally-off devices with a higher threshold voltage.
On the other hand, the devices present reverse recovery due to the LV Si MOSFET and higher on-resistance and internal parasitics compared with other GaN technologies.Since this component is more immune against gate oscillations (discussed in Section 3.1.3),this component is suited better in applications with multiple switches, e.g., multi-level converters and high step-up and step-down applications.

•
Normally-off GaNs present the lowest gate charge and on-resistance compared with the aforementioned GaNs, while having the lowest threshold voltage.Thus, this component is more susceptible to malfunction due to gate-source ringing.Converters with ground connection to the source of the switch or limited floating points are the structure in which this device presents better performance, e.g., DC-DC boost converter, DC-DC buck converter, full-bridge, and half-bridge topologies.

Design/Layout Challenges
Since GaN has more and more appeal on the power electronics market and in the research community, topics related to PCB design, thermal loss extraction, and challenges related in how to control overvoltages due to fast switching and, consequently, gate oscillations will be discussed herein.The objective is to highlight the challenges that designers are facing when changing from the conventional Si to GaN devices and to provide insight into how to overcome these issues.

Device Package
Available on the market, most of the GaNs are Surface-Mounted Devices (SMD).This trend relates primarily to decreasing the parasitic inductances between the device terminals, since this component can operate at high switching frequencies, and these parameters play a major role in switching performance [49][50][51][52][53].The GaNs available have much smaller packages as compared to the TO family: 83-times smaller than TO-247-3 and 45-times smaller than TO-220 (considering only the package), which brings the benefit of space reduction, as shown in Figure 4, although the thermal cycle of the device should be addressed carefully.However, some off-the-shelf GaN devices are made in the TO-220 package [46].SMD components also bring the benefit of decreasing the power loop parasitics, since the drain-source-gate-kelvin pins are directly connected to the PCB and not via external pads, as for the TO family shown in Figure 4.

Internal Parasitics
In Figure 3, ideal devices are depicted.Since GaN semiconductors can operate at high switching frequencies due to their fast transient both to turn-on and turn-off, the internal and external parasitics due to, respectively, internal bond-wire connections and PCB layout need to be considered and minimized during device production and the PCB layout project in order to maximize device and system performance.As power electronics engineers, the only feature that can be controlled in this case is the PCB design parasitics, as the switches are off-the-shelf selected.Figure 5a shows the main internal parasitic components inside a cascode GaN device [54,55].It can be noticed that the structure of the cascode device increases the number of internal parasitic inductances and capacitances to be considered in the analysis.
A basic model of a normally-off GaN device is shown in Figure 5b.Some manufacturers provide an extra pin, the so-called Kelvin connection (Figure 5b illustrate this connection).This pad provides the return for the gate driver, minimizing or even eliminating the influence of the parasitic common source inductance in the driver circuit.This pin, however, is not present in all devices.In these circumstances, the source return track of the driver circuit should be placed as close as possible to the gate pin, as shown in Figure 5c, minimizing the influence of the aforementioned inductance in the driver stage and minimizing the gate driver loop.As mentioned previously, a negative voltage is recommended to turn-off cascode-mode and e-mode GaN devices.However, this feature increases the number of components in the driver stage, hence the complexity of the circuit.Increasing the number of components in the driver stage, the minimization of the parasitic inductances in this part of the circuit becomes a challenge during the design stage.In Section 3.1.3,more details regarding this topic will be presented.

Signal and Power Loops
The two critical loops that should be carefully projected in order to achieve the best performance of these devices are the signal and power loops, as highlighted in Figure 6a.As previously mentioned, the parasitic inductances and capacitances influence the performance of these devices [56,57], but they are not the only ones.Copper-based planes and tracks interconnect the components on a PCB layout.These connections increase, primarily, the parasitic inductances of the loops, and consequently, these loops should be carefully routed and minimized in order to achieve a better circuit performance.
The signal loop or gate driver loop is the circuit that drives the GaN devices.The transition speed of the device is directly related to the R gon and R go f f and the voltage levels applied at the gate/source terminals.The R gon controls the turn-on slew rate dv dt of the GaN device.If the gate resistor is too small, the dv dt is high, and ringing between drain-source (overvoltage) and gate-source terminals might occur [58].This gate-source ringing, if not properly addressed, can cause an inappropriate turn-on if the voltage V gs becomes higher than the threshold voltage V th of the device.A negative voltage to turn-off the GaN component is recommended to minimize this influence, giving more margin between the turn-off voltage plateau and the threshold voltage of the GaN, although this strategy increases the gate-driver circuitry complexity and the energy consumption of the circuit.R go f f is responsible for the pull-down of the device to the off-state.
Gate oscillations are also caused by the power loop parasitics, and this loop should be carefully addressed in order to eliminate unintended device turn-on.The gate oscillations is generated by the common source inductance in the power loop and gate inductances in the signal loop.Both inductances should be minimized during the PCB design stage.The switches need to be placed as close as possible to each other to minimize the common source inductance.Additionally, the output of the driver stage (R gon and R go f f ) should be placed as close as possible to the gate of the switches to minimize the driver loop and, consequently, the gate parasitic inductance, as illustrated Figure 5c.
As shown in Figure 6b (adapted from [45]), drain-source overvoltages can be observed in the GaN e-mode terminals.All the parasitic capacitances will be charged during the turn-off transient.The overvoltage generated by common source inductances at the power stage level can improperly turn-on the GaN devices since the gate-source signal might present ringing above the threshold voltage level.An experimental verification showing in practice the relatively low threshold level is depicted in Figure 7.It can be noticed that the gate-source voltages from nearby GaN devices were also affected by the ringing.This event happened since the low internal parasitic capacitance values of these devices are not completely immune, and the noise propagates throughout the circuit.Additionally, the components perform an excessive ringing since they are connected to multiple floating points, which brings an extra challenge since the circuit might have multiple topological stages during one switching period, leading to multiple ringing events in one switching cycle.
Snubber circuits [43,[59][60][61] are an alternative to suppress switch overvoltages generated by fast switching transients or bad PCB design.Some snubber circuits are regenerative, which configure an advantage since no energy is dissipated during the commutation period (all energy stored in the snubber is returned to the circuit), although some of these configurations are ratter complex and require more PCB space.On the other hand, some snubber circuits, e.g., RC and RCD snubbers, are passive structures, which reduces the overall efficiency of the circuit by consuming some power, although these are simple structures that do not require a large amount of PCB space.From the discussion, some key points can be highlight that should be taken into consideration while developing power converters applying GaN semiconductors: PCB design is crucial to achieve the best performance of the GaN devices.

•
Power and signal stages should be carefully addressed and routed in order to minimize the parasitic inductances that disrupt the performance of the GaN device.Some devices on the market already integrate GaN devices and their driver circuits in the same package [62][63][64][65].
• Although 0 V is sufficient to turn-off the GaN e-mode devices, a negative voltage is preferred in order to increase the noise immunity against ringing at the driver stage, as shown in Figures 6 and 7.

•
Gate-resistors are used to control the speed of the device, and its placement during the design stage should be as close as possible to the gate pin of the GaN semiconductor.As mentioned above, monolithic integration of the switch and driver in the same package has been considered for the new generation of GaN power devices.Although this strategy brings the benefits of loops and parasitic minimization, mitigating voltage dips that might collapse the gate of these devices, it also takes away the freedom to control the rise and fall times of the switch by selecting the proper gate resistors.Additionally, these structures can be used to build simple topologies, e.g., buck, boost, buck-boost, and full-bridge.More complex structures still require separate switches and drivers.

•
Components that present Kelvin connection internally decouple the common source inductance on the power stage of the device.For components that do not offer this extra pin, the gate return pad should be connected as close as possible to the gate of the GaN device, as shown in Figure 5, minimizing the parasitic inductances at the gate level.

Thermal Management
As previously mentioned, GaN devices cannot achieve their best performance if used in conventional TO packages, although some options are available on the market [46].Manufacturers are now developing new packages to overcome parasitic problems related to GaN devices, most of them SMD packages.These new packages introduce an extra challenge for power electronics engineers: thermal management.Thermal heat transfer proves to be correlated with the overall performance and reliability of the device [66], and some studies in the field have been realized [67].
Reported in the literature [68][69][70][71][72], GaN components can survive much higher temperatures, in controllable environments, than the Si competitor.For applications in power electronics, a major issue is related in how reliable these devices are to operate in harsh environments, for instance deserts (high ambient temperature) or space (difficult/impossible access to maintenance).Some discussions on this topic are found in the literature [73].Making these components as reliable as possible is a challenge faced by semiconductor researchers.Studies show that changes in the internal layer distribution/composition [74][75][76] and gate overdrive protection [77] improve the reliability of these devices.Additionally, the temperature-dependent thermal resistance and reliability of these devices are also an important point, as discussed in [78].SMD packages are extremely compact, but might introduce thermal problems related in how to extract the heat, generated by conduction and switching losses, from these devices.Research is being conducted to improve the heat dissipation packaging [79] and the thermal management of these devices [80].Some companies claim that its packages have good thermal transfer capability, in which a heat sink can be directly attached to it.In some cases, a thermal pad is provided on top of the device package [47] to help the heat extraction using passive cooling.In these cases, an SMD or regular heat sink is directly attached to the device, as shown in Figure 8a.Some devices on the market also provide a bottom thermal pad [81] to improve the thermal extraction.This pad needs to be connected directly with the source pin of the device.Most of the devices available on the market do not present thermal pads, nor packages with good thermal transfer capability, which lead to some extra effort to keep the device temperature below its limit.Some of the strategies used are presented in Figure 8b-d.Since these devices transfer the heat through the source pin, some thermal vias are used to connect top and bottom copper layers on the PCB level, and interfaced by a Thermal Interface Material (TIM), a heat sink is attached to spread and cool down the devices (Figure 8b).Another technique is to create a copper region connected to each source of the devices using the top layer of the PCB and attach an SMD heat sink to each device source terminal (Figure 8c).Another option listed herein is to use inner copper layers as heat sinks, increasing the number of layers in the PCB design and using one or more layers, with a large copper plane area, as the heat sink (Figure 8d), helping to extract the heat from these devices.Depending on the project specifications and the chosen technology, the best cooling method among the possible ones can be applied to achieve the maximum component, circuit, and system performance.

Comparison between GaN and Si Semiconductors
As previously mentioned, GaN devices are a possible competitor of Si devices currently.Table 1, however, shows just a comparison between different lateral GaN devices/technologies.This comparison is now expanded for Si components with similar voltage and current specifications, similar to Table 2.These devices will be addressed herein with discussions related to their internal characteristics and some important figures-of-merit.These figures-of-merit are important in order to compare the available technologies on the market and show the importance of a good choice for applications in different circuit topologies.
In [82], the author stated that the device parameters should be compared for components with similar current density J on and not a similar current level.From the power electronics point-of-view, however, information regarding current density and, more specifically, die or chip area is not provided in datasheets, which leaves no other option than selecting components with a similar current capability for comparison.Therefore, the comparison made herein is between 650/600-V and 100-V GaN and Si devices for similar current levels available on the market.As previously mentioned, one of the main advantages of GaN normally-off devices is the absence of reverse recovery, since no body diode is present in their internal structure.This characteristic is interesting to mitigate part of the switching losses during turn-on of the device since with no body diode, no reverse recovery is observed during the transition between off-and on-states.
FOMs are used to compare materials/technologies and define their theoretical boundaries/ limitations.Some of these FOMs are important in the power electronics field in order to compare fairly devices and have a good indication of their performances [82][83][84][85][86][87].These FOMs will be discussed herein, bringing insights for power electronics engineers about which characteristics should be taken into account when selecting active switches for project implementation.Firstly, the FOM shown in (2) compares the on-resistance of the device (R ds−on ) and the stored energy across the gate-source terminals (Q g ); hence, conduction and driver loss indicators are obtained for the analyzed device.As highlighted in Figure 9 and Table 2, both 650-V and 100-V GaN devices present better theoretical FOM1 compared with Si technology, and, consequently a better performance is expected in power electronics applications.This figure can be interpreted as follows: the closer the dots and/or regions are to the bottom-left corner, the better will be the performance of the semiconductor, since the device will present both lower conduction losses (related to the R ds−on value) and driver losses (related to the gate charge energy Q g ).The dashed arrow in Figure 9 shows the difference between GaN devices packed in TO-220 [46] and state-of-the-art Si components [88][89][90].The continuous line shows the distance between the SMD GaN devices [47,81] available on the market and the Si technology.
Proposed in [83], the FOM presented in (3) gives a good indication about the switching and conduction losses, since the energy stored at the output capacitance C oss is dissipated at the channel of the device in hard-switching applications (modeling switching losses), and the on-resistance R ds−on represents the conduction losses.Analyzing the data in Table 2, GaN devices present a better FOM and are a viable alternative for hard-switching applications with lower switching losses.Finally, the Power-Density-FOM (PDFOM), proposed in [84], is also an important FOM to be discussed, since it considers the package dimensions, together with the thermal and electrical characteristics of the semiconductors.As described in [84] and repeated herein for didactical reasons, Equation (4) brings a figure-of-merit that considers conduction (R ds−on ) and switching (Q gd ) losses (electrical characteristics), together with thermal resistance R thjc (thermal characteristics) and package dimensions A pack (size of the package).The higher the value returned by this FOM, the higher can be the power density of the converter, since a good compromise between all the aforementioned characteristics is achieved.This figure-of-merit is a good indicator of the fact that, considering the thermal resistance, losses and package dimensions, the size of the heat sink, one of the bulkiest components in a power electronics converter, can be estimated.

Conclusions
This paper summarized the challenges faced by power electronics engineers when it comes to GaN application in power electronics circuits.Important discussions related to the different GaN devices available on the market and their advantages and disadvantages were highlighted in the paper.Comparing the normally-on, cascode, and normally-off lateral devices, from an application point of view, the normally-off devices provide the best cost/benefit, since they present a lower internal parasitic component that enables the application at high frequencies with lower switching and conduction losses, although it is the device with the lowest immunity in the gate-source pins and lowest threshold voltage, which increase the driver and power stage layout complexity.Consequently, a careful power and signal design needs to be considered in order to achieve a noise immunity between the gate-source pins to neither experience shoot-through, nor achieve the breakdown voltage of the devices.
A comparison between GaN and Si technologies was also presented.Gallium nitride devices present better electrical characteristics and FOMs compared with Si-based MOSFETs.The SMD packages of GaN devices raise the thermal design challenge, since a device with a much smaller footprint might present higher temperatures and difficulties to extract the heat.A discussion related to this topic was addressed, showing some possible strategies to cool down the devices.Based on manufacturers' datasheet information, power electronics designers should carefully analyze some essential data provided (Table 2) to know if the package has good thermal transfer capability.Additionally, some FOMs were revised herein, giving the reader some indicators to define which semiconductor offers the best theoretical performance, considering conduction and switching losses, together with thermal transfer capability.
The thermal management and PCB layout should be carefully addressed during the design stage.As pointed out in Section 3.1.3,driver and power stage layouts are extremely important in order to achieve the best performance of GaN-based devices.Minimization of the parasitic inductances in both circuits is important.It was also mentioned that, due to a small margin between 0 V and the threshold voltage of the GaN devices, a negative voltage is recommended to pull-down the component, which increases the complexity of the driver stage and the challenge to minimize the parasitic inductances at the driver circuit.
Figures-of-merit were used to compare different GaN and Si components.These FOMs are important for converter designers to identify possible switches that are candidates to perform correctly within a specific project application.Devices were compared according to the PDFOM, a figure-of-merit that accounts for the electrical properties, thermal properties, and package dimensions.This FOM

Figure 1 .
Figure 1.Interconnection of PV panels into the grid and emphasis on the basic components of power electronics converters.

Figure 2 .
Figure 2. Baliga's figure-of-merit to show the technological limit of each semiconductor material.

Figure 3 .
Figure 3. Different structures for GaN devices on the market: (a) normally-on GaN device; (b) cascode GaN device; and (c) normally-off GaN device.

Figure 4 .
Figure 4. Size comparison between TO-247, TO-220, and SMDGaNs available on the market.

Figure 5 .
Figure 5. Internal parasitics in: (a) cascode GaN; (b) normally-off GaN; and (c) project example of how to connect the return source pin if no Kelvin connection is available.

Figure 6 .
Figure 6.(a) Critical loops in a power electronics converter design; and (b) drain-source overvoltage and its impact on gate-source voltage level.

Figure 7 .
Figure 7. Experimental verification of the capacitive coupling in GaN devices: drain-source overshoot and its influence on the gate-source signal.

Figure 8 .
Figure 8. Thermal techniques to extract heat from SMD GaN devices.

Figure 9 .
Figure 9.Comparison between GaN vs. Si components considering conduction and driver losses.

Table 1 .
Application KPIs for comparison of normally-on, cascode and normally-off GaN devices.

Table 2 .
Application KPIs for comparison of normally-on GaN, cascode GaN, normally-off GaN, and Si devices.