Dual 3-Phase Bridge Multilevel Inverters for AC Drives with Voltage Sag Ride-through Capability

: One of the main power quality issues that can a ﬀ ect variable speed drives (VSDs) is the occurrence of voltage sags on their AC power supply. Voltage sags can a ﬀ ect the inverter nominal operation, leading to a malfunction of the AC motor. This paper presents an inverter with resilient capability to voltage sags. The topology consists of two conventional three-phase bridge inverters arranged to require just a single DC source. This inverter is also characterized by a voltage multilevel operation, providing the full advantages of multilevel converters without the need for level balancing. Associated with this AC motor driver, a control system based on a ﬁeld-oriented controller with a vector voltage modulator that will enable voltage sag ride-through capability is proposed. The proposed control system does not require any changes in the occurrence of voltage sags. To verify the characteristics of the proposed drive and control system, simulation tests are provided. Simulation results conﬁrm the voltage sag resilient capability of the proposed multilevel converter.


Introduction
A major issue in industry applications is related to the power quality in the AC electrical grids [1]. In fact, due to the lack of AC power quality, important and costly losses in several industrial and business companies have been reported [2]. Among several power quality issues, one of the most hazardous is the occurrence of sags in the AC voltages [3]. This type of perturbation is normally originated by line faults or by sudden over-currents in the distribution lines, decreasing the AC voltage RMS value below 90% of the rated value and lasting from one AC grid cycle to few seconds. In fact, the Institute of Electrical and Electronics Engineering (IEEE) has a standard, numbered by 1159-1995, that defines voltage sag as "a decrease of 0.9 to 0.1 pu in the effective nominal voltage of half a cycle to 1 min duration" [4]. There is also another standard from a different institution, as is the case of the International Electrotechnical Commission (IEC). In this case, the definition of a voltage sag is given by the standard IEC 1000-2-1 [5], which is a sudden reduction of the voltage at a point in the electrical system, followed by a voltage recovery after a short period of time (from 0.5 cycle to a few seconds).
The variable speed drive (VSD) is a very important piece of industry equipment that can be severely affected by voltage sag perturbations, since AC drives are constant power loads. Most VSDs have power converters to drive three-phase induction motors. The typical topology used in VSDs includes a three-phase bridge diode rectifier, which provides a DC bus voltage to a single three-phase voltage source inverter (VSI) feeding the AC motor. The main disadvantage of this VSD is that it is very sensitive to voltage sags and short interruptions. In fact, the AC voltage RMS value decreased during Although open-end windings and two 3-phase VSIs topologies present several advantages over the single 3-phase VSI solution, very few studies have been made regarding the voltage sags issue and the possible advantages/disadvantages, namely the sag ride-through capability of the open-end windings dual inverter topology when subjected to voltage sags and similar disturbances. In fact, the previous works have usually been focused on the voltage boost capability of the rectifier (in VSDs with back-to-back inverters). However, due to the limitation of the boost gain, this solution presents limits regarding the decrease of the source voltage. As said before, many of the solutions require extra components, which increase the cost, complexity, and efficiency of the system. Therefore, to provide a better voltage sag ride-through capability in VSDs, this paper proposes the use of open-end windings and dual VSI structure for the AC VSD. This solution does need any extra power converter or components. To minimize the DC voltage source count and at the same time the referred voltage sags ride-through, only one of the 2 inverters is connected to the DC supply. Therefore, the two inverters may be operated in an asymmetrical regime. Besides the boost capability of the rectifier, there is also the capability to boost the floating capacitor voltage. Taking this into consideration, in this work, the capability to change the reference value for the floating capacitor voltage is also explored as a way to achieve a higher immunity to deep voltage sags. The proposed multilevel topology and controller allows boost operation without any extra converters or components. Another aspect of the topology regards the design aspects of the converter. In this case, since the topology presents boost capability, the voltage droop associated with the inductors used as filters is not critical in this system. Regarding the capacitors, their capacitance is also not critical due to that capability, although some stored energy is needed to be voltage sag resilient. Capacitors can be designed considering only the limitation of the ripple function of the switching frequency and load as usually is done in VSDs with the capability to ride-through voltage sags. A control system is also proposed for the two 3-phase VSIs with open-end windings and designed to maintain motor operation conditions during the occurrence of voltage sags. Associated with this control system, the use of a voltage vector modulator is proposed. In this context, the impact of the voltage vectors under several references of the floating voltage capacitor is also addressed. The performance of AC VSDs fitted with the dual VSI structure is tested through several simulation tests.

Proposed Multilevel Inverter with Voltage Sag Ride-through Capability
Conventional VSDs for three-phase AC motors are based on a three-phase two-level VSI supplied by a full-bridge diode rectifier ( Figure 1). The diode rectifier has no control over the DC bus voltage. Therefore, the DC voltage level is strongly dependent on the AC voltage RMS value, the VSDs performance being highly dependent on the DC-link voltage, since industrial AC motors give little margin to the DC Bus voltage variation. This fact makes existing VSDs very sensitive to voltage sags. Furthermore, the single inverter topology is also limited by the number of voltage levels that can be applied to the motor, imposing a high rate of rise of applied voltage in the motor windings. This section presents a circuit configuration to achieve the voltage sag ride-through capability. Figure 2 shows the proposed configuration, where the motor has open-end windings. Two 3-phase VSIs are connected to each side of the windings. One 3-phase VSI is DC fed from to the diode bridge rectifier while the second 3-phase VSI is connected to a DC floating capacitor. This capacitor enables the use of a single DC source (the diode bridge rectifier). This DC floating capacitor will be charged by the DC source constituted by the diode bridge rectifier and through the inverter that is directly connected to that source. Thus, proper control of the two inverters is essential to charge/discharge the floating capacitor, as is shown in next section.

Comparison with Other Topologies
As described in the introduction, several solutions have been proposed to eliminate or attenuate the problem of the voltage sags in AV VSDs. To point out the differences between existing solutions and the herein proposed topology and impact in the drives, Table 1 lists several characteristics, enabling comparisons. In the classical AC VSD structure, the immunity to voltage sags is clearly dependent of the storage element. Since the capacitor used in these drives usually does not have the required capacitance for sag ride-through, the sag immunity of the drive is very low. Thus, solutions using supercapacitors or batteries have also been proposed. Besides the cost of these storage elements, in some solutions the use of an extra power converter was also proposed, which further increases the system cost. Another solution was presented in [22], which uses a DC-DC buck-boost converter after the diode rectifier. However, this solution requires extra power semiconductors, higher voltage capacitors, and an extra storage element (inductor). To avoid the extra DC-DC converter, but still presenting boost capability, the use of an active rectifier (back-to-back inverter) was also proposed. This may give high immunity to voltage sag. However, it requires extra switches and depends on the control speed of the rectifier side. To provide multilevel capability to the AC VSD, the ABB company introduced a new multilevel topology [38]. This drive was named as ACS 200 and is characterized by ride-through functionality. However, this topology requires an important number of extra switches and capacitors. The herein proposed solution is also characterized by their multilevel operation. Nevertheless, it only requires an extra two-level three-phase inverter with a floating capacitor. It presents boost capability, even if used with a diode rectifier. It also can be used with an active rectifier, and, in this case, there are two converters with Boost capability, the rectifier and the inverter. In this way, the herein proposed topology will present a very high immunity to voltage sags.

Comparison with Other Topologies
As described in the introduction, several solutions have been proposed to eliminate or attenuate the problem of the voltage sags in AV VSDs. To point out the differences between existing solutions and the herein proposed topology and impact in the drives, Table 1 lists several characteristics, enabling comparisons. In the classical AC VSD structure, the immunity to voltage sags is clearly dependent of the storage element. Since the capacitor used in these drives usually does not have the required capacitance for sag ride-through, the sag immunity of the drive is very low. Thus, solutions using supercapacitors or batteries have also been proposed. Besides the cost of these storage elements, in some solutions the use of an extra power converter was also proposed, which further increases the system cost. Another solution was presented in [22], which uses a DC-DC buck-boost converter after the diode rectifier. However, this solution requires extra power semiconductors, higher voltage capacitors, and an extra storage element (inductor). To avoid the extra DC-DC converter, but still presenting boost capability, the use of an active rectifier (back-to-back inverter) was also proposed. This may give high immunity to voltage sag. However, it requires extra switches and depends on the control speed of the rectifier side. To provide multilevel capability to the AC VSD, the ABB company introduced a new multilevel topology [38]. This drive was named as ACS 200 and is characterized by ride-through functionality. However, this topology requires an important number of extra switches and capacitors. The herein proposed solution is also characterized by their multilevel operation. Nevertheless, it only requires an extra two-level three-phase inverter with a floating capacitor. It presents boost capability, even if used with a diode rectifier. It also can be used with an active rectifier, and, in this case, there are two converters with Boost capability, the rectifier and the inverter. In this way, the herein proposed topology will present a very high immunity to voltage sags.

Comparison with Other Topologies
As described in the introduction, several solutions have been proposed to eliminate or attenuate the problem of the voltage sags in AV VSDs. To point out the differences between existing solutions and the herein proposed topology and impact in the drives, Table 1 lists several characteristics, enabling comparisons. In the classical AC VSD structure, the immunity to voltage sags is clearly dependent of the storage element. Since the capacitor used in these drives usually does not have the required capacitance for sag ride-through, the sag immunity of the drive is very low. Thus, solutions using supercapacitors or batteries have also been proposed. Besides the cost of these storage elements, in some solutions the use of an extra power converter was also proposed, which further increases the system cost. Another solution was presented in [22], which uses a DC-DC buck-boost converter after the diode rectifier. However, this solution requires extra power semiconductors, higher voltage capacitors, and an extra storage element (inductor). To avoid the extra DC-DC converter, but still presenting boost capability, the use of an active rectifier (back-to-back inverter) was also proposed. This may give high immunity to voltage sag. However, it requires extra switches and depends on the control speed of the rectifier side. To provide multilevel capability to the AC VSD, the ABB company introduced a new multilevel topology [38]. This drive was named as ACS 200 and is characterized by ride-through functionality. However, this topology requires an important number of extra switches and capacitors. The herein proposed solution is also characterized by their multilevel operation. Nevertheless, it only requires an extra two-level three-phase inverter with a floating capacitor. It presents boost capability, even if used with a diode rectifier. It also can be used with an active rectifier, and, in this case, there are two converters with Boost capability, the rectifier and the inverter. In this way, the herein proposed topology will present a very high immunity to voltage sags.

AC VSD Model with the Proposed Multilevel Inverter
The model of the AC VSD presented in Figure 2 can be obtained considering that the power switches of each leg are defined as S ij and S ij , where I represents each of the inverters (1, 2) and j represents each of the legs (1, 2, or 3). Considering ideal power switches, the variables representing their switching states can be binary quantities. Consequently, it will be considered S = 1 when the switch is conducting (ON state mode) and S = 0 when the switch is turned OFF. Thus, in accordance with this and from the analysis of the converter power circuit, the AC voltages of the VSD (applied to each of the motor winding) are functions of the switches' states, S ij , and DC voltages, From the analysis of Equation (1), supposing V DC1 = V DC2 = V DC and considering all the combinations of the switches, it is possible to obtain all the multilevel output voltages applied to each of the windings. The maximum voltage is 1.333 V DC , higher than the V DC voltage, therefore allowing some margin for handling voltage sags.
In order to obtain a vector representation of the multilevel inverter AC voltages in the αβ0 system coordinates, a Cark-Concordia transform is used. Thus, applying this transformation [39] (multiplying by Equation (2)) to the three-phase stationary coordinate system presented in (1), the new quantities will be expressed by Equation (3).
Energies 2019, 12, 2324 (3) From this equation, and taking into consideration the states of the switches, it is possible to obtain the control system and the voltage vectors that will be used to develop a space-vector modulator for this VSD, as presented in the next section.

Field Oriented Control
The behavior of the wound-rotor induction motor can be described by the following equations, written in a reference frame synchronous with the rotor flux: where u s and u r denote the stator and rotor voltage, respectively; ψ s and ψ r represent the stator flux and rotor flux respectively; i s and i r are the stator and rotor currents; r s and r r are the stator and rotor resistances; L s , L r , and L m are the stator, rotor, and mutual inductances; ω r is the angular speed of the rotor flux vector; and ω is the rotor angular speed in electric radians. One of the linear strategies most widely applied in power electronics is the field-oriented control principle (FOC) [40]. This control technique uses an appropriate coordinate system that allows the torque, T, and the flux, ψ r , to be controlled independently of each other. In rotor flux oriented synchronously rotating reference frame, the rotor flux is controlled by the real part of the stator current, i sd , and the torque by the imaginary part of the stator current, i sq . Therefore, Equations (9) and (10) represent the stator currents references (i * sd and i * sq ) that are function of the flux (ψ * r ) and torque (T) references, as follows: The location of the flux vector can be obtained by a simple velocity observer (ω), which is obtained by the measure of the rotor rotation speed (ω r ), (11).
These are the basic principles of FOC, their equations were implemented through Simulink blocks. The induction motor parameters have been obtained by manufacturer's catalogue, given in the table that is presented in the results Section 5.

Current Controller
As previously verified, the controller of the motor requires the control of the stator currents in dq coordinates. In this way, a sliding mode current controller can be adopted defining sliding surfaces S d and S q as follows: where k is a positive definite constant. To ensure that the system reaches the sliding surface, to track the output reference current, a voltage vector modulator in the αβ plane is devised. To work on αβ coordinates, transformed switching functions that consider the currents in the αβ coordinates are defined as follows: where k α , k β are positive definite constants selected to limit the switching frequency of semiconductors.
The two sliding surfaces are used to select a voltage vector using a modulator. The modulator will ensure that the system trajectory will always move to the sliding surface and will stay in that surface, accordingly to the stability condition S e α,β , t • S e α,β , t < 0 [41,42]. So, the vector modulator must be designed in order to choose a vector, taking into consideration the sliding surface (4) and the stability condition. For example, if S(e α , t) < 0 this means that i * sd cos(ωt) − i * sq sin(ωt) < i α , then the chosen voltage vector must ensure • S(e α , t) > 0, which means using a vector with a positive component α and with sufficient amplitude.
To develop the required vector modulator, an analysis of the voltage vectors that the inverter can apply to the load must be performed. Thus, from Equation (3)

Impact of A Voltage Sag on the Voltage Vectors
To analyze the impact of a voltage sag on the voltage vectors that can be applied to the motor, a reduction of the VDC1 must be considered. It should be noted that, due to the structure of this topology, it is possible, through the development of an appropriate vector modulator, to maintain the voltage level of the floating capacitor (VDC2). Thus, considering a voltage sag of 20% (20% reduction in VDC1), the amplitude of the voltage vectors will also be affected (Figure 4a). In fact, in this situation, the amplitude of the vectors will be reduced. For example, for the vector with a higher amplitude (for example the one located in the rightmost point) the amplitude in the αβ plane will be reduced from 1.633 to 1.469. Another impact of this reduction is that, since the two DC voltages are not equal anymore, then the number of different voltage vectors will became higher (from 19 to 49).

Impact of a Voltage Sag on the Voltage Vectors
To analyze the impact of a voltage sag on the voltage vectors that can be applied to the motor, a reduction of the V DC1 must be considered. It should be noted that, due to the structure of this topology, it is possible, through the development of an appropriate vector modulator, to maintain the voltage level of the floating capacitor (V DC2 ). Thus, considering a voltage sag of 20% (20% reduction in V DC1 ), the amplitude of the voltage vectors will also be affected (Figure 4a). In fact, in this situation, the amplitude of the vectors will be reduced. For example, for the vector with a higher amplitude (for example the one located in the rightmost point) the amplitude in the αβ plane will be reduced from 1.633 to 1.469. Another impact of this reduction is that, since the two DC voltages are not equal anymore, then the number of different voltage vectors will became higher (from 19 to 49). As expected, a further reduction of the V DC1 voltage will also further reduce the amplitude of the voltage vectors. Figure 4b shows the obtained voltage vectors for a voltage sag of 50%. In this case, the vector with a higher amplitude is decreased from 1.633 to 1.224. One of the aspects associated with this topology is that the reduction of the voltage vector amplitude is not proportional to the reduction of the DC voltage associated with the grid. In reality, it is much more attenuated since, with this topology, it is possible to maintain the voltage level across the floating capacitor (V DC2 ).

Impact of A Voltage Sag on the Voltage Vectors
To analyze the impact of a voltage sag on the voltage vectors that can be applied to the motor, a reduction of the VDC1 must be considered. It should be noted that, due to the structure of this topology, it is possible, through the development of an appropriate vector modulator, to maintain the voltage level of the floating capacitor (VDC2). Thus, considering a voltage sag of 20% (20% reduction in VDC1), the amplitude of the voltage vectors will also be affected (Figure 4a). In fact, in this situation, the amplitude of the vectors will be reduced. For example, for the vector with a higher amplitude (for example the one located in the rightmost point) the amplitude in the αβ plane will be reduced from 1.633 to 1.469. Another impact of this reduction is that, since the two DC voltages are not equal anymore, then the number of different voltage vectors will became higher (from 19 to 49). As expected, a further reduction of the VDC1 voltage will also further reduce the amplitude of the voltage vectors. Figure 4b shows the obtained voltage vectors for a voltage sag of 50%. In this case, the vector with a higher amplitude is decreased from 1.633 to 1.224. One of the aspects associated with this topology is that the reduction of the voltage vector amplitude is not proportional to the reduction of the DC voltage associated with the grid. In reality, it is much more attenuated since, with this topology, it is possible to maintain the voltage level across the floating capacitor (VDC2).   One characteristic of the dual VSI topology is the possibility of having higher voltages across the floating capacitor than the one associated with the DC source connected to the grid. Then, it is possible to compensate the reduction of the DC voltage originated by the grid. To verify this characteristic, an analysis of the increase of the voltage across the floating capacitor proportional to the reduction of the voltage of the DC source connected to the grid is also presented. In Figure 5a) is presented the obtained voltage vectors when there is a voltage sag of 20% (20% reduction in V DC1 ) and an increase by 20 % of the floating capacitor voltage (V DC2 ). Another example can be seen in Figure 5b) where is presented the obtained voltage vectors when there is a voltage sag of 50% and an increase by 50 % of the floating capacitor voltage (V DC2 ). From both figures is possible to verify that with the increase of the floating capacitor voltage (V DC2 ) is possible to compensate the reduction of the DC voltage associated to the rectifier. In fact, through this strategy the amplitude of the vectors with a higher amplitude is maintained. Figure 5 b) where is presented the obtained voltage vectors when there is a voltage sag of 50% and an increase by 50 % of the floating capacitor voltage (VDC2). From both figures is possible to verify that with the increase of the floating capacitor voltage (VDC2) is possible to compensate the reduction of the DC voltage associated to the rectifier. In fact, through this strategy the amplitude of the vectors with a higher amplitude is maintained. Besides the control of the VSD AC voltages, the balance of the floating capacitor voltage (VDC2) must also be ensured. To ensure this balance without affecting the control of the VSD AC voltages, the redundant vectors will be used. In fact, the redundant vector choice enables higher voltages than the ones generated by the usual DC voltage. According to the required voltage, the switching combination that must be chosen among the redundant vectors is a function of the sign of the three-phase motor currents. Therefore, six sectors are defined in accordance with the following condition: As said, the regulation of the voltage across the floating capacitor is ensured by the redundant vectors. As an example, let's consider VDC1 = VDC2 and that under the point of view of the load control the choice must be one of the vectors 2, 20, 38, 49, 56, and 58 (all these vectors maintain the same voltage components, as can be seen in Figure 3). Table 2 shows the switching combination and applied voltage. Thus, if the voltage of the floating capacitor is lower than the reference and the load currents are in sector I, then the voltage vector that will be adopted to ensure the charge of the Besides the control of the VSD AC voltages, the balance of the floating capacitor voltage (V DC2 ) must also be ensured. To ensure this balance without affecting the control of the VSD AC voltages, the redundant vectors will be used. In fact, the redundant vector choice enables higher voltages than the ones generated by the usual DC voltage. According to the required voltage, the switching combination that must be chosen among the redundant vectors is a function of the sign of the three-phase motor currents. Therefore, six sectors are defined in accordance with the following condition: i 1 > 0 and i 2 < 0 and i 3 > 0 − Sector I i 1 > 0 and i 2 < 0 and i 3 < 0 − Sector II i 1 > 0 and i 2 > 0 and i 3 < 0 − Sector III i 1 < 0 and i 2 > 0 and i 3 < 0 − Sector IV i 1 < 0 and i 2 > 0 and i 3 > 0 − Sector V i 1 < 0 and i 2 < 0 and i 3 > 0 − Sector VI (14) As said, the regulation of the voltage across the floating capacitor is ensured by the redundant vectors. As an example, let's consider V DC1 = V DC2 and that under the point of view of the load control the choice must be one of the vectors 2, 20, 38, 49, 56, and 58 (all these vectors maintain the same voltage components, as can be seen in Figure 3). Table 2 shows the switching combination and applied voltage. Thus, if the voltage of the floating capacitor is lower than the reference and the load currents are in sector I, then the voltage vector that will be adopted to ensure the charge of the floating capacitor is 38. Otherwise, if the voltage of the floating capacitor is higher than the reference, then the adopted voltage vector should be the 20. The previous example can be seen through Figure 6. The condition of the switches and direction of the currents regarding vector 38 is shown in Figure 6a. Through this figure it is possible to verify that the output DC current of the right placed inverter flows in a way that the floating capacitor will be charged. However, if vector 20 is selected instead of vector 38, the direction of the output DC current of the rightmost inverter will be reversed, by which the floating capacitor will be discharged, as presented by Figure 6b. The previous example can be seen through Figure 6. The condition of the switches and direction of the currents regarding vector 38 is shown in Figure 6a. Through this figure it is possible to verify that the output DC current of the right placed inverter flows in a way that the floating capacitor will be charged. However, if vector 20 is selected instead of vector 38, the direction of the output DC current of the rightmost inverter will be reversed, by which the floating capacitor will be discharged, as presented by Figure 6b. S11 S12 S13 S11 S12 S13 Cflo Inverter connected to the grid Inverter connected to the floating capacitor (a) S11 S12 S13 S11 S12 S13 Cflo Inverter connected to the grid Inverter connected to the floating capacitor Under the occurrence of a voltage sag there will be an asymmetry the DC voltages of the inverters, increasing the number of different voltage vectors, as shown in Figure 4. Thus, considering that VDC1 reduces to 80% of their nominal value, it is possible to now verify that all the previous vectors do not present the same amplitude as seen by Figure 4a and Table 3. However, their amplitude and location are very near, making it possible to maintain the same strategy, previously described (for sector I, if the voltage of the floating capacitor is lower than the reference then the adopted voltage vector should be the 38, otherwise, it must be chosen the vector 20).  Under the occurrence of a voltage sag there will be an asymmetry the DC voltages of the inverters, increasing the number of different voltage vectors, as shown in Figure 4. Thus, considering that V DC1 reduces to 80% of their nominal value, it is possible to now verify that all the previous vectors do not present the same amplitude as seen by Figure 4a and Table 3. However, their amplitude and location are very near, making it possible to maintain the same strategy, previously described (for sector I, if the voltage of the floating capacitor is lower than the reference then the adopted voltage vector should be the 38, otherwise, it must be chosen the vector 20). During the voltage swell there is also an asymmetry of the DC inverter voltages. However, as in the case of the voltage sag, their amplitude and location are very nearly possible, even in this situation, to maintain the same strategy for the vector modulator.

Voltage Vector Modulator Implementation
As said before, the vector voltage modulator should be coordinated with the sliding surfaces of the motor controller. Thus, to establish a relationship between the vector to chosen and the control laws, several levels will be used, defined by a multilevel comparator. Since there are more different vectors in the α axis, when compared with the β axis, seven voltage levels for the law, associated with the α component, and five voltage levels for the β component are used (Figure 7). In accordance with the output of the comparators, the vector voltage to be applied is chosen. For example, considering that both components of the currents are much lower than the reference value, in this situation, the sliding surfaces (4) will give a high positive value. In this way, the vector with higher amplitude should be chosen. In a more generic way, the choice of the vector function of the sliding surfaces of the controller can be implemented through a look-up table, as presented in Table 4. with the α component, and five voltage levels for the β component are used (Figure 7). In accordance with the output of the comparators, the vector voltage to be applied is chosen. For example, considering that both components of the currents are much lower than the reference value, in this situation, the sliding surfaces (4) will give a high positive value. In this way, the vector with higher amplitude should be chosen. In a more generic way, the choice of the vector function of the sliding surfaces of the controller can be implemented through a look-up table, as presented in Table 4.

Simulation Results
To validate the proposed AC VSD and control system able to provide voltage sags ride-through, several digital computer simulations were performed. The simulation of the system was implemented in the program MATLAB/Simulink. The tests were performed on a 15 kW, 1445 rpm, 4-pole, and 50 Hz open-end winding induction motor. The induction motor parameters are given in Table 5 (they have been obtained by manufacturer's catalogue). Regarding the parameters

Simulation Results
To validate the proposed AC VSD and control system able to provide voltage sags ride-through, several digital computer simulations were performed. The simulation of the system was implemented in the program MATLAB/Simulink. The tests were performed on a 15 kW, 1445 rpm, 4-pole, and 50 Hz open-end winding induction motor. The induction motor parameters are given in Table 5 (they have been obtained by manufacturer's catalogue). Regarding the parameters used for the grid and power converter, they are presented in Table 6. The values of the capacitors were selected in accordance with capacitances needed in classical AC drives, with a diode rectifier and an inverter with some voltage sag resiliency.  To analyze the voltage ride-through capability of the proposed system, a test is performed where the VSD dual 3-phase VSIs work with the nominal grid voltage and then a voltage sag occurs. At the output of the of the diode rectifier, the voltage (V DC1 ) is near the maximum of the phase-phase grid voltage. Since, in this case, the grid phase-neutral voltage is 230 V, their voltage is near 550 V. For the voltage of the floating capacitor (V DC2 ), a reference of 550 V was defined. The choice of this reference was made in order to work with symmetric DC voltages in normal situations (voltage vectors given by Figure 3). In this test, the grid voltage decreases suddenly, from 100% of the nominal voltage (Vn) to 70% Vn at t =1.5 s and back to 100% Vn at t = 2.2 s. Figure 8 presents the time behavior of the waveforms of the DC sides of the two inverters. As can be seen, although the voltage of the DC side connected to the grid is affected, the voltage in the DC side connected to the floating capacitor is not affected and stays constant. This creates immunity to the voltage sags in the system. In fact, through Figure 9 it is possible to confirm that the three-phase motor currents will not be affected by this voltage sag. The multilevel voltage applied to winding 1 of the motor is presented in Figure 10. This figure shows that the multilevel voltage is maintained even during the voltage sag, in spite of the existence of the reduction of their amplitude. It should be stated that the control system and modulation was not changed during the voltage sag.    Another similar test was made, but in this case the grid voltage decreased suddenly from 100% of the nominal voltage (Vn) to 30% Vn at t = 1.5 s and back to 100% Vn at t = 2.2 s. The time behavior    Another similar test was made, but in this case the grid voltage decreased suddenly from 100% of the nominal voltage (Vn) to 30% Vn at t = 1.5 s and back to 100% Vn at t = 2.2 s. The time behavior Another similar test was made, but in this case the grid voltage decreased suddenly from 100% of the nominal voltage (Vn) to 30% Vn at t = 1.5 s and back to 100% Vn at t = 2.2 s. The time behavior of the waveforms of the DC sides of the two inverters is presented in Figure 11. In this case, it is possible to verify that voltage sags with very high depths lead to a high ripple in the voltage in the DC side connected to the floating capacitor. The voltage of the DC side connected to the grid is also strongly affected and also presents a high ripple. In this situation, the three-phase motor currents will be affected, as shown by Figure 12. This is due to the reduction of the available voltage that can be applied to the motor windings. In fact, due to this reduction, in this case the voltage is not enough to maintain the required amplitude of the currents. The multilevel voltage applied to winding 1 of the motor maintains their multilevel operation but with a higher reduction in their amplitude (Figure 13), confirming the cause for why the currents will not achieve the required value. However, this situation can be corrected by increasing the floating capacitor voltage, as shown in the next test. will be affected, as shown by Figure 12. This is due to the reduction of the available voltage that can be applied to the motor windings. In fact, due to this reduction, in this case the voltage is not enough to maintain the required amplitude of the currents. The multilevel voltage applied to winding 1 of the motor maintains their multilevel operation but with a higher reduction in their amplitude (Figure 13), confirming the cause for why the currents will not achieve the required value. However, this situation can be corrected by increasing the floating capacitor voltage, as shown in the next test.   to maintain the required amplitude of the currents. The multilevel voltage applied to winding 1 of the motor maintains their multilevel operation but with a higher reduction in their amplitude (Figure 13), confirming the cause for why the currents will not achieve the required value. However, this situation can be corrected by increasing the floating capacitor voltage, as shown in the next test.   In this test, the same conditions of the previous one were considered (same voltage sag, i.e., with a suddenly decrease of the voltage grid from 100% of the nominal voltage (Vn) to 30% Vn at t = 1.5 s and back to 100% Vn at t = 2.2 s), but in this case the reference of the floating capacitor voltage was changed. Thus, at t = 1.5 s, when the voltage sag occurs, the reference of the floating capacitor voltage was increased from 550 V to 650 V. The result of this test can be seen in Figure 14, which shows the time behavior of the waveforms of the DC sides of the two inverters. From this result it is possible to verify that the voltage in the floating capacitors will follow the reference and is stable all the time (maintaining a low voltage ripple). Moreover, it also shows the fast response to the sudden change in their reference. Regarding the three-phase currents, it is possible to verify that, in this case, they will not be affected as in the previous test ( Figure 15). This is due to the fact that the voltage applied to the windings is higher than the previous case, since the voltage in the floating capacitor In this test, the same conditions of the previous one were considered (same voltage sag, i.e., with a suddenly decrease of the voltage grid from 100% of the nominal voltage (Vn) to 30% Vn at t = 1.5 s and back to 100% Vn at t = 2.2 s), but in this case the reference of the floating capacitor voltage was changed. Thus, at t = 1.5 s, when the voltage sag occurs, the reference of the floating capacitor voltage was increased from 550 V to 650 V. The result of this test can be seen in Figure 14, which shows the time behavior of the waveforms of the DC sides of the two inverters. From this result it is possible to verify that the voltage in the floating capacitors will follow the reference and is stable all the time (maintaining a low voltage ripple). Moreover, it also shows the fast response to the sudden change in their reference. Regarding the three-phase currents, it is possible to verify that, in this case, they will not be affected as in the previous test ( Figure 15). This is due to the fact that the voltage applied to the windings is higher than the previous case, since the voltage in the floating capacitor has increased. This can be seen in Figure 16, wherein the multilevel voltage applied to winding 1 of the motor is presented.
with a suddenly decrease of the voltage grid from 100% of the nominal voltage (Vn) to 30% Vn at t = 1.5 s and back to 100% Vn at t = 2.2 s), but in this case the reference of the floating capacitor voltage was changed. Thus, at t = 1.5 s, when the voltage sag occurs, the reference of the floating capacitor voltage was increased from 550 V to 650 V. The result of this test can be seen in Figure 14, which shows the time behavior of the waveforms of the DC sides of the two inverters. From this result it is possible to verify that the voltage in the floating capacitors will follow the reference and is stable all the time (maintaining a low voltage ripple). Moreover, it also shows the fast response to the sudden change in their reference. Regarding the three-phase currents, it is possible to verify that, in this case, they will not be affected as in the previous test ( Figure 15). This is due to the fact that the voltage applied to the windings is higher than the previous case, since the voltage in the floating capacitor has increased. This can be seen in Figure 16, wherein the multilevel voltage applied to winding 1 of the motor is presented.

Conclusions
This work addressed the issue of voltage sags in AC VSDs with open-winding motors. To provide voltage sag ride-through capability, a multilevel inverter was proposed based in a Dual 3-phase VSIs structure connected to both sides of the open-end motor windings. The multilevel

Conclusions
This work addressed the issue of voltage sags in AC VSDs with open-winding motors. To provide voltage sag ride-through capability, a multilevel inverter was proposed based in a Dual 3-phase VSIs structure connected to both sides of the open-end motor windings. The multilevel inverter uses two 3-phase VSIs, but requires only a single DC source. A three-phase diode rectifier connected to the grid is used as the DC source, while a floating capacitor is used in the other 3-phase VSI. This topology allows higher voltages in the floating capacitor, when compared to the voltage at the output of the diode rectifier. Due to the increase of this voltage, it is possible to obtain immunity to deep voltage sags. This characteristic cannot be completely achieved by the classical AC drives as the boost function is not possible. The controller used for the VSD is based in the field oriented control. To control the motor flux and torque, a sliding mode controller for the AC currents was also proposed and its outputs were used to select vectors from a voltage vector modulator. The analysis of the space vectors gave the margins to obtain voltage sag ride-through capability. The proposed system does not require changing the controller when voltage sags occur, but just needs an increase of the voltage in the floating capacitor to achieve resiliency to deep voltage sags. The demonstration of the capabilities of the proposed VSD and the control system was made through several simulation test cases with a 15-hp motor. The obtained results confirm the immunity capabilities and requirements to successfully ride-through deep voltage sags. These tests were made without changing the control or modulation strategy. The results show that to obtain a ride-through voltage sag capability, just an increase in the floating capacitor voltage is needed. The results also show that, even with a voltage sag of 70%, the system has the capability to maintain the required current of the motor. This property can only be obtained through the capability of the system to increase the voltage to the floating capacitor during the voltage sag.