A Full-bridge Director Switches based Multilevel Converter with DC Fault Blocking Capability and Its Predictive Control Strategy

Voltage source converter-based high-voltage direct current transmission system (VSC-HVDC) technology has been widely used. However, traditional half-bridge sub module (HBSM)-based module multilevel converter (MMC) cannot block a DC fault current. This paper proposes that a full-bridge director switches based multi-level converter can offer features such as DC side fault blocking capability and is more compact and lower cost than other existing MMC topologies. A suitable predictive control strategy is proposed to minimize the error of the output AC current and the capacitor voltage of the sub-module while the director switches are operated in low-frequency mode. The validity of the proposed topology and control method is demonstrated based on simulation and experimental studies.


Introduction
The modular multilevel converter (MMC) has been accepted as a suitable solution for high-voltage and high-power application fields due to several inherent features [1][2][3][4][5][6][7][8]. However, blocking the DC fault current becomes a difficult problem because the anti-parallel diodes are still conducting after the insulated-gate bipolar transistors (IGBTs) of HBSM are turned off [9].
To solve this problem, recent research has highlighted a number of interesting converter topologies which combine the features of the multilevel output AC voltage waveform and DC fault blocking capacity [9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Full-bridge sub-module (FBSM) based MMC (F-MMC) is a basic configuration with DC fault current blocking capacity [10,11]. However, the DC fault current blocking capability comes at a cost of nearly doubling power losses and number of semiconductor devices. Some other type of sub-module is proposed instead of FBSM to make a further optimization in reducing the number of IGBTs, such as a clamp double sub-module (CDSM) proposed in [14,15] and a three-level cross-connected sub-module (TCSM) proposed in [16]. Several hybrid MMC topologies are also proposed, based on HBSM and those various types of sub-module [9,12,13,[16][17][18][19]23], for further reducing the cost and loss on the premise of having the DC fault blocking capacity, such as hybrid MMC based on CDSM and HBSM (CH-MMC). However, there are still some drawbacks, for example, as they are composed of a large number of sub-modules, the system needs to be more complicated and the converter station bulkier.
The alternate-arm multilevel converter (AAMC) based on the hybrid topology of HBSM and director switches is proposed in [20][21][22]. The AAMC further improves the traditional MMC topology by cutting the number of sub-modules, reducing DC bus voltage, and gaining the ability to block DC fault currents [22]. However, some features still have the possibility for further optimization, such as the size and cost of the overall system. One of the main technical challenges associated with the control of such a director switches based multilevel converter is to simultaneously keep the capacitor voltages balanced and provide good output current tracking performance, while the director switches keep switching in low frequency.
In order to further optimize the size and cost of the voltage source converter-based high-voltage direct current transmission system (VSC-HVDC) converter with the blocking ability of DC faults, this paper proposes a full bridge director switches based alternate-arm multi-level converter (FA-MMC) and a corresponding control strategy: 1.
The size and cost of the overall system can be significantly reduced by reducing the number of SM capacitors, IGBTs, and other related devices. In addition, an FA-MMC retains the ability to block DC-side faults since it uses H-bridge SMs as the AAMC. 2.
Similar to AAMC, a systematic multi-objective control method is needed for this kind of topology to minimize the error of output AC current and the capacitor voltage of the sub-module while the director switches are operated in low-frequency mode. A suitable predictive control strategy for this kind of topology is presented in this paper to achieve the flexibility to include the previously mentioned multiple system requirements.

Structure and Basic Operation
The basic circuit configuration of full-bridge director switches based modular multi-Level converter (FA-MMC) proposed in this paper is shown in Figure 1b. The proposed topology consists of a stack of H-bridge SMs and four director switches (S1-S4) made of series IGBTs or IGCTs. The ability of DC-side fault blocking is still retained since the H-bridge SMs structure is the same as the AAMC.
Energies 2018, 11, x FOR PEER REVIEW 2 of 22 optimization, such as the size and cost of the overall system. One of the main technical challenges associated with the control of such a director switches based multilevel converter is to simultaneously keep the capacitor voltages balanced and provide good output current tracking performance, while the director switches keep switching in low frequency. In order to further optimize the size and cost of the voltage source converter-based high-voltage direct current transmission system (VSC-HVDC) converter with the blocking ability of DC faults, this paper proposes a full bridge director switches based alternate-arm multi-level converter (FA-MMC) and a corresponding control strategy: 1 The size and cost of the overall system can be significantly reduced by reducing the number of SM capacitors, IGBTs, and other related devices. In addition, an FA-MMC retains the ability to block DC-side faults since it uses H-bridge SMs as the AAMC. 2 Similar to AAMC, a systematic multi-objective control method is needed for this kind of topology to minimize the error of output AC current and the capacitor voltage of the sub-module while the director switches are operated in low-frequency mode. A suitable predictive control strategy for this kind of topology is presented in this paper to achieve the flexibility to include the previously mentioned multiple system requirements.

Structure and Basic Operation
The basic circuit configuration of full-bridge director switches based modular multi-Level converter (FA-MMC) proposed in this paper is shown in Figure 1b. The proposed topology consists of a stack of H-bridge SMs and four director switches (S1-S4) made of series IGBTs or IGCTs. The ability of DC-side fault blocking is still retained since the H-bridge SMs structure is the same as the AAMC. The voltage of the director switches (Udirector in Figure 1b) is equal to the DC voltage (UDC in Figure 2) plus the voltage produced by the stack of H-bridge SMs which can be considered as only one controllable voltage source. Therefore, the voltage of director switches can be adjusted flexibly so that the switching of S1-S4 can switch at near to zero voltage. The ideal voltage waveform is shown in Figure 2a.
The working cycle of S1-S4 is synchronized with the output AC voltage. S1 and S4 are conducting and S2 and S3 are turned off while the output AC voltage (Uac in Figure 1b is in its positive half-cycle, in contrast, S2 and S3 are conducting and S1 and S4 are turned off while the output AC voltage is in its negative half-cycle. This ensures that the four director switches can switch at low-frequency and at the point of zero-voltage-crossing as shown in Figure 2a. These features lead to low switching losses, The voltage of the director switches (U director in Figure 1b) is equal to the DC voltage (U DC in Figure 2) plus the voltage produced by the stack of H-bridge SMs which can be considered as only one controllable voltage source. Therefore, the voltage of director switches can be adjusted flexibly so that the switching of S 1 -S 4 can switch at near to zero voltage. The ideal voltage waveform is shown in Figure 2a. and low demand for dynamic voltage sharing at the switching instant of the series switches, so that the system design has been simplified.
(a) (b) Figure 2. The voltage waveform and state of S1-S4: (a) without energy balance mode; (b) with energy balance mode.

Energy Balance
When the AC current flows through the stack of H-bridge sub module. In order to ensure the continuous operation of the system, the energy balance of the stack of H-bridges should be guaranteed. The amount of energy transferred from the AC side (EAC) and going to the DC side (EDC) should be equal over half the fundamental period and is given as For EAC to equal EDC, the relationship between the DC voltage magnitudes and AC voltage magnitudes mentioned in Equation (1) and (2) can be given as However, since the converters can't operate in the perfect given by Equation (3), an energy balancing strategy should be used.
Reference [22] presented two methods to achieve energy balance for AAMCs that can also be used in this topology: Overlap current and third harmonic current injection. In this paper the overlap current method is used to extend the period when the current directed from S1 and S4 to S2 and S3 is extended and S1-S4 are all conducting. The overlap current is used to exchange power between the sub module capacitors and the DC bus. The load current is only slightly affected, since the overlap time is very short and the inductance can smooth the change in current. Considering its effect on the grid current, the overlap time is determined to be less than 0.8 ms. The working cycle of S 1 -S 4 is synchronized with the output AC voltage. S 1 and S 4 are conducting and S 2 and S 3 are turned off while the output AC voltage (U ac in Figure 1b is in its positive half-cycle, in contrast, S 2 and S 3 are conducting and S 1 and S 4 are turned off while the output AC voltage is in its negative half-cycle. This ensures that the four director switches can switch at low-frequency and at the point of zero-voltage-crossing as shown in Figure 2a. These features lead to low switching losses, and low demand for dynamic voltage sharing at the switching instant of the series switches, so that the system design has been simplified.

Energy Balance
When the AC current flows through the stack of H-bridge sub module. In order to ensure the continuous operation of the system, the energy balance of the stack of H-bridges should be guaranteed. The amount of energy transferred from the AC side (E AC ) and going to the DC side (E DC ) should be equal over half the fundamental period and is given as For E AC to equal E DC , the relationship between the DC voltage magnitudes and AC voltage magnitudes mentioned in Equations (1) and (2) can be given as However, since the converters can't operate in the perfect given by Equation (3), an energy balancing strategy should be used.
Reference [22] presented two methods to achieve energy balance for AAMCs that can also be used in this topology: Overlap current and third harmonic current injection. In this paper the overlap current method is used to extend the period when the current directed from S 1 and S 4 to S 2 and S 3 is extended and S 1 -S 4 are all conducting. The overlap current is used to exchange power between the sub module capacitors and the DC bus. The load current is only slightly affected, since the overlap time is very short and the inductance can smooth the change in current. Considering its effect on the grid current, the overlap time is determined to be less than 0.8 ms.

Predictive Control Strategy
The control strategy of the proposed topology requires minimizing the error of the output current and DC voltage in each sub module, and, meanwhile, the director switches switching should be operated in low-frequency and zero-voltage switching mode.

Dynamic Modeling
Based on Figure 2, the governing equations of the single-phase FA-MMC can be shown as follows: As presented in Section 2, the value of L b is small and the voltage on it can be ignored; S 1 -S 4 have five switching state combinations depending on a switching function S d as shown in Table 1. The output voltage of each H-bridge sub module is equal to V ci (capacitor voltage of the ith sub module (i = 1, 2, · · · , n)), −V ci , or zero, depending on the switching states, and depends on a switching function Si The relationship between V ci and U DC is formalized as Based on Equation (16) and the basic principle, V PB is formalized as The dynamic capacitor voltage of the cells of the H-bridge sub module in Figure 1b is formalized as Energies 2019, 12, 91

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The relationship of currents is and i b in Figure 1b, which was also indicated by the switching function S d according to Table 1, is expressed as The switching states of director switches operate in an energy balancing mode, as mentioned in Table 1. As discussed previously, the current i b flows through the stack of H-bridge sub modules, buffer inductor, and director switch to the DC side, charging or discharging the capacitor of the H-bridge sub modules.
Only considering the basic operating mode, substituting Equations (5), (6), (9), and (11a) into (4), a dynamic model of the single-phase proposed topology in basic operating mode can be expressed as where S d = 1 or −1. Equation (12) can be simplified as where L = L b + L s .

Proposed Predictive Control
The predictive control strategy is proposed in this section based on the dynamic model of the FA-MMC presented above, the three primary targets of the predictive control strategy is achieved as follows:

AC-Side Current Control
Assuming a sampling period of T s , a discrete-time model of the FA-MMC AC-side current in basic operating mode based on Equation (3) is calculated by the value of S d could be assumed as a constant value during a short sampling period of T s . i s (k) is the actual AC current at time k and i s (k + 1) is the predicted AC current at time k + 1, U DC (k) can be considered as a constant value if the DC side voltage is controlled. Finally, V ci (k) is the capacitor voltage of the sub module i at time k.
To reduce the error between the predicted current and the reference current, a cost function associated with the current error is defined as where i sref is the reference current and i s (k + 1) is the predicted current obtained from Equation (14). Ideally, J i will be equal to its minimum value of (J min = 0 in Figure 4) if the AC-side current is controlled well.

Capacitor Voltage Balancing
Based on Equations (10) and (11), V ci (k + 1) can be deduced as where V ci (k) can be measured in real time. Another cost function for balancing the capacitor voltage of sub modules is given as where V ciref (k + 1) is the reference DC capacitor voltage of sub module i (with i between 1 and n), which can be equal to the average voltage of all cells (given as , and V ci (k + 1) is a predicted value, which can be obtained from Equation (16).
Consequently, by adding the above cost function together a combined cost function, which can simultaneously achieve the two main control objectives mentioned above is given as the linear combination where α and β are weighing factors, α is adjusted based on the cost contribution allocated to the error of AC-Side current, and β is adjusted based on the cost contribution allocated to the voltage deviations of sub module capacitors. The empirical method to determine the value of cost function is presented in [24]. Within each sampling and computing period T s , the combined cost function J all is re-calculated, and the best switching indicated to the minimum value for Equation (18) will be adopted for the current control cycle.

Director Switch Control
As presented in Figure 2a in Section 2.1, the state of director switches S 1 -S 4 at the next step should depend on the value of V AC . According to Equation (5), the necessary value of V AC at the current step can be expressed as However, the fluctuation of V AC (k + 1) due to differences between i sref (k + 1) and i s (k) during zero voltage crossings will lead to high frequency repeated switching of S 1 -S 4 , resulting in an increase of switching losses.
Therefore, a director switch control strategy should be taken considering the need to 1. Add the energy-balancing mode (S d = 0 in Table 1) in to achieve energy balancing of the stack of H-bridge by exchanging power with DC bus.

2.
Avoid repeated switching of the director switches.
Replacing i s (k) by i sref (k), the necessary value of V AC at the current step can be expressed as where i sref (k) is the reference value of the current of the current step. Voltage V ACref (k + 1), obtained by Equation (20), is a standard sine wave, which can avoid the fluctuation of V AC (k + 1) due to differences between i sref (k + 1) and i s (k) during zero voltage crossings. Finally, the implementation procedure of the proposed director switch control strategy is summarized in Part I of Figure 4. The schematic diagram of the control system is shown in Figure 3.

Simulation Results
This section evaluates the performance of the proposed FA-MMC and control method with a simulation. The simulation parameters are given in Table 2.  procedure of the proposed director switch control strategy is summarized in Part I of Figure 3. The schematic diagram of the control system is shown in Figure 4.

Simulation Results
This section evaluates the performance of the proposed FA-MMC and control method with a simulation. The simulation parameters are given in Table 2.  Figure 5 shows the voltage of the stack of H-bridges cells, the voltage across the director switches S 1 -S 4 , and the AC output voltage while the load current tracks the reference in steady-state operation. The simulation results are consistent with the working principle of the topology described in Figure 1b of Section 2. The voltage waveforms appear staircased because there are only two cells, while they would more closely resemble a sine curve with an increase in the number of cells. Figure 6 shows that the capacitor voltages in the two cells are averaged well and mostly under the control of MPC in basic operating mode. Further, they get closer to the given value U DC /n cell_FA in energy-balancing mode. Figure 7 shows the director switch control signal of S 1 -S 4 . It can be seen in Figure 7a that they all operated at a frequency of 100 Hz and achieved zero voltage switching under the director switch control strategy described in Part I of Figure 4. In contrast, when Part I of Figure 4 is removed, the director switch control signal, which is only determined by V AC (k + 1), is shown in Figure 6b. The difference in responses occurs because V ACref (k + 1) in Equation (20) is obviously a standard sine wave while the V AC (k + 1) is repeatedly crossing the zero voltage point as shown in Figure 8. This demonstrates the effectiveness of the director switch control strategy. Figure 9 reveals that the relation of the current across L b (I b in Figure 9) and the load current (Is in Figure 9) is similar to Equation (11a) in basic operating mode. The current across L b (I b in Figure 9) becomes an overlap current that charges or discharges the capacitor of the cells when S1-S4 are all conducting in energy balancing mode.   Figure 5 shows the voltage of the stack of H-bridges cells, the voltage across the director switches S1-S4, and the AC output voltage while the load current tracks the reference in steady-state operation. The simulation results are consistent with the working principle of the topology described in Figure 1b of Section 2. The voltage waveforms appear staircased because there are only two cells, while they would more closely resemble a sine curve with an increase in the number of cells. Figure 6 shows that the capacitor voltages in the two cells are averaged well and mostly under the control of MPC in basic operating mode. Further, they get closer to the given value UDC/ncell_FA in energy-balancing mode. Figure 7 shows the director switch control signal of S1-S4. It can be seen in Figure 7a that they all operated at a frequency of 100 Hz and achieved zero voltage switching under the director switch control strategy described in Part I of Figure 3. In contrast, when Part I of Figure 3 is removed, the director switch control signal, which is only determined by VAC(k + 1), is shown in Figure 6b. The difference in responses occurs because VACref(k + 1) in Equation (20) is obviously a standard sine wave while the VAC(k + 1) is repeatedly crossing the zero voltage point as shown in Figure 8. This demonstrates the effectiveness of the director switch control strategy. Figure 9 reveals that the relation of the current across Lb (Ib in Figure 9) and the load current (Is in Figure 9) is similar to Equation (11a) in basic operating mode. The current across Lb (Ib in Figure 9) becomes an overlap current that charges or discharges the capacitor of the cells when S1-S4 are all conducting in energy balancing mode.

Operating Performance under a Transient-State Condition
To test the dynamic performance, a sudden change in the reference current is set at 0.04 s, and the behavior of the system is shown in Figure 10. It can be seen that the current tracked the reference value well. The time of reference tracking (from 600 A to −600 A) is less than 0.01 ms as shown in Figure 10b, and the output AC voltage waveform is shown in Figure 11.
The capacitor voltage is shown in Figure 12. It can be seen that the capacitor voltage of the two sub-module remains balanced after a sudden change of load current. Figure 12b shows that there is a deviation in the beginning, but is averaged well immediately by the predictive control strategy after 1 ms. Figure 13 shows the states of the director switches at the instant of the sudden change of load current, demonstrating that the director switches are controlled well and operated in low-frequency mode.

Operating Performance under a Transient-State Condition
To test the dynamic performance, a sudden change in the reference current is set at 0.04 s, and the behavior of the system is shown in Figure 10. It can be seen that the current tracked the reference value well. The time of reference tracking (from 600 A to −600 A) is less than 0.01 ms as shown in Figure 10b, and the output AC voltage waveform is shown in Figure 11.
The capacitor voltage is shown in Figure 12. It can be seen that the capacitor voltage of the two sub-module remains balanced after a sudden change of load current. Figure 12b shows that there is a deviation in the beginning, but is averaged well immediately by the predictive control strategy after 1 ms.

Operating Performance under a Transient-State Condition
To test the dynamic performance, a sudden change in the reference current is set at 0.04 s, and the behavior of the system is shown in Figure 10. It can be seen that the current tracked the reference value well. The time of reference tracking (from 600 A to −600 A) is less than 0.01 ms as shown in Figure 10b, and the output AC voltage waveform is shown in Figure 11.
The capacitor voltage is shown in Figure 12. It can be seen that the capacitor voltage of the two sub-module remains balanced after a sudden change of load current. Figure 12b shows that there is a deviation in the beginning, but is averaged well immediately by the predictive control strategy after 1 ms. Figure 13 shows the states of the director switches at the instant of the sudden change of load current, demonstrating that the director switches are controlled well and operated in low-frequency mode.     S2 S3 S4 Figure 13. Control signal of S1-S4.

Operating Performance under a DC Fault
Having verified the normal operation of the converter, the model was tested under a DC fault. A three-phase model was built, and a DC fault was induced at 0.04 s. The blocking time is set to be 3 ms after the fault current is detected considering the sensor delay time. Figure 14 shows that the voltage of the cell capacitor is kept at 1.5 kV and the AC current follows the given value before 0.04 s. When a DC short-circuit happens at 0.04 s, the direction of current is reversed and the AC side current rises at first because during the sensor delay, the capacitors discharge and current flows from the AC side to the DC side. After 3 ms, when the converter station is blocked, the DC and AC side currents gradually reduce to zero along with the charging of the capacitor.

Operating Performance under a DC Fault
Having verified the normal operation of the converter, the model was tested under a DC fault. A three-phase model was built, and a DC fault was induced at 0.04 s. The blocking time is set to be 3 ms after the fault current is detected considering the sensor delay time. Figure 14 shows that the voltage of the cell capacitor is kept at 1.5 kV and the AC current follows the given value before 0.04 s. When a DC short-circuit happens at 0.04 s, the direction of current is reversed and the AC side current rises at first because during the sensor delay, the capacitors discharge and current flows from the AC side to the DC side. After 3 ms, when the converter station is blocked, the DC and AC side currents gradually reduce to zero along with the charging of the capacitor. S2 S3 S4 Figure 13. Control signal of S1-S4.

Operating Performance under a DC Fault
Having verified the normal operation of the converter, the model was tested under a DC fault. A three-phase model was built, and a DC fault was induced at 0.04 s. The blocking time is set to be 3 ms after the fault current is detected considering the sensor delay time. Figure 14 shows that the voltage of the cell capacitor is kept at 1.5 kV and the AC current follows the given value before 0.04 s. When a DC short-circuit happens at 0.04 s, the direction of current is reversed and the AC side current rises at first because during the sensor delay, the capacitors discharge and current flows from the AC side to the DC side. After 3 ms, when the converter station is blocked, the DC and AC side currents gradually reduce to zero along with the charging of the capacitor.

Experimental Results
Experiments on an FA-MMC-based inverter were also carried out to verify the proposed topology and test the predictive control strategy. The parameters for the experiment are listed in Table 3. A photo of the inverter is shown in Figure 15 and an IGBT is utilized as the power switch. The main control algorithms were implemented in a combination of a DSP and FPGA. The DC-link voltage was obtained via a three-phase autotransformer.

Experimental Results
Experiments on an FA-MMC-based inverter were also carried out to verify the proposed topology and test the predictive control strategy. The parameters for the experiment are listed in Table 3. A photo of the inverter is shown in Figure 15 and an IGBT is utilized as the power switch. The main control algorithms were implemented in a combination of a DSP and FPGA. The DC-link voltage was obtained via a three-phase autotransformer. (c)

Experimental Results
Experiments on an FA-MMC-based inverter were also carried out to verify the proposed topology and test the predictive control strategy. The parameters for the experiment are listed in Table 3. A photo of the inverter is shown in Figure 15 and an IGBT is utilized as the power switch. The main control algorithms were implemented in a combination of a DSP and FPGA. The DC-link voltage was obtained via a three-phase autotransformer.    To test the system balance ability, a 100 Ω resistor was shunted to capacitor SM2. The topology worked in this unbalanced condition by appropriately setting the value of the weighting factor β, which is used to balance the capacitor voltage of the two SMs to zero. In this paper, we set the weighting factor α to a fixed value of 50, and set weighting factor β to 0 or 100 to compare the waveforms. Figure 16 shows the capacitor voltages of the two SMs. At first, the capacitor voltage of SM1 is lower than SM2, and the fluctuation is larger due to the unbalanced condition. After giving a suitable value to weighting factor β, each cell capacitor voltage is well regulated to their reference value and the fluctuation of the two cells is also the same. To test the system balance ability, a 100 Ω resistor was shunted to capacitor SM2. The topology worked in this unbalanced condition by appropriately setting the value of the weighting factor β, which is used to balance the capacitor voltage of the two SMs to zero. In this paper, we set the weighting factor α to a fixed value of 50, and set weighting factor β to 0 or 100 to compare the waveforms. Figure 16 shows the capacitor voltages of the two SMs. At first, the capacitor voltage of SM1 is lower than SM2, and the fluctuation is larger due to the unbalanced condition. After giving a suitable value to weighting factor β, each cell capacitor voltage is well regulated to their reference value and the fluctuation of the two cells is also the same.   Figure 18 we can see that the voltage ripple of the two cell capacitors does not affect the current, apparently due to the robustness of the predictive control. When the weighting factor β is set to 100, meaning that the capacitor voltage balance is considered as a control goal, only a slight distortion is introduced into the output current.  Figures 17 and 18 show the output current and voltage of this topology, which are both measured during balanced and unbalanced operation. From Figure 18 we can see that the voltage ripple of the two cell capacitors does not affect the current, apparently due to the robustness of the predictive control. When the weighting factor β is set to 100, meaning that the capacitor voltage balance is considered as a control goal, only a slight distortion is introduced into the output current.  To test the dynamic performance, the behavior of the FA-MMC and corresponding control method for a step in the angle of the reference current is shown in Figure 19. The waveforms show that the voltage changed quickly to drive the current to its new reference value and that the current is well-tracked. Figure 19 also shows that the dynamic capacitor voltage waveform is not influenced by the step in the angle of the reference current. Figure 20 shows a detailed view of the output voltage and current for a step in the angle of the reference current. The reference tracking of the proposed method that considered the possible switching states adjacent to VAC(k + 1) is fast, because extreme voltage changes are possible. The results are similar to simulation results.  To test the dynamic performance, the behavior of the FA-MMC and corresponding control method for a step in the angle of the reference current is shown in Figure 19. The waveforms show that the voltage changed quickly to drive the current to its new reference value and that the current is well-tracked. Figure 19 also shows that the dynamic capacitor voltage waveform is not influenced by the step in the angle of the reference current. Figure 20 shows a detailed view of the output voltage and current for a step in the angle of the reference current. The reference tracking of the proposed method that considered the possible switching states adjacent to VAC(k + 1) is fast, because extreme voltage changes are possible. The results are similar to simulation results. To test the dynamic performance, the behavior of the FA-MMC and corresponding control method for a step in the angle of the reference current is shown in Figure 19. The waveforms show that the voltage changed quickly to drive the current to its new reference value and that the current is well-tracked. Figure 19 also shows that the dynamic capacitor voltage waveform is not influenced by the step in the angle of the reference current. Figure 20 shows a detailed view of the output voltage and current for a step in the angle of the reference current. The reference tracking of the proposed method that considered the possible switching states adjacent to V AC (k + 1) is fast, because extreme voltage changes are possible. The results are similar to simulation results.

DC Fault Blocking Capacity
When a DC-side short-circuit happens, with all IGBTs turned off, the director switches and stack of H-bridges behave as a number of uncontrolled diodes connecting with all DC capacitors in the cells connected in series, as shown in Figure 21. The equivalent capacitor value in Figure 21 can be expressed as

DC Fault Blocking Capacity
When a DC-side short-circuit happens, with all IGBTs turned off, the director switches and stack of H-bridges behave as a number of uncontrolled diodes connecting with all DC capacitors in the cells connected in series, as shown in Figure 21. The equivalent capacitor value in Figure 21 can be expressed as

DC Fault Blocking Capacity
When a DC-side short-circuit happens, with all IGBTs turned off, the director switches and stack of H-bridges behave as a number of uncontrolled diodes connecting with all DC capacitors in the cells connected in series, as shown in Figure 21. The equivalent capacitor value in Figure 21 can be expressed as C e = C/n cell_FA (21) where C is the capacitance of the capacitor in each cell and ncell_FA is the number of cells in one phase of the FA-MMC. The AC source charges the equivalent capacitor and inductors (including the L s , L b , L d ) through the DC fault current, thus, limiting the rising rate of the fault current. Consequently, the value of U ce will rise rapidly, and the DC fault current will be blocked.  (21) where C is the capacitance of the capacitor in each cell and ncell_FA is the number of cells in one phase of the FA-MMC. The AC source charges the equivalent capacitor and inductors (including the Ls, Lb, Ld) through the DC fault current, thus, limiting the rising rate of the fault current. Consequently, the value of Uce will rise rapidly, and the DC fault current will be blocked.

Number of Sub-module and IGBTs
Equation (3) shows that the DC bus voltage is lower than the peak value of output AC voltage by 27% in FA-MMC topology. This implies that the voltage rating of the director switches should be at least equal to the peak value of output AC voltage since they have to support higher voltages.
Assuming that the maximum allowable working voltage rating of the IGBTs is equal to the voltage rating of the DC capacitors in the sub-modules, the number of sub-modules of the proposed FA-MMC is given by  (23) where nS, the number of IGBT in S1-S4, is given by Given the same AC output voltage, we also can deduce the DC voltage, number of cells, and IGBTs needed in an AAMC. The relationship between DC and AC voltage magnitudes in an AAMC, which has been derived in [22], can be expressed as

Number of Sub-module and IGBTs
Equation (3) shows that the DC bus voltage is lower than the peak value of output AC voltage by 27% in FA-MMC topology. This implies that the voltage rating of the director switches should be at least equal to the peak value of output AC voltage since they have to support higher voltages.
Assuming that the maximum allowable working voltage rating of the IGBTs is equal to the voltage rating of the DC capacitors in the sub-modules, the number of sub-modules of the proposed FA-MMC is given by where U RATED is the voltage rating of the IGBTs. The number of IGBTs of each phase of the FA-MMC is given by where n S , the number of IGBT in S 1 -S 4 , is given by Given the same AC output voltage, we also can deduce the DC voltage, number of cells, and IGBTs needed in an AAMC. The relationship between DC and AC voltage magnitudes in an AAMC, which has been derived in [22], can be expressed as It can be seen from Equation (3) and (25) that the FA-MMC can reduce the DC bus voltage by half with the same AC output voltage and same active/reactive power flow compared with an AAMC.
Considering the sum of the sub-module capacitor voltage must be greater than the peak value of the line-to-line voltage to achieve DC current blocking capability, the number of sub-modules of an AAMC can be expressed as But, it only has two direct switches, so considering Equation (24) and (26), the number of IGBTs of a single-phase AAMC is given by To summarize, the number of IGBTs of the FA-MMC is less than that of the AAMC, and the DC voltage and number of sub-modules of the FA-MMC is nearly half those of the AAMC, leading to smaller size, less need for insulation, and lower cost. And the comparison results of the number of IGBTs and sub-module capacitors between FA-MMC, AAMC and various MMC topologies mentioned in the introduction is shown in Table 4.

Efficiency Analysis
To evaluate the power losses of the FA-MMC and AAMC, a simple loss calculation method for module multilevel converter is adopted [25]. And the result is shown in Table 5. To summarize, the losses of FA2MC increases slightly compared with AAMC, but it is still significantly lower than other types of MMC topologies.

Comprehensive Comparison with Other Topological Structures
According to the above analysis, a comprehensive comparison between the full-bridge MMC, half-bridge MMC, CH-MMC, A2MC, and FA-MMC is summarized in Table 6, where more "+" means the corresponding topology performs better in the corresponding characteristic. It can be seen in Table 6 that the FA-MMC has advantages in several aspects compared with the other topologies.

Conclusions
In this paper, a FA-MMC topology and its predictive control scheme have been proposed. The effectiveness of the proposed topology and proposed control strategy under various operating conditions are evaluated based on simulation studies in the PowerSIM environment and experiments, and the comparisons with other topological structures are also given. Through the analysis and demonstration mentioned above, the characteristics of this topology and its predictive control strategy are summarized as follows: (1) The sub-module capacitor number of FA-MMC reduce significantly while connecting to the same AC voltage level and power level, results in a more compact structure; (2) Further, it reduces the number of needed IGBTs while retaining the ability to block a DC-side fault compared with other topologies, so that the cost of the system is reduced; (3) The algorithm the algorithm has been proved to be able to achieve multiple control objectives of FA-MMC simultaneously (i.e., capacitor voltages balancing and ac-side currents control). The developed control strategy also contains a director switch control function so that the director switch maintains operation in low-frequency and zero voltage switching mode.

Conflicts of Interest:
The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.

E AC
The amount of energy transferred from AC side over half the fundamental period E DC The amount of energy going to DC side over half the fundamental period. The current through Lb C The capacitor value of cell S d Switching function of director switch L s Filter inductor I s The current through Ls T s Sampling period J all , J i , J vc Cost function α, β Weighting factor