Direct Digital Design of PIDF Controllers with ComPlex Zeros for DC-DC Buck Converters

: This paper presents a new direct digital design method for discrete proportional integral derivative PID + ﬁlter (PIDF) controllers employed in DC-DC buck converters. The considered controller structure results in a proper transfer function which has the advantage of being directly implementable by a microcontroller algorithm. Secondly, it can be written as an Inﬁnite Impulse Response (IIR) digital ﬁlter. Thirdly, the further degree of freedom introduced by the low pass ﬁlter of the transfer function can be used to satisfy additional speciﬁcations. A new design procedure is proposed, which consists of the conjunction of the pole-zero cancellation method with an analytical design control methodology based on inversion formulae. These two methods are employed to reduce the negative effects introduced by the complex poles in the transfer function of the buck converter while exactly satisfying steady-state speciﬁcations on the tracking error and frequency domain requirements on the phase margin and on the gain crossover frequency. The proposed approach allows the designer to assign a closed-loop bandwidth without constraints imposed by the resonance frequency of the buck converter. The response under step variation of the reference value, and the disturbance rejection capability of the proposed control technique under load variations are also evaluated in real-time implementation by using the Arduino DUE board, and compared with other methods.


Introduction
Many industrial applications need the transformation of a constant DC voltage source to a constant value even under load variation, such as photovoltaic systems, mobile power supply equipment, DC supply systems, etc. The buck converter is one of the most widely utilized DC-DC converters, because of its simplicity, high efficiency, and low cost, see e.g., [1], and therefore each improvement has potentially a major economic and commercial impact. However, the presence of its nonlinear characteristics in the switching behavior and the saturation of the duty cycle render the output voltage control a challenging task. Numerous control strategies have been proposed for the voltage regulation of the buck converter. Each of them has advantages and disadvantages, and the selection of the most appropriate one depends mainly on the design task at hand. A brief review of the main digital control techniques can be found in [2]. Among these, the non-linear sliding mode control, which leads to fast transient response under load variation and high robustness, is worth mentioning [3,4]. However, the control performance is reduced by the introduction of high frequency oscillations around the sliding surface, the so-called chattering. Another practical alternative for the voltage regulation of the buck converter is the fuzzy logic control. This non-linear adaptive technique digital implementation using the Atmel SAM3X8E microcontroller based on the ARM ® Cortex ® -M3 processor on an Arduino Due board. The experimental results have been analyzed and compared with classical PID control solutions.
The paper is organized as follows. The digital control schemes and discrete buck converter model are described in Section 2. In Section 3, we propose the discrete PIDF controller with complex conjugate zeros. The control problem and the proposed design solution are presented in Section 4. We describe the simulated and experimental results of the proposed DC-DC buck converter control and the performance comparison with other methods in Section 5. Conclusions and remarks will end the paper.

Digital Control Schemes and Discrete Buck Converter Model
The DC-DC buck converter is a step-down switching converter extensively described, e.g., in [21]. The block scheme of the digital voltage mode control and the buck converter circuit considered in this paper are shown in Figure 1. It is assumed that the converter operates in continuous-conduction mode (CCM). In the buck converter scheme, Vout is the output voltage, Vin is the input voltage, L is the filter inductance, C is the filter capacitance, R is the load resistance, RL and RC denote, respectively, the parasitic series resistances of the inductor and capacitor. Moreover, rn(z) represents the reference digital signal, while yn(z) denotes the sampled output of the process. The sampled signal is obtained by the analog-to-digital converter (ADC) with sampling period Ts. The tracking error signal en(z) = rn(z)−yn(z) is processed by a discrete-time compensator C(z) to generate the control signal dn(z). The Digital Pulse Width Modulator (DPWM) converts dn(z) into the corresponding analog duty cycle with values between 0 and 1 according to the desired ratio of Vout/Vin, and modulates the PWM signal to drive the buck converter switch.
The transfer function of the discrete plant model G(z) is the Z-transform of the product of the continuous-time converter transfer function G(s) and the transfer function of the zero-order hold: (1) Notice that in the hardware device the output voltage of the buck converter is driven into the admissible range of the ADC input voltage by a constant sensor gain H; the resulting output signal of the ADC is then multiplied by the factor 1/H to be compared with the reference value rn. In (1) the factors H·(1/H) = 1 have been simplified and omitted. According to the buck converter averaged model and Equation (2) of [21], the transfer function of the buck converter: In the buck converter scheme, V out is the output voltage, V in is the input voltage, L is the filter inductance, C is the filter capacitance, R is the load resistance, R L and R C denote, respectively, the parasitic series resistances of the inductor and capacitor. Moreover, r n (z) represents the reference digital signal, while y n (z) denotes the sampled output of the process. The sampled signal is obtained by the analog-to-digital converter (ADC) with sampling period T s . The tracking error signal e n (z) = r n (z)−y n (z) is processed by a discrete-time compensator C(z) to generate the control signal d n (z). The Digital Pulse Width Modulator (DPWM) converts d n (z) into the corresponding analog duty cycle with values between 0 and 1 according to the desired ratio of V out /V in , and modulates the PWM signal to drive the buck converter switch.
The transfer function of the discrete plant model G(z) is the Z-transform of the product of the continuous-time converter transfer function G(s) and the transfer function of the zero-order hold: Notice that in the hardware device the output voltage of the buck converter is driven into the admissible range of the ADC input voltage by a constant sensor gain H; the resulting output signal of the ADC is then multiplied by the factor 1/H to be compared with the reference value r n . In (1) the  (2) of [21], the transfer function of the buck converter: is a second-order low-pass filter, with a left-half complex plane zero introduced by the equivalent series resistance of the filter capacitance. The mathematical averaged model is obtained by the following input/state/output equations, where the diode and transistor conduction losses have been neglected [22]. where: The discrete model of the buck converter is: where: a = e −ξω n T s cos ω n T s 1 − ξ 2 , and it can be obtained by applying the definition of the Z-transform to the series plants H 0 (s)G(s)H. Notice that G(z) is characterized the following two complex conjugate poles: Indeed, from (1) it follows that: where: Expanding R(s) into partial fractions we have: Applying the standard manipulation theorems of the Z-transform to R(s) we have: It follows that (8) can be written as: which can be rewritten as in (4) using (5)-(7).

The Proposed Discrete PIDF Controller with Complex Conjugate Zeros
The controller presented in this paper is a discrete PIDF controller, described by the following transfer function: when: τ Ts , the controller (9) represents the discrete pole-zero mapping transformation with the sampling period T s of the following continuous-time PIDF controller: Here K i is the integral gain, δ is the damping ratio and 1/τ is the natural frequency of the controller zeros, and: is a parameter that depends on the high frequency controller gain, which is defined as: The PIDF controller (10) is equivalent to the classical parallel PIDF controller: In fact, equivalent parameters for (11) can be obtained from δ, β, K i , τ by equating (10) and (11): the resulting proportional gain, and the integral, the derivative and the filter time constants are shown in the following Equation (12): Notice that when β > 1 and δ ≥ 1 the PIDF controller (10) reduces to a series PID controller, when 0 < β < 1 the PIDF controller has complex conjugate zeros, and when β = 1 and δ = 1 the PIDF controller becomes a PI controller, see [19].
Interestingly, the controller (9) can be written as a digital biquadratic filter: where which has the clear advantage of being directly implementable on a microcontroller by using the difference equation:

The Design Problem and the Proposed Design Solution
For control design purposes, the control system scheme can be simplified as in Figure 2, where G(z) and C(z) are given by (1) and (9), respectively, while L(z) denotes the loop gain transfer function L(z) = C(z)G(z).
The PIDF controller (10) is equivalent to the classical parallel PIDF controller: In fact, equivalent parameters for (11) can be obtained from δ, β, Ki, τ by equating (10) and (11): the resulting proportional gain, and the integral, the derivative and the filter time constants are shown in the following Equation (12): Notice that when β > 1 and δ ≥ 1 the PIDF controller (10) reduces to a series PID controller, when 0 < β < 1 the PIDF controller has complex conjugate zeros, and when β = 1 and δ = 1 the PIDF controller becomes a PI controller, see [19].
Interestingly, the controller (9) can be written as a digital biquadratic filter: where: which has the clear advantage of being directly implementable on a microcontroller by using the difference equation:

The Design Problem and the Proposed Design Solution
For control design purposes, the control system scheme can be simplified as in Figure 2, where G(z) and C(z) are given by (1) and (9), respectively, while L(z) denotes the loop gain transfer function L(z) = C(z)G(z).

Pole/Zero Compensation Method
The PIDF controller (9) introduces a pair of complex conjugate zeros, which can be placed to achieve pole/zero compensation. The PIDF parameters can be selected as follows: where ξ and ω n are the parameters of the buck converter described in (3). In this way, the transfer function of the controller can be factorized into two parts. The zeros and the integrator: are completely determined by the zero/pole cancellation. The remaining factor is: (17) and it comprises the parameters that are yet to be assigned. Thus, we can consider a new control problem where the controller is C(z), while the former factor is part of the plant, whose transfer function then becomes:

Discrete Inversion Formulae Method
The design method based on the so-called "inversion formulae" consists in a set of closed-form expressions that deliver the parameters of the controller to exactly satisfy specifications on the gain crossover frequency ω g , phase margin Φ m and/or gain margin G m . In most cases, these specifications are satisfied if the frequency response associated with the loop gain transfer function: L(e jωT s ) = C(e jωTs ) G(e jωT s ) at frequency ω g satisfies: In other words, the design method based on the inversion formulae is a way of constraining the loop gain polar plot to cross a specific point of the complex plane. In practice, in the vast majority of the situations that are interesting in practice this goal alone is sufficient to guarantee that the specifications on the phase (or gain) margin and crossover frequency are met, see [15] for further details.
The classical feedback design problem is to find a controller C(z) that satisfies the steady-state a zero position error specification, and such that the gain crossover frequency and the phase margin of the loop gain transfer function L(z) are, respectively, ω g and Φ m .
The first step of the design method consists in guaranteeing that the steady-state requirement is met. In most situations, the pole at z = 1 of the controller is sufficient to automatically satisfy the steady-state requirements. However, in some cases, the number of poles at z = 1 of the plant and the single pole at z = 1of the controller are not sufficient to meet the desired static requirements, and the factor K i in (9) must be chosen accordingly. For example, this is the case of a type-0 plant as the considered buck converter when the steady-state specifications not only require zero position error, but also that the velocity error (i.e., the tracking error in the response of a ramp) be equal to (or smaller than) a given non-zero constant. In the considered case specifications on the steady-state error do not lead to constraints in the value of the integral constant. Let L(z) = C(z) G(z) be the loop gain transfer function. We define: The solvability of the feedback design problem amounts to solving the complex equation: in the unknowns K i > 0 and β d > 0. The closed-form solution to this problem is given in the following theorem: Theorem 1. The values of K i and β d that solve the control problem are given by the following expressions: Proof. From (18), the controller (17) has to be designed in such a way that: holds. The frequency response of (17) for ω = ω g can be written in Cartesian form as: Equating (24) and (23) directly leads to (21) and (22).

Remark 1.
It is easy to verify that the parameters β d and K i in (21) and in (22) are positive if and only if: and one of the following conditions holds: or: and one of the following conditions holds: Note that, if one of the previous conditions fails, the required frequency-domain constraints are infeasible. In other words, the devised inversion formulae provide a solution whenever a feasible solution exists.
It is worth stressing that the proposed approach is based on closed-form expressions that deliver a discrete-time PIDF controller that satisfies exactly the design specification. This is clearly a major advantage since the imposed stability margin is guaranteed, and it is not subject to variations induced by the discretization method.

Design Problem
The aim of this section is to apply the proposed designed procedure to the buck converter circuit with the parameters given in Table 1. The steady state requirement is zero position error, while the phase margin and the gain crossover frequency of the open loop frequency response are required to be equal to Φ m = 85 • and ω g = 1600 rad/s, respectively. Table 1. Circuit parameters of the buck converter.

Proposed Solution Using Discrete-Time PIDF Controller
The discrete plant (4) of the buck converter with the parameters given in Table 1 and with sampling period T s equal to 5 × 10 −5 s is: The same result can be obtained using the zero-order-hold discretization method on the transfer function of the continuous time averaged model (2): The steady-state requirements are automatically satisfied by the pole at z = 1 of the discrete PIDF controller. Its zeros can be designed to cancel the complex poles of G(z) at 0.96 ± j 0.18 by selecting δ d = 0.982 and ω d = 0.97 rad/s in (9). It follows that: The complex value G(e jωgTs ) = 8.94 e j 1.54 determines the gain M g = 1/8.94 = 0.11 that the controller has to introduce at frequency ω g , and the phase ϕ g = 85 • + 180 • + 88.4 • = 353.4 • of the controller at ω g needed to satisfy the design specification on the phase margin. The parameters of the PIDF controller (9) that solves the problem are β d = 3.22, K i = 0.078, and follow directly from (21)(22). The resulting PIDF transfer function is: which can also be rewritten as:  Figure 5 showing the effectiveness of the control in the time domain. Notice that selecting a different value of the sampling time T s causes the complex conjugate poles of the discrete plant to shift in the complex plane. In this case, new values of δ d and ω d can be computed according to (9) as functions of T s to exactly cancel the shifted poles.
with a 1 = −1.303, a 2 = 0.3033, b 0 = 0.0781, b 1 = −0.1496, b 2 = 0.0743. Applying this discrete controller, the design requirements are exactly satisfied, as one can observe by the Nyquist and Bode plots of the open loop frequency response L(e jωΤs ) shown in red in Figures 3-4. The step response of the controlled system is plotted in red in Figure 5 showing the effectiveness of the control in the time domain. Notice that selecting a different value of the sampling time T s causes the complex conjugate poles of the discrete plant to shift in the complex plane. In this case, new values of δ d and ω d can be computed according to (9) as functions of T s to exactly cancel the shifted poles.

Simulation and Experimental Results
The proposed control system for the buck converter regulation has been extensively simulated in MATLAB-Simulink ® using the model shown in Figure 6. As a first step, the PIDF controller has been tested introducing the discrete transfer function block contained in the Simulink ® library. Then, this block has been substituted with the Infinite Impulse Response (IIR) digital filter shown in Figure  7, which has the advantage to be directly implementable by a microcontroller algorithm.

Simulation and Experimental Results
The proposed control system for the buck converter regulation has been extensively simulated in MATLAB-Simulink ® using the model shown in Figure 6. As a first step, the PIDF controller has been tested introducing the discrete transfer function block contained in the Simulink ® library. Then, this block has been substituted with the Infinite Impulse Response (IIR) digital filter shown in Figure 7, which has the advantage to be directly implementable by a microcontroller algorithm.

Simulation and Experimental Results
The proposed control system for the buck converter regulation has been extensively simulated in MATLAB-Simulink ® using the model shown in Figure 6. As a first step, the PIDF controller has been tested introducing the discrete transfer function block contained in the Simulink ® library. Then, this block has been substituted with the Infinite Impulse Response (IIR) digital filter shown in Figure  7, which has the advantage to be directly implementable by a microcontroller algorithm.   The control signal dn, the inductor current and the output voltage of the converter and inductor under step reference variations from 0 V to 12 V are shown in Figure 8 from which the smoothness and monotonicity of the response achieved with our method can be clearly observed, as well as the notching effect of the complex conjugate zeros, which is well-visible in the first part of the transient response of the control signal. It is also worth noting that the simulated response and the experimental one exhibit a very good matching, demonstrating that our model is effectively descriptive of the real-world buck converter. The control signal d n , the inductor current and the output voltage of the converter and inductor under step reference variations from 0 V to 12 V are shown in Figure 8 from which the smoothness and monotonicity of the response achieved with our method can be clearly observed, as well as the notching effect of the complex conjugate zeros, which is well-visible in the first part of the transient response of the control signal. It is also worth noting that the simulated response and the experimental one exhibit a very good matching, demonstrating that our model is effectively descriptive of the real-world buck converter. under step reference variations from 0 V to 12 V are shown in Figure 8 from which the smoothness and monotonicity of the response achieved with our method can be clearly observed, as well as the notching effect of the complex conjugate zeros, which is well-visible in the first part of the transient response of the control signal. It is also worth noting that the simulated response and the experimental one exhibit a very good matching, demonstrating that our model is effectively descriptive of the real-world buck converter. An experimental hardware device has been built to verify the proposed method for the DC-DC buck converter. It is composed by the buck converter and an Arduino Due development board, based on a 32-bit Atmel SAM3X8E ARM ® Cortex ® M3 CPU, see Figure 9. The main components of the buck converter circuit have been selected as shown in Table 1. An interrupt routine is generated every T s = 5 × 10 −5 s. This routine starts the ADC conversion of the output signal of the converter and computes the duty cycle of the PWM control signal. Figure 10  An experimental hardware device has been built to verify the proposed method for the DC-DC buck converter. It is composed by the buck converter and an Arduino Due development board, based on a 32-bit Atmel SAM3X8E ARM ® Cortex ® M3 CPU, see Figure 9. The main components of the buck converter circuit have been selected as shown in Table 1.
under step reference variations from 0 V to 12 V are shown in Figure 8 from which the smoothness and monotonicity of the response achieved with our method can be clearly observed, as well as the notching effect of the complex conjugate zeros, which is well-visible in the first part of the transient response of the control signal. It is also worth noting that the simulated response and the experimental one exhibit a very good matching, demonstrating that our model is effectively descriptive of the real-world buck converter. An experimental hardware device has been built to verify the proposed method for the DC-DC buck converter. It is composed by the buck converter and an Arduino Due development board, based on a 32-bit Atmel SAM3X8E ARM ® Cortex ® M3 CPU, see Figure 9. The main components of the buck converter circuit have been selected as shown in Table 1.  An interrupt routine is generated every T s = 5 × 10 −5 s. This routine starts the ADC conversion of the output signal of the converter and computes the duty cycle of the PWM control signal. Figure 10 represents the difference Equation (14) of the PIDF controller using the Direct-Form II Transposed structure of a Biquad Cascade IIR Filter shown in Figure 7.  The output voltage of the converter and inductor current I L under step reference variations from 0 V to 12 V are shown in Figure 11. The measure of I L has been obtained using the analog transducer LEM 6−NP with a 5V supply and a galvanic isolation between the primary and the secondary circuit. The experimental results confirm the behavior already observed in the simulations: the output voltage reaches the desired value in a monotonic fashion, and the inductor current remains always well below the saturation value. A zoom of the inductor current sensor output in steady-state condition is shown in Figure 12 from which the regularity of the PWM duty cycle when the system has reached the new steady-state can be observed. This is a consequence of the selected bandwidth, which is large enough to obtain a fast set point tracking, but narrow enough to avoid the amplification of high frequency noise and discontinuities due to the PWM behavior. Note that assigning such bandwidth without cancelling the complex conjugate poles would result in large The output voltage of the converter and inductor current I L under step reference variations from 0 V to 12 V are shown in Figure 11. The measure of I L has been obtained using the analog transducer LEM 6−NP with a 5V supply and a galvanic isolation between the primary and the secondary circuit. The experimental results confirm the behavior already observed in the simulations: the output voltage reaches the desired value in a monotonic fashion, and the inductor current remains always well below the saturation value. A zoom of the inductor current sensor output in steady-state condition is shown in Figure 12 from which the regularity of the PWM duty cycle when the system has reached the new steady-state can be observed. This is a consequence of the selected bandwidth, which is large enough to obtain a fast set point tracking, but narrow enough to avoid the amplification of high frequency noise and discontinuities due to the PWM behavior. Note that assigning such bandwidth without cancelling the complex conjugate poles would result in large oscillations due to the presence of the resonance peak in the closed-loop system. The output voltage of the converter and inductor current I L under step reference variations from 0 V to 12 V are shown in Figure 11. The measure of I L has been obtained using the analog transducer LEM 6−NP with a 5V supply and a galvanic isolation between the primary and the secondary circuit. The experimental results confirm the behavior already observed in the simulations: the output voltage reaches the desired value in a monotonic fashion, and the inductor current remains always well below the saturation value. A zoom of the inductor current sensor output in steady-state condition is shown in Figure 12 from which the regularity of the PWM duty cycle when the system has reached the new steady-state can be observed. This is a consequence of the selected bandwidth, which is large enough to obtain a fast set point tracking, but narrow enough to avoid the amplification of high frequency noise and discontinuities due to the PWM behavior. Note that assigning such bandwidth without cancelling the complex conjugate poles would result in large oscillations due to the presence of the resonance peak in the closed-loop system.    The output voltage of the converter and inductor current I L under step reference variations from 0 V to 12 V are shown in Figure 11. The measure of I L has been obtained using the analog transducer LEM 6−NP with a 5V supply and a galvanic isolation between the primary and the secondary circuit. The experimental results confirm the behavior already observed in the simulations: the output voltage reaches the desired value in a monotonic fashion, and the inductor current remains always well below the saturation value. A zoom of the inductor current sensor output in steady-state condition is shown in Figure 12 from which the regularity of the PWM duty cycle when the system has reached the new steady-state can be observed. This is a consequence of the selected bandwidth, which is large enough to obtain a fast set point tracking, but narrow enough to avoid the amplification of high frequency noise and discontinuities due to the PWM behavior. Note that assigning such bandwidth without cancelling the complex conjugate poles would result in large oscillations due to the presence of the resonance peak in the closed-loop system.

Comparison with Other Methods
There are various design techniques for determining the parameters of a PID controller when the mathematical model of the plant is explicitly available. For a comparison with the proposed design method, three classical PID tuning techniques have been considered, see Table 2. The first controller has been obtained using the Internal Model Control IMC-Chien method described in [23], and by neglecting the capacitor and inductor resistances in (2). The second has been obtained by placing one zero of the PID controller an octave below the cut-off frequency, approximately at 480 rad/s, while the other zero has been placed at 7 × 10 3 rad/s, see [12]. The third controller has been obtained by selecting the PID zeros to approximately cancel the complex conjugate poles of the converter at the cut-off frequency and a phase margin equal to 95 • , see [10]. The considered continuous-time PID controllers have been simulated via the Simulink ® PID(s) block which implements a PID controller in the form: The MATLAB-Simulink ® PID(s) model uses a lowpass filter in the derivative term to obtain a proper transfer function. The default value of the coefficient N in the filter is set at 100. Using this value in (32), all the considered PID controls generate large oscillations during the step response transient. These oscillations are considerably reduced by setting the coefficient N of the filter to the value N = 200,000. It is clear that the time constant of the filter is a critical component in the design of a PID controller and that a systematic design method should be taken into account. Accordingly, in our method, the time constant of the filter is selected to achieve the desired closed-loop system performance, and it is not designed by using trial-and-error, empiric or rule-of-thumb methods.
For the practical implementation of the controller on the Arduino board, the continuous-time PID controllers are converted to the discrete-time by using the backward Euler's integration method, as suggested in [10]. The discrete control algorithm will therefore implement the causal difference equation: Moreover, an anti-windup filter based on the conditional integration method (see [24] for details) has been implemented in order to minimize the detrimental effect of the large saturation resulting from the techniques listed in Table 3. The simulated step responses of these three methods in the continuous-time are shown in Figure 13. The simulated step response using the IMC-Chien method is very fast, with a settling time of 0.2 ms. However, the peak of the resulting control signal is approximately 80.
There are various design techniques for determining the parameters of a PID controller when the mathematical model of the plant is explicitly available. For a comparison with the proposed design method, three classical PID tuning techniques have been considered, see Table 2. The first controller has been obtained using the Internal Model Control IMC-Chien method described in [23], and by neglecting the capacitor and inductor resistances in (2). The second has been obtained by placing one zero of the PID controller an octave below the cut-off frequency, approximately at 480 rad/s, while the other zero has been placed at 7×10 3 rad/s, see [12]. The third controller has been obtained by selecting the PID zeros to approximately cancel the complex conjugate poles of the converter at the cut-off frequency and a phase margin equal to 95°, see [10]. The considered continuous-time PID controllers have been simulated via the Simulink ® PID(s) block which implements a PID controller in the form: The MATLAB-Simulink ® PID(s) model uses a lowpass filter in the derivative term to obtain a proper transfer function. The default value of the coefficient N in the filter is set at 100. Using this value in (32), all the considered PID controls generate large oscillations during the step response transient. These oscillations are considerably reduced by setting the coefficient N of the filter to the value N = 200,000. It is clear that the time constant of the filter is a critical component in the design of a PID controller and that a systematic design method should be taken into account. Accordingly, in our method, the time constant of the filter is selected to achieve the desired closed-loop system performance, and it is not designed by using trial-and-error, empiric or rule-of-thumb methods.
For the practical implementation of the controller on the Arduino board, the continuous-time PID controllers are converted to the discrete-time by using the backward Euler's integration method, as suggested in [10]. The discrete control algorithm will therefore implement the causal difference equation Moreover, an anti-windup filter based on the conditional integration method (see [24] for details) has been implemented in order to minimize the detrimental effect of the large saturation resulting from the techniques listed in Table 3.
The simulated step responses of these three methods in the continuous-time are shown in Figure 13. The simulated step response using the IMC-Chien method is very fast, with a settling time of 0.2 ms. However, the peak of the resulting control signal is approximately 80.  On the other hand, the saturation of the duty cycle range [0,1] leads to an oscillatory behavior in the experimental output voltage, see Figures 14b. In fact, the resulting settling time is 20 times greater than the one obtained in the simulated test. Moreover, a steady-state ripple in the output voltage and in the inductor current is present because of the excessively aggressive tuning.
The simulated continuous-time step response using the pole placement method exhibits a rise time of 8.1 × 10 −5 s, a settling time of 4.2 ms, and an overshoot equal to 6%. As in the previous case, the control signal reaches a very high value, in this case with a peak of nearly 180. The converter signals obtained using this control method in the experimental hardware device are shown in Figures 14c. The main drawback of this type of control is the large steady-state ripple in the output voltage, see [10]. This is due to an excessively large closed-loop bandwidth that results in an aggressive control action which tries to compensate the high frequency noise. The saturation of the duty cycle in the range [0-1] leads to an ON-OFF behavior in the hardware device and high power dissipation both during the transient response and in the maintenance of the steady-state. Note also that the voltage ripple is unsuitable for most sensitive electronic equipment and the resulting current may cause heating and damage of capacitors over time, see [25].
The simulated continuous-time step response using the pole-zero cancellation method has a rise time of 4.1 × 10 −4 s, a settling time of 0.7 ms. The peak of the control signal is 48, which is considerably lower than the ones obtained with the previously described techniques, but still orders of magnitude above the saturation level. The corresponding experimental results are shown in Figures 14d. Notice that the steady-state output ripple is not present using this type of control because of the less aggressive tuning of the parameters, which also results in a lower peak of the control variable. However, the non-linear saturation of the control signal is not considered in (2). As a consequence, the zeros of the controller only partially compensate the oscillatory effects of the buck converter poles in the transient period. It follows that the settling time rises to 4 ms in practice, and the experimental output voltage exhibits an oscillatory behavior with an overshoot of 20-30%. On the other hand, the saturation of the duty cycle range [0,1] leads to an oscillatory behavior in the experimental output voltage, see Figure 14b. In fact, the resulting settling time is 20 times greater than the one obtained in the simulated test. Moreover, a steady-state ripple in the output voltage and in the inductor current is present because of the excessively aggressive tuning.
The simulated continuous-time step response using the pole placement method exhibits a rise time of 8.1 × 10 −5 s, a settling time of 4.2 ms, and an overshoot equal to 6%. As in the previous case, the control signal reaches a very high value, in this case with a peak of nearly 180. The converter signals obtained using this control method in the experimental hardware device are shown in Figure 14c. The main drawback of this type of control is the large steady-state ripple in the output voltage, see [10]. This is due to an excessively large closed-loop bandwidth that results in an aggressive control action which tries to compensate the high frequency noise. The saturation of the duty cycle in the range [0,1] leads to an ON-OFF behavior in the hardware device and high power dissipation both during the transient response and in the maintenance of the steady-state. Note also that the voltage ripple is unsuitable for most sensitive electronic equipment and the resulting current may cause heating and damage of capacitors over time, see [25].
The simulated continuous-time step response using the pole-zero cancellation method has a rise time of 4.1 × 10 −4 s, a settling time of 0.7 ms. The peak of the control signal is 48, which is considerably lower than the ones obtained with the previously described techniques, but still orders of magnitude above the saturation level. The corresponding experimental results are shown in Figure 14d. Notice that the steady-state output ripple is not present using this type of control because of the less aggressive tuning of the parameters, which also results in a lower peak of the control variable. However, the non-linear saturation of the control signal is not considered in (2). As a consequence, the zeros of the controller only partially compensate the oscillatory effects of the buck converter poles in the transient period. It follows that the settling time rises to 4 ms in practice, and the experimental output voltage exhibits an oscillatory behavior with an overshoot of 20-30%. Figure 13. Simulated step responses using IMC-Chien method, the pole placement method and pole-zero control method in the continuous-time case: output voltages and control signals. On the other hand, the saturation of the duty cycle range [0,1] leads to an oscillatory behavior in the experimental output voltage, see Figures 14b. In fact, the resulting settling time is 20 times greater than the one obtained in the simulated test. Moreover, a steady-state ripple in the output voltage and in the inductor current is present because of the excessively aggressive tuning.
The simulated continuous-time step response using the pole placement method exhibits a rise time of 8.1 × 10 −5 s, a settling time of 4.2 ms, and an overshoot equal to 6%. As in the previous case, the control signal reaches a very high value, in this case with a peak of nearly 180. The converter signals obtained using this control method in the experimental hardware device are shown in Figures 14c. The main drawback of this type of control is the large steady-state ripple in the output voltage, see [10]. This is due to an excessively large closed-loop bandwidth that results in an aggressive control action which tries to compensate the high frequency noise. The saturation of the duty cycle in the range [0-1] leads to an ON-OFF behavior in the hardware device and high power dissipation both during the transient response and in the maintenance of the steady-state. Note also that the voltage ripple is unsuitable for most sensitive electronic equipment and the resulting current may cause heating and damage of capacitors over time, see [25].
The simulated continuous-time step response using the pole-zero cancellation method has a rise time of 4.1 × 10 −4 s, a settling time of 0.7 ms. The peak of the control signal is 48, which is considerably lower than the ones obtained with the previously described techniques, but still orders of magnitude above the saturation level. The corresponding experimental results are shown in Figures 14d. Notice that the steady-state output ripple is not present using this type of control because of the less aggressive tuning of the parameters, which also results in a lower peak of the control variable. However, the non-linear saturation of the control signal is not considered in (2). As a consequence, the zeros of the controller only partially compensate the oscillatory effects of the buck converter poles in the transient period. It follows that the settling time rises to 4 ms in practice, and the experimental output voltage exhibits an oscillatory behavior with an overshoot of 20-30%. Compared to all the considered methods, the proposed control procedure leads to a good matching between simulated and experimental results, due to the design which is carried out directly in discrete-time via closed-form formulae. As such, the phase margin that we obtain with the discrete PIDF controller is exactly the design one. On the contrary, other approaches are based on the design of the controller in the discrete domain, and eventually, on the discretization of the obtained continuous controller. However, this results in a discrete controller that often delivers a phase margin considerably different from the one that would have ideally been obtained in the Compared to all the considered methods, the proposed control procedure leads to a good matching between simulated and experimental results, due to the design which is carried out directly in discrete-time via closed-form formulae. As such, the phase margin that we obtain with the discrete PIDF controller is exactly the design one. On the contrary, other approaches are based on the design of the controller in the discrete domain, and eventually, on the discretization of the obtained continuous controller. However, this results in a discrete controller that often delivers a phase margin considerably different from the one that would have ideally been obtained in the continuous time, see Table 2, where the phase margins obtained from the considered methods and a discrete PID of the following form are presented:

The Proposed Control under Output Load and Converter Parameters Variations
For the widespread diffusion of a control technique in practical applications, robustness to parameter variation and model uncertainty is clearly a key feature. For this reason, we study the behavior of the output voltage under different load resistance variations. Experimental results of the step load testing under different output loads (10 Ω, 20 Ω and 30 Ω) are shown in Figure 15a. Notice that the output voltage presents an almost overlapping behavior in the three considered cases, confirming that the control is not affected by load variation in the range ±50% of the nominal value, see Table 1. Other experimental results on load variations from 20 Ω to 10 Ω and from 20 Ω to 30 Ω in steady-state condition are shown in Figure 15b. Notice that the proposed control system promptly stabilizes the voltage output with negligible undershoot and overshoot, thus providing a good performance in the case of load variations. Moreover, the set-point step response remains virtually the same irrespectively of the load resistance.  Table 2, where the phase margins obtained from the considered methods and a discrete PID of the following form are presented:

The Proposed Control under Output Load and Converter Parameters Variations
For the widespread diffusion of a control technique in practical applications, robustness to parameter variation and model uncertainty is clearly a key feature. For this reason, we study the behavior of the output voltage under different load resistance variations. Experimental results of the step load testing under different output loads (10 Ω, 20 Ω and 30 Ω) are shown in Figure 15a. Notice that the output voltage presents an almost overlapping behavior in the three considered cases, confirming that the control is not affected by load variation in the range ±50% of the nominal value, see Table 1. Other experimental results on load variations from 20 Ω to 10 Ω and from 20 Ω to 30 Ω in steady-state condition are shown in Figure 15b. Notice that the proposed control system promptly stabilizes the voltage output with negligible undershoot and overshoot, thus providing a good performance in the case of load variations. Moreover, the set-point step response remains virtually the same irrespectively of the load resistance. While load variations are due to normal operations of the buck converter, other parameters of the circuit of the converter, such as the inductance and capacitance, may vary as well as a result of the uncertainties affecting the production of the electrical components. In particular, the resonance frequency is directly related to the inductance and capacitance. In fact, since R>>RC and R>>RL, in practice we have: Therefore, the inductor current and the output voltage under variations of the capacitor and inductor in the buck converter are also studied, and the results are shown in Figures 16 and 17. The While load variations are due to normal operations of the buck converter, other parameters of the circuit of the converter, such as the inductance and capacitance, may vary as well as a result of the uncertainties affecting the production of the electrical components. In particular, the resonance frequency is directly related to the inductance and capacitance. In fact, since R>>R C and R>>R L , in practice we have: Therefore, the inductor current and the output voltage under variations of the capacitor and inductor in the buck converter are also studied, and the results are shown in Figures 16 and 17.
The proposed system delivers a good robust performance under parameter variations, and a monotonic response is obtained with all the considered combinations. proposed system delivers a good robust performance under parameter variations, and a monotonic response is obtained with all the considered combinations. Step responses with the proposed design procedure when the model value of the capacitor is 100 μF−20%, 100 μF+20%.

Figure 17.
Step responses with the proposed design procedure when the model value of the inductor is set to 680 μH−10% and 680 μH+10%.

Conclusions
A new design framework for the control of buck converters has been presented in this paper. The proposed methodology is based on the discrete PIDF controller, and hinges on a direct design procedure that can be easily implemented in any non-specific platform. Indeed, the proposed methodology delivers a closed-form solution to meet suitable phase margin and gain crossover frequency values without a simulation environment. Moreover, the proposed design procedure and the discrete control algorithm are simple, they require small tuning times and they can be implemented by inexpensive microcontrollers.
Numerical and experimental verifications confirm that the proposed method goes well beyond the well-known zero/pole cancellation strategy and other control methods available in the literature. Indeed, the proposed approach enables the designer to assign an arbitrary bandwidth, which is therefore no longer constrained by the resonant peak. This aspect leads to a double benefit. On the one hand, this method avoids an excessively large bandwidth, which would result in noise/ripple amplification and ultimately in an increase in power consumption and a decrease in the component life. On the other hand, this method avoids the discretization problem that derives from discretizing Step responses with the proposed design procedure when the model value of the capacitor is 100 µF−20%, 100 µF+20%. proposed system delivers a good robust performance under parameter variations, and a monotonic response is obtained with all the considered combinations. Step responses with the proposed design procedure when the model value of the capacitor is 100 μF−20%, 100 μF+20%.

Figure 17.
Step responses with the proposed design procedure when the model value of the inductor is set to 680 μH−10% and 680 μH+10%.

Conclusions
A new design framework for the control of buck converters has been presented in this paper. The proposed methodology is based on the discrete PIDF controller, and hinges on a direct design procedure that can be easily implemented in any non-specific platform. Indeed, the proposed methodology delivers a closed-form solution to meet suitable phase margin and gain crossover frequency values without a simulation environment. Moreover, the proposed design procedure and the discrete control algorithm are simple, they require small tuning times and they can be implemented by inexpensive microcontrollers.
Numerical and experimental verifications confirm that the proposed method goes well beyond the well-known zero/pole cancellation strategy and other control methods available in the literature. Indeed, the proposed approach enables the designer to assign an arbitrary bandwidth, which is therefore no longer constrained by the resonant peak. This aspect leads to a double benefit. On the one hand, this method avoids an excessively large bandwidth, which would result in noise/ripple amplification and ultimately in an increase in power consumption and a decrease in the component life. On the other hand, this method avoids the discretization problem that derives from discretizing Step responses with the proposed design procedure when the model value of the inductor is set to 680 µH−10% and 680 µH+10%.

Conclusions
A new design framework for the control of buck converters has been presented in this paper. The proposed methodology is based on the discrete PIDF controller, and hinges on a direct design procedure that can be easily implemented in any non-specific platform. Indeed, the proposed methodology delivers a closed-form solution to meet suitable phase margin and gain crossover frequency values without a simulation environment. Moreover, the proposed design procedure and the discrete control algorithm are simple, they require small tuning times and they can be implemented by inexpensive microcontrollers.
Numerical and experimental verifications confirm that the proposed method goes well beyond the well-known zero/pole cancellation strategy and other control methods available in the literature. Indeed, the proposed approach enables the designer to assign an arbitrary bandwidth, which is therefore no longer constrained by the resonant peak. This aspect leads to a double benefit. On the one hand, this method avoids an excessively large bandwidth, which would result in noise/ripple amplification and ultimately in an increase in power consumption and a decrease in the component life. On the other hand, this method avoids the discretization problem that derives from discretizing a controller which assigns a bandwidth that is too large with respect to the sampling period. This, in particular, avoids detrimental effects on the stability margin due to the discretization. Moreover, experimental results confirm that the selection of large phase margin with the direct proposed method delivers a good system performance under load variations and plant uncertainties.
Author Contributions: S.C. provided for theoretical developments, simulations and experimental tests, L.N. and F.P. contributed to theoretical developments and manuscript organization, G.G. contributed to experimental results and manuscript finalization.
Funding: This research received no external funding.

Conflicts of Interest:
The authors declare no conflict of interest.

Abbreviations
The following abbreviations and symbols are used in this manuscript: Gain crossover frequency ω n Buck converter natural frequency 1/τ Natural frequency of the controller zeros